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   1
   2 /*
   3  * Local APIC virtualization
   4  *
   5  * Copyright (C) 2006 Qumranet, Inc.
   6  * Copyright (C) 2007 Novell
   7  * Copyright (C) 2007 Intel
   8  *
   9  * Authors:
  10  *   Dor Laor <dor.laor@qumranet.com>
  11  *   Gregory Haskins <ghaskins@novell.com>
  12  *   Yaozu (Eddie) Dong <eddie.dong@intel.com>
  13  *
  14  * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
  15  *
  16  * This work is licensed under the terms of the GNU GPL, version 2.  See
  17  * the COPYING file in the top-level directory.
  18  */
  19
  20 #include <linux/kvm_host.h>
  21 #include <linux/kvm.h>
  22 #include <linux/mm.h>
  23 #include <linux/highmem.h>
  24 #include <linux/smp.h>
  25 #include <linux/hrtimer.h>
  26 #include <linux/io.h>
  27 #include <linux/module.h>
  28 #include <linux/math64.h>
  29 #include <asm/processor.h>
  30 #include <asm/msr.h>
  31 #include <asm/page.h>
  32 #include <asm/current.h>
  33 #include <asm/apicdef.h>
  34 #include <asm/atomic.h>
  35 #include "kvm_cache_regs.h"
  36 #include "irq.h"
  37 #include "trace.h"
  38
  39 #ifndef CONFIG_X86_64
  40 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
  41 #else
  42 #define mod_64(x, y) ((x) % (y))
  43 #endif
  44
  45 #define PRId64 "d"
  46 #define PRIx64 "llx"
  47 #define PRIu64 "u"
  48 #define PRIo64 "o"
  49
  50 #define APIC_BUS_CYCLE_NS 1
  51
  52 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
  53 #define apic_debug(fmt, arg...)
  54
  55 #define APIC_LVT_NUM                    6
  56 /* 14 is the version for Xeon and Pentium 8.4.8*/
  57 #define APIC_VERSION                    (0x14UL | ((APIC_LVT_NUM - 1) << 16))
  58 #define LAPIC_MMIO_LENGTH               (1 << 12)
  59 /* followed define is not in apicdef.h */
  60 #define APIC_SHORT_MASK                 0xc0000
  61 #define APIC_DEST_NOSHORT               0x0
  62 #define APIC_DEST_MASK                  0x800
  63 #define MAX_APIC_VECTOR                 256
  64
  65 #define VEC_POS(v) ((v) & (32 - 1))
  66 #define REG_POS(v) (((v) >> 5) << 4)
  67
  68 static inline u32 apic_get_reg(struct kvm_lapic *apic, int reg_off)
  69 {
  70         return *((u32 *) (apic->regs + reg_off));
  71 }
  72
  73 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
  74 {
  75         *((u32 *) (apic->regs + reg_off)) = val;
  76 }
  77
  78 static inline int apic_test_and_set_vector(int vec, void *bitmap)
  79 {
  80         return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  81 }
  82
  83 static inline int apic_test_and_clear_vector(int vec, void *bitmap)
  84 {
  85         return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  86 }
  87
  88 static inline void apic_set_vector(int vec, void *bitmap)
  89 {
  90         set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  91 }
  92
  93 static inline void apic_clear_vector(int vec, void *bitmap)
  94 {
  95         clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  96 }
  97
  98 static inline int apic_hw_enabled(struct kvm_lapic *apic)
  99 {
 100         return (apic)->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
 101 }
 102
 103 static inline int  apic_sw_enabled(struct kvm_lapic *apic)
 104 {
 105         return apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED;
 106 }
 107
 108 static inline int apic_enabled(struct kvm_lapic *apic)
 109 {
 110         return apic_sw_enabled(apic) && apic_hw_enabled(apic);
 111 }
 112
 113 #define LVT_MASK        \
 114         (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
 115
 116 #define LINT_MASK       \
 117         (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
 118          APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
 119
 120 static inline int kvm_apic_id(struct kvm_lapic *apic)
 121 {
 122         return (apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
 123 }
 124
 125 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
 126 {
 127         return !(apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
 128 }
 129
 130 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
 131 {
 132         return apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
 133 }
 134
 135 static inline int apic_lvtt_period(struct kvm_lapic *apic)
 136 {
 137         return apic_get_reg(apic, APIC_LVTT) & APIC_LVT_TIMER_PERIODIC;
 138 }
 139
 140 static inline int apic_lvt_nmi_mode(u32 lvt_val)
 141 {
 142         return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
 143 }
 144
 145 static unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
 146         LVT_MASK | APIC_LVT_TIMER_PERIODIC,     /* LVTT */
 147         LVT_MASK | APIC_MODE_MASK,      /* LVTTHMR */
 148         LVT_MASK | APIC_MODE_MASK,      /* LVTPC */
 149         LINT_MASK, LINT_MASK,   /* LVT0-1 */
 150         LVT_MASK                /* LVTERR */
 151 };
 152
 153 static int find_highest_vector(void *bitmap)
 154 {
 155         u32 *word = bitmap;
 156         int word_offset = MAX_APIC_VECTOR >> 5;
 157
 158         while ((word_offset != 0) && (word[(--word_offset) << 2] == 0))
 159                 continue;
 160
 161         if (likely(!word_offset && !word[0]))
 162                 return -1;
 163         else
 164                 return fls(word[word_offset << 2]) - 1 + (word_offset << 5);
 165 }
 166
 167 static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic)
 168 {
 169         apic->irr_pending = true;
 170         return apic_test_and_set_vector(vec, apic->regs + APIC_IRR);
 171 }
 172
 173 static inline int apic_search_irr(struct kvm_lapic *apic)
 174 {
 175         return find_highest_vector(apic->regs + APIC_IRR);
 176 }
 177
 178 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
 179 {
 180         int result;
 181
 182         if (!apic->irr_pending)
 183                 return -1;
 184
 185         result = apic_search_irr(apic);
 186         ASSERT(result == -1 || result >= 16);
 187
 188         return result;
 189 }
 190
 191 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
 192 {
 193         apic->irr_pending = false;
 194         apic_clear_vector(vec, apic->regs + APIC_IRR);
 195         if (apic_search_irr(apic) != -1)
 196                 apic->irr_pending = true;
 197 }
 198
 199 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
 200 {
 201         struct kvm_lapic *apic = vcpu->arch.apic;
 202         int highest_irr;
 203
 204         /* This may race with setting of irr in __apic_accept_irq() and
 205          * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
 206          * will cause vmexit immediately and the value will be recalculated
 207          * on the next vmentry.
 208          */
 209         if (!apic)
 210                 return 0;
 211         highest_irr = apic_find_highest_irr(apic);
 212
 213         return highest_irr;
 214 }
 215
 216 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 217                              int vector, int level, int trig_mode);
 218
 219 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq)
 220 {
 221         struct kvm_lapic *apic = vcpu->arch.apic;
 222
 223         return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
 224                         irq->level, irq->trig_mode);
 225 }
 226
 227 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
 228 {
 229         int result;
 230
 231         result = find_highest_vector(apic->regs + APIC_ISR);
 232         ASSERT(result == -1 || result >= 16);
 233
 234         return result;
 235 }
 236
 237 static void apic_update_ppr(struct kvm_lapic *apic)
 238 {
 239         u32 tpr, isrv, ppr;
 240         int isr;
 241
 242         tpr = apic_get_reg(apic, APIC_TASKPRI);
 243         isr = apic_find_highest_isr(apic);
 244         isrv = (isr != -1) ? isr : 0;
 245
 246         if ((tpr & 0xf0) >= (isrv & 0xf0))
 247                 ppr = tpr & 0xff;
 248         else
 249                 ppr = isrv & 0xf0;
 250
 251         apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
 252                    apic, ppr, isr, isrv);
 253
 254         apic_set_reg(apic, APIC_PROCPRI, ppr);
 255 }
 256
 257 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
 258 {
 259         apic_set_reg(apic, APIC_TASKPRI, tpr);
 260         apic_update_ppr(apic);
 261 }
 262
 263 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest)
 264 {
 265         return dest == 0xff || kvm_apic_id(apic) == dest;
 266 }
 267
 268 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
 269 {
 270         int result = 0;
 271         u8 logical_id;
 272
 273         logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR));
 274
 275         switch (apic_get_reg(apic, APIC_DFR)) {
 276         case APIC_DFR_FLAT:
 277                 if (logical_id & mda)
 278                         result = 1;
 279                 break;
 280         case APIC_DFR_CLUSTER:
 281                 if (((logical_id >> 4) == (mda >> 0x4))
 282                     && (logical_id & mda & 0xf))
 283                         result = 1;
 284                 break;
 285         default:
 286                 printk(KERN_WARNING "Bad DFR vcpu %d: %08x\n",
 287                        apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR));
 288                 break;
 289         }
 290
 291         return result;
 292 }
 293
 294 int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
 295                            int short_hand, int dest, int dest_mode)
 296 {
 297         int result = 0;
 298         struct kvm_lapic *target = vcpu->arch.apic;
 299
 300         apic_debug("target %p, source %p, dest 0x%x, "
 301                    "dest_mode 0x%x, short_hand 0x%x\n",
 302                    target, source, dest, dest_mode, short_hand);
 303
 304         ASSERT(!target);
 305         switch (short_hand) {
 306         case APIC_DEST_NOSHORT:
 307                 if (dest_mode == 0)
 308                         /* Physical mode. */
 309                         result = kvm_apic_match_physical_addr(target, dest);
 310                 else
 311                         /* Logical mode. */
 312                         result = kvm_apic_match_logical_addr(target, dest);
 313                 break;
 314         case APIC_DEST_SELF:
 315                 result = (target == source);
 316                 break;
 317         case APIC_DEST_ALLINC:
 318                 result = 1;
 319                 break;
 320         case APIC_DEST_ALLBUT:
 321                 result = (target != source);
 322                 break;
 323         default:
 324                 printk(KERN_WARNING "Bad dest shorthand value %x\n",
 325                        short_hand);
 326                 break;
 327         }
 328
 329         return result;
 330 }
 331
 332 /*
 333  * Add a pending IRQ into lapic.
 334  * Return 1 if successfully added and 0 if discarded.
 335  */
 336 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 337                              int vector, int level, int trig_mode)
 338 {
 339         int result = 0;
 340         struct kvm_vcpu *vcpu = apic->vcpu;
 341
 342         switch (delivery_mode) {
 343         case APIC_DM_LOWEST:
 344                 vcpu->arch.apic_arb_prio++;
 345         case APIC_DM_FIXED:
 346                 /* FIXME add logic for vcpu on reset */
 347                 if (unlikely(!apic_enabled(apic)))
 348                         break;
 349
 350                 result = !apic_test_and_set_irr(vector, apic);
 351                 if (!result) {
 352                         if (trig_mode)
 353                                 apic_debug("level trig mode repeatedly for "
 354                                                 "vector %d", vector);
 355                         break;
 356                 }
 357
 358                 if (trig_mode) {
 359                         apic_debug("level trig mode for vector %d", vector);
 360                         apic_set_vector(vector, apic->regs + APIC_TMR);
 361                 } else
 362                         apic_clear_vector(vector, apic->regs + APIC_TMR);
 363                 kvm_vcpu_kick(vcpu);
 364                 break;
 365
 366         case APIC_DM_REMRD:
 367                 printk(KERN_DEBUG "Ignoring delivery mode 3\n");
 368                 break;
 369
 370         case APIC_DM_SMI:
 371                 printk(KERN_DEBUG "Ignoring guest SMI\n");
 372                 break;
 373
 374         case APIC_DM_NMI:
 375                 result = 1;
 376                 kvm_inject_nmi(vcpu);
 377                 kvm_vcpu_kick(vcpu);
 378                 break;
 379
 380         case APIC_DM_INIT:
 381                 if (level) {
 382                         result = 1;
 383                         if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
 384                                 printk(KERN_DEBUG
 385                                        "INIT on a runnable vcpu %d\n",
 386                                        vcpu->vcpu_id);
 387                         vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
 388                         kvm_vcpu_kick(vcpu);
 389                 } else {
 390                         apic_debug("Ignoring de-assert INIT to vcpu %d\n",
 391                                    vcpu->vcpu_id);
 392                 }
 393                 break;
 394
 395         case APIC_DM_STARTUP:
 396                 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
 397                            vcpu->vcpu_id, vector);
 398                 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
 399                         result = 1;
 400                         vcpu->arch.sipi_vector = vector;
 401                         vcpu->arch.mp_state = KVM_MP_STATE_SIPI_RECEIVED;
 402                         kvm_vcpu_kick(vcpu);
 403                 }
 404                 break;
 405
 406         case APIC_DM_EXTINT:
 407                 /*
 408                  * Should only be called by kvm_apic_local_deliver() with LVT0,
 409                  * before NMI watchdog was enabled. Already handled by
 410                  * kvm_apic_accept_pic_intr().
 411                  */
 412                 break;
 413
 414         default:
 415                 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
 416                        delivery_mode);
 417                 break;
 418         }
 419         return result;
 420 }
 421
 422 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
 423 {
 424         return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
 425 }
 426
 427 static void apic_set_eoi(struct kvm_lapic *apic)
 428 {
 429         int vector = apic_find_highest_isr(apic);
 430         int trigger_mode;
 431         /*
 432          * Not every write EOI will has corresponding ISR,
 433          * one example is when Kernel check timer on setup_IO_APIC
 434          */
 435         if (vector == -1)
 436                 return;
 437
 438         apic_clear_vector(vector, apic->regs + APIC_ISR);
 439         apic_update_ppr(apic);
 440
 441         if (apic_test_and_clear_vector(vector, apic->regs + APIC_TMR))
 442                 trigger_mode = IOAPIC_LEVEL_TRIG;
 443         else
 444                 trigger_mode = IOAPIC_EDGE_TRIG;
 445         mutex_lock(&apic->vcpu->kvm->irq_lock);
 446         kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode);
 447         mutex_unlock(&apic->vcpu->kvm->irq_lock);
 448 }
 449
 450 static void apic_send_ipi(struct kvm_lapic *apic)
 451 {
 452         u32 icr_low = apic_get_reg(apic, APIC_ICR);
 453         u32 icr_high = apic_get_reg(apic, APIC_ICR2);
 454         struct kvm_lapic_irq irq;
 455
 456         irq.vector = icr_low & APIC_VECTOR_MASK;
 457         irq.delivery_mode = icr_low & APIC_MODE_MASK;
 458         irq.dest_mode = icr_low & APIC_DEST_MASK;
 459         irq.level = icr_low & APIC_INT_ASSERT;
 460         irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
 461         irq.shorthand = icr_low & APIC_SHORT_MASK;
 462         irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
 463
 464         apic_debug("icr_high 0x%x, icr_low 0x%x, "
 465                    "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
 466                    "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
 467                    icr_high, icr_low, irq.shorthand, irq.dest_id,
 468                    irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
 469                    irq.vector);
 470
 471         mutex_lock(&apic->vcpu->kvm->irq_lock);
 472         kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq);
 473         mutex_unlock(&apic->vcpu->kvm->irq_lock);
 474 }
 475
 476 static u32 apic_get_tmcct(struct kvm_lapic *apic)
 477 {
 478         ktime_t remaining;
 479         s64 ns;
 480         u32 tmcct;
 481
 482         ASSERT(apic != NULL);
 483
 484         /* if initial count is 0, current count should also be 0 */
 485         if (apic_get_reg(apic, APIC_TMICT) == 0)
 486                 return 0;
 487
 488         remaining = hrtimer_expires_remaining(&apic->lapic_timer.timer);
 489         if (ktime_to_ns(remaining) < 0)
 490                 remaining = ktime_set(0, 0);
 491
 492         ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
 493         tmcct = div64_u64(ns,
 494                          (APIC_BUS_CYCLE_NS * apic->divide_count));
 495
 496         return tmcct;
 497 }
 498
 499 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
 500 {
 501         struct kvm_vcpu *vcpu = apic->vcpu;
 502         struct kvm_run *run = vcpu->run;
 503
 504         set_bit(KVM_REQ_REPORT_TPR_ACCESS, &vcpu->requests);
 505         run->tpr_access.rip = kvm_rip_read(vcpu);
 506         run->tpr_access.is_write = write;
 507 }
 508
 509 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
 510 {
 511         if (apic->vcpu->arch.tpr_access_reporting)
 512                 __report_tpr_access(apic, write);
 513 }
 514
 515 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
 516 {
 517         u32 val = 0;
 518
 519         if (offset >= LAPIC_MMIO_LENGTH)
 520                 return 0;
 521
 522         switch (offset) {
 523         case APIC_ARBPRI:
 524                 printk(KERN_WARNING "Access APIC ARBPRI register "
 525                        "which is for P6\n");
 526                 break;
 527
 528         case APIC_TMCCT:        /* Timer CCR */
 529                 val = apic_get_tmcct(apic);
 530                 break;
 531
 532         case APIC_TASKPRI:
 533                 report_tpr_access(apic, false);
 534                 /* fall thru */
 535         default:
 536                 apic_update_ppr(apic);
 537                 val = apic_get_reg(apic, offset);
 538                 break;
 539         }
 540
 541         return val;
 542 }
 543
 544 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
 545 {
 546         return container_of(dev, struct kvm_lapic, dev);
 547 }
 548
 549 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
 550 {
 551         return apic_hw_enabled(apic) &&
 552             addr >= apic->base_address &&
 553             addr < apic->base_address + LAPIC_MMIO_LENGTH;
 554 }
 555
 556 static int apic_mmio_read(struct kvm_io_device *this,
 557                           gpa_t address, int len, void *data)
 558 {
 559         struct kvm_lapic *apic = to_lapic(this);
 560         unsigned int offset = address - apic->base_address;
 561         unsigned char alignment = offset & 0xf;
 562         u32 result;
 563         if (!apic_mmio_in_range(apic, address))
 564                 return -EOPNOTSUPP;
 565
 566         if ((alignment + len) > 4) {
 567                 printk(KERN_ERR "KVM_APIC_READ: alignment error %lx %d",
 568                        (unsigned long)address, len);
 569                 return 0;
 570         }
 571         result = __apic_read(apic, offset & ~0xf);
 572
 573         trace_kvm_apic_read(offset, result);
 574
 575         switch (len) {
 576         case 1:
 577         case 2:
 578         case 4:
 579                 memcpy(data, (char *)&result + alignment, len);
 580                 break;
 581         default:
 582                 printk(KERN_ERR "Local APIC read with len = %x, "
 583                        "should be 1,2, or 4 instead\n", len);
 584                 break;
 585         }
 586         return 0;
 587 }
 588
 589 static void update_divide_count(struct kvm_lapic *apic)
 590 {
 591         u32 tmp1, tmp2, tdcr;
 592
 593         tdcr = apic_get_reg(apic, APIC_TDCR);
 594         tmp1 = tdcr & 0xf;
 595         tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
 596         apic->divide_count = 0x1 << (tmp2 & 0x7);
 597
 598         apic_debug("timer divide count is 0x%x\n",
 599                                    apic->divide_count);
 600 }
 601
 602 static void start_apic_timer(struct kvm_lapic *apic)
 603 {
 604         ktime_t now = apic->lapic_timer.timer.base->get_time();
 605
 606         apic->lapic_timer.period = apic_get_reg(apic, APIC_TMICT) *
 607                     APIC_BUS_CYCLE_NS * apic->divide_count;
 608         atomic_set(&apic->lapic_timer.pending, 0);
 609
 610         if (!apic->lapic_timer.period)
 611                 return;
 612
 613         hrtimer_start(&apic->lapic_timer.timer,
 614                       ktime_add_ns(now, apic->lapic_timer.period),
 615                       HRTIMER_MODE_ABS);
 616
 617         apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
 618                            PRIx64 ", "
 619                            "timer initial count 0x%x, period %lldns, "
 620                            "expire @ 0x%016" PRIx64 ".\n", __func__,
 621                            APIC_BUS_CYCLE_NS, ktime_to_ns(now),
 622                            apic_get_reg(apic, APIC_TMICT),
 623                            apic->lapic_timer.period,
 624                            ktime_to_ns(ktime_add_ns(now,
 625                                         apic->lapic_timer.period)));
 626 }
 627
 628 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
 629 {
 630         int nmi_wd_enabled = apic_lvt_nmi_mode(apic_get_reg(apic, APIC_LVT0));
 631
 632         if (apic_lvt_nmi_mode(lvt0_val)) {
 633                 if (!nmi_wd_enabled) {
 634                         apic_debug("Receive NMI setting on APIC_LVT0 "
 635                                    "for cpu %d\n", apic->vcpu->vcpu_id);
 636                         apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
 637                 }
 638         } else if (nmi_wd_enabled)
 639                 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
 640 }
 641
 642 static int apic_mmio_write(struct kvm_io_device *this,
 643                            gpa_t address, int len, const void *data)
 644 {
 645         struct kvm_lapic *apic = to_lapic(this);
 646         unsigned int offset = address - apic->base_address;
 647         unsigned char alignment = offset & 0xf;
 648         u32 val;
 649         if (!apic_mmio_in_range(apic, address))
 650                 return -EOPNOTSUPP;
 651
 652         /*
 653          * APIC register must be aligned on 128-bits boundary.
 654          * 32/64/128 bits registers must be accessed thru 32 bits.
 655          * Refer SDM 8.4.1
 656          */
 657         if (len != 4 || alignment) {
 658                 /* Don't shout loud, $infamous_os would cause only noise. */
 659                 apic_debug("apic write: bad size=%d %lx\n",
 660                            len, (long)address);
 661                 return 0;
 662         }
 663
 664         val = *(u32 *) data;
 665
 666         /* too common printing */
 667         if (offset != APIC_EOI)
 668                 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
 669                            "0x%x\n", __func__, offset, len, val);
 670
 671         offset &= 0xff0;
 672
 673         trace_kvm_apic_write(offset, val);
 674
 675         switch (offset) {
 676         case APIC_ID:           /* Local APIC ID */
 677                 apic_set_reg(apic, APIC_ID, val);
 678                 break;
 679
 680         case APIC_TASKPRI:
 681                 report_tpr_access(apic, true);
 682                 apic_set_tpr(apic, val & 0xff);
 683                 break;
 684
 685         case APIC_EOI:
 686                 apic_set_eoi(apic);
 687                 break;
 688
 689         case APIC_LDR:
 690                 apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK);
 691                 break;
 692
 693         case APIC_DFR:
 694                 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
 695                 break;
 696
 697         case APIC_SPIV:
 698                 apic_set_reg(apic, APIC_SPIV, val & 0x3ff);
 699                 if (!(val & APIC_SPIV_APIC_ENABLED)) {
 700                         int i;
 701                         u32 lvt_val;
 702
 703                         for (i = 0; i < APIC_LVT_NUM; i++) {
 704                                 lvt_val = apic_get_reg(apic,
 705                                                        APIC_LVTT + 0x10 * i);
 706                                 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
 707                                              lvt_val | APIC_LVT_MASKED);
 708                         }
 709                         atomic_set(&apic->lapic_timer.pending, 0);
 710
 711                 }
 712                 break;
 713
 714         case APIC_ICR:
 715                 /* No delay here, so we always clear the pending bit */
 716                 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
 717                 apic_send_ipi(apic);
 718                 break;
 719
 720         case APIC_ICR2:
 721                 apic_set_reg(apic, APIC_ICR2, val & 0xff000000);
 722                 break;
 723
 724         case APIC_LVT0:
 725                 apic_manage_nmi_watchdog(apic, val);
 726         case APIC_LVTT:
 727         case APIC_LVTTHMR:
 728         case APIC_LVTPC:
 729         case APIC_LVT1:
 730         case APIC_LVTERR:
 731                 /* TODO: Check vector */
 732                 if (!apic_sw_enabled(apic))
 733                         val |= APIC_LVT_MASKED;
 734
 735                 val &= apic_lvt_mask[(offset - APIC_LVTT) >> 4];
 736                 apic_set_reg(apic, offset, val);
 737
 738                 break;
 739
 740         case APIC_TMICT:
 741                 hrtimer_cancel(&apic->lapic_timer.timer);
 742                 apic_set_reg(apic, APIC_TMICT, val);
 743                 start_apic_timer(apic);
 744                 return 0;
 745
 746         case APIC_TDCR:
 747                 if (val & 4)
 748                         printk(KERN_ERR "KVM_WRITE:TDCR %x\n", val);
 749                 apic_set_reg(apic, APIC_TDCR, val);
 750                 update_divide_count(apic);
 751                 break;
 752
 753         default:
 754                 apic_debug("Local APIC Write to read-only register %x\n",
 755                            offset);
 756                 break;
 757         }
 758         return 0;
 759 }
 760
 761 void kvm_free_lapic(struct kvm_vcpu *vcpu)
 762 {
 763         if (!vcpu->arch.apic)
 764                 return;
 765
 766         hrtimer_cancel(&vcpu->arch.apic->lapic_timer.timer);
 767
 768         if (vcpu->arch.apic->regs_page)
 769                 __free_page(vcpu->arch.apic->regs_page);
 770
 771         kfree(vcpu->arch.apic);
 772 }
 773
 774 /*
 775  *----------------------------------------------------------------------
 776  * LAPIC interface
 777  *----------------------------------------------------------------------
 778  */
 779
 780 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
 781 {
 782         struct kvm_lapic *apic = vcpu->arch.apic;
 783
 784         if (!apic)
 785                 return;
 786         apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
 787                      | (apic_get_reg(apic, APIC_TASKPRI) & 4));
 788 }
 789
 790 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
 791 {
 792         struct kvm_lapic *apic = vcpu->arch.apic;
 793         u64 tpr;
 794
 795         if (!apic)
 796                 return 0;
 797         tpr = (u64) apic_get_reg(apic, APIC_TASKPRI);
 798
 799         return (tpr & 0xf0) >> 4;
 800 }
 801
 802 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
 803 {
 804         struct kvm_lapic *apic = vcpu->arch.apic;
 805
 806         if (!apic) {
 807                 value |= MSR_IA32_APICBASE_BSP;
 808                 vcpu->arch.apic_base = value;
 809                 return;
 810         }
 811
 812         if (!kvm_vcpu_is_bsp(apic->vcpu))
 813                 value &= ~MSR_IA32_APICBASE_BSP;
 814
 815         vcpu->arch.apic_base = value;
 816         apic->base_address = apic->vcpu->arch.apic_base &
 817                              MSR_IA32_APICBASE_BASE;
 818
 819         /* with FSB delivery interrupt, we can restart APIC functionality */
 820         apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
 821                    "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
 822
 823 }
 824
 825 void kvm_lapic_reset(struct kvm_vcpu *vcpu)
 826 {
 827         struct kvm_lapic *apic;
 828         int i;
 829
 830         apic_debug("%s\n", __func__);
 831
 832         ASSERT(vcpu);
 833         apic = vcpu->arch.apic;
 834         ASSERT(apic != NULL);
 835
 836         /* Stop the timer in case it's a reset to an active apic */
 837         hrtimer_cancel(&apic->lapic_timer.timer);
 838
 839         apic_set_reg(apic, APIC_ID, vcpu->vcpu_id << 24);
 840         apic_set_reg(apic, APIC_LVR, APIC_VERSION);
 841
 842         for (i = 0; i < APIC_LVT_NUM; i++)
 843                 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
 844         apic_set_reg(apic, APIC_LVT0,
 845                      SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
 846
 847         apic_set_reg(apic, APIC_DFR, 0xffffffffU);
 848         apic_set_reg(apic, APIC_SPIV, 0xff);
 849         apic_set_reg(apic, APIC_TASKPRI, 0);
 850         apic_set_reg(apic, APIC_LDR, 0);
 851         apic_set_reg(apic, APIC_ESR, 0);
 852         apic_set_reg(apic, APIC_ICR, 0);
 853         apic_set_reg(apic, APIC_ICR2, 0);
 854         apic_set_reg(apic, APIC_TDCR, 0);
 855         apic_set_reg(apic, APIC_TMICT, 0);
 856         for (i = 0; i < 8; i++) {
 857                 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
 858                 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
 859                 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
 860         }
 861         apic->irr_pending = false;
 862         update_divide_count(apic);
 863         atomic_set(&apic->lapic_timer.pending, 0);
 864         if (kvm_vcpu_is_bsp(vcpu))
 865                 vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP;
 866         apic_update_ppr(apic);
 867
 868         vcpu->arch.apic_arb_prio = 0;
 869
 870         apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr="
 871                    "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
 872                    vcpu, kvm_apic_id(apic),
 873                    vcpu->arch.apic_base, apic->base_address);
 874 }
 875
 876 bool kvm_apic_present(struct kvm_vcpu *vcpu)
 877 {
 878         return vcpu->arch.apic && apic_hw_enabled(vcpu->arch.apic);
 879 }
 880
 881 int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
 882 {
 883         return kvm_apic_present(vcpu) && apic_sw_enabled(vcpu->arch.apic);
 884 }
 885
 886 /*
 887  *----------------------------------------------------------------------
 888  * timer interface
 889  *----------------------------------------------------------------------
 890  */
 891
 892 static bool lapic_is_periodic(struct kvm_timer *ktimer)
 893 {
 894         struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic,
 895                                               lapic_timer);
 896         return apic_lvtt_period(apic);
 897 }
 898
 899 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
 900 {
 901         struct kvm_lapic *lapic = vcpu->arch.apic;
 902
 903         if (lapic && apic_enabled(lapic) && apic_lvt_enabled(lapic, APIC_LVTT))
 904                 return atomic_read(&lapic->lapic_timer.pending);
 905
 906         return 0;
 907 }
 908
 909 static int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
 910 {
 911         u32 reg = apic_get_reg(apic, lvt_type);
 912         int vector, mode, trig_mode;
 913
 914         if (apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
 915                 vector = reg & APIC_VECTOR_MASK;
 916                 mode = reg & APIC_MODE_MASK;
 917                 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
 918                 return __apic_accept_irq(apic, mode, vector, 1, trig_mode);
 919         }
 920         return 0;
 921 }
 922
 923 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
 924 {
 925         struct kvm_lapic *apic = vcpu->arch.apic;
 926
 927         if (apic)
 928                 kvm_apic_local_deliver(apic, APIC_LVT0);
 929 }
 930
 931 static struct kvm_timer_ops lapic_timer_ops = {
 932         .is_periodic = lapic_is_periodic,
 933 };
 934
 935 static const struct kvm_io_device_ops apic_mmio_ops = {
 936         .read     = apic_mmio_read,
 937         .write    = apic_mmio_write,
 938 };
 939
 940 int kvm_create_lapic(struct kvm_vcpu *vcpu)
 941 {
 942         struct kvm_lapic *apic;
 943
 944         ASSERT(vcpu != NULL);
 945         apic_debug("apic_init %d\n", vcpu->vcpu_id);
 946
 947         apic = kzalloc(sizeof(*apic), GFP_KERNEL);
 948         if (!apic)
 949                 goto nomem;
 950
 951         vcpu->arch.apic = apic;
 952
 953         apic->regs_page = alloc_page(GFP_KERNEL);
 954         if (apic->regs_page == NULL) {
 955                 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
 956                        vcpu->vcpu_id);
 957                 goto nomem_free_apic;
 958         }
 959         apic->regs = page_address(apic->regs_page);
 960         memset(apic->regs, 0, PAGE_SIZE);
 961         apic->vcpu = vcpu;
 962
 963         hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
 964                      HRTIMER_MODE_ABS);
 965         apic->lapic_timer.timer.function = kvm_timer_fn;
 966         apic->lapic_timer.t_ops = &lapic_timer_ops;
 967         apic->lapic_timer.kvm = vcpu->kvm;
 968         apic->lapic_timer.vcpu = vcpu;
 969
 970         apic->base_address = APIC_DEFAULT_PHYS_BASE;
 971         vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE;
 972
 973         kvm_lapic_reset(vcpu);
 974         kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
 975
 976         return 0;
 977 nomem_free_apic:
 978         kfree(apic);
 979 nomem:
 980         return -ENOMEM;
 981 }
 982
 983 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
 984 {
 985         struct kvm_lapic *apic = vcpu->arch.apic;
 986         int highest_irr;
 987
 988         if (!apic || !apic_enabled(apic))
 989                 return -1;
 990
 991         apic_update_ppr(apic);
 992         highest_irr = apic_find_highest_irr(apic);
 993         if ((highest_irr == -1) ||
 994             ((highest_irr & 0xF0) <= apic_get_reg(apic, APIC_PROCPRI)))
 995                 return -1;
 996         return highest_irr;
 997 }
 998
 999 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1000 {
1001         u32 lvt0 = apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1002         int r = 0;
1003
1004         if (kvm_vcpu_is_bsp(vcpu)) {
1005                 if (!apic_hw_enabled(vcpu->arch.apic))
1006                         r = 1;
1007                 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1008                     GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1009                         r = 1;
1010         }
1011         return r;
1012 }
1013
1014 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1015 {
1016         struct kvm_lapic *apic = vcpu->arch.apic;
1017
1018         if (apic && atomic_read(&apic->lapic_timer.pending) > 0) {
1019                 if (kvm_apic_local_deliver(apic, APIC_LVTT))
1020                         atomic_dec(&apic->lapic_timer.pending);
1021         }
1022 }
1023
1024 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1025 {
1026         int vector = kvm_apic_has_interrupt(vcpu);
1027         struct kvm_lapic *apic = vcpu->arch.apic;
1028
1029         if (vector == -1)
1030                 return -1;
1031
1032         apic_set_vector(vector, apic->regs + APIC_ISR);
1033         apic_update_ppr(apic);
1034         apic_clear_irr(vector, apic);
1035         return vector;
1036 }
1037
1038 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu)
1039 {
1040         struct kvm_lapic *apic = vcpu->arch.apic;
1041
1042         apic->base_address = vcpu->arch.apic_base &
1043                              MSR_IA32_APICBASE_BASE;
1044         apic_set_reg(apic, APIC_LVR, APIC_VERSION);
1045         apic_update_ppr(apic);
1046         hrtimer_cancel(&apic->lapic_timer.timer);
1047         update_divide_count(apic);
1048         start_apic_timer(apic);
1049 }
1050
1051 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1052 {
1053         struct kvm_lapic *apic = vcpu->arch.apic;
1054         struct hrtimer *timer;
1055
1056         if (!apic)
1057                 return;
1058
1059         timer = &apic->lapic_timer.timer;
1060         if (hrtimer_cancel(timer))
1061                 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
1062 }
1063
1064 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1065 {
1066         u32 data;
1067         void *vapic;
1068
1069         if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1070                 return;
1071
1072         vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1073         data = *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr));
1074         kunmap_atomic(vapic, KM_USER0);
1075
1076         apic_set_tpr(vcpu->arch.apic, data & 0xff);
1077 }
1078
1079 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1080 {
1081         u32 data, tpr;
1082         int max_irr, max_isr;
1083         struct kvm_lapic *apic;
1084         void *vapic;
1085
1086         if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1087                 return;
1088
1089         apic = vcpu->arch.apic;
1090         tpr = apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1091         max_irr = apic_find_highest_irr(apic);
1092         if (max_irr < 0)
1093                 max_irr = 0;
1094         max_isr = apic_find_highest_isr(apic);
1095         if (max_isr < 0)
1096                 max_isr = 0;
1097         data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1098
1099         vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1100         *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)) = data;
1101         kunmap_atomic(vapic, KM_USER0);
1102 }
1103
1104 void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1105 {
1106         if (!irqchip_in_kernel(vcpu->kvm))
1107                 return;
1108
1109         vcpu->arch.apic->vapic_addr = vapic_addr;
1110 }