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   1
   2 /*
   3  * Local APIC virtualization
   4  *
   5  * Copyright (C) 2006 Qumranet, Inc.
   6  * Copyright (C) 2007 Novell
   7  * Copyright (C) 2007 Intel
   8  *
   9  * Authors:
  10  *   Dor Laor <dor.laor@qumranet.com>
  11  *   Gregory Haskins <ghaskins@novell.com>
  12  *   Yaozu (Eddie) Dong <eddie.dong@intel.com>
  13  *
  14  * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
  15  *
  16  * This work is licensed under the terms of the GNU GPL, version 2.  See
  17  * the COPYING file in the top-level directory.
  18  */
  19
  20 #include <linux/kvm_host.h>
  21 #include <linux/kvm.h>
  22 #include <linux/mm.h>
  23 #include <linux/highmem.h>
  24 #include <linux/smp.h>
  25 #include <linux/hrtimer.h>
  26 #include <linux/io.h>
  27 #include <linux/module.h>
  28 #include <linux/math64.h>
  29 #include <asm/processor.h>
  30 #include <asm/msr.h>
  31 #include <asm/page.h>
  32 #include <asm/current.h>
  33 #include <asm/apicdef.h>
  34 #include <asm/atomic.h>
  35 #include "kvm_cache_regs.h"
  36 #include "irq.h"
  37
  38 #ifndef CONFIG_X86_64
  39 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
  40 #else
  41 #define mod_64(x, y) ((x) % (y))
  42 #endif
  43
  44 #define PRId64 "d"
  45 #define PRIx64 "llx"
  46 #define PRIu64 "u"
  47 #define PRIo64 "o"
  48
  49 #define APIC_BUS_CYCLE_NS 1
  50
  51 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
  52 #define apic_debug(fmt, arg...)
  53
  54 #define APIC_LVT_NUM                    6
  55 /* 14 is the version for Xeon and Pentium 8.4.8*/
  56 #define APIC_VERSION                    (0x14UL | ((APIC_LVT_NUM - 1) << 16))
  57 #define LAPIC_MMIO_LENGTH               (1 << 12)
  58 /* followed define is not in apicdef.h */
  59 #define APIC_SHORT_MASK                 0xc0000
  60 #define APIC_DEST_NOSHORT               0x0
  61 #define APIC_DEST_MASK                  0x800
  62 #define MAX_APIC_VECTOR                 256
  63
  64 #define VEC_POS(v) ((v) & (32 - 1))
  65 #define REG_POS(v) (((v) >> 5) << 4)
  66
  67 static inline u32 apic_get_reg(struct kvm_lapic *apic, int reg_off)
  68 {
  69         return *((u32 *) (apic->regs + reg_off));
  70 }
  71
  72 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
  73 {
  74         *((u32 *) (apic->regs + reg_off)) = val;
  75 }
  76
  77 static inline int apic_test_and_set_vector(int vec, void *bitmap)
  78 {
  79         return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  80 }
  81
  82 static inline int apic_test_and_clear_vector(int vec, void *bitmap)
  83 {
  84         return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  85 }
  86
  87 static inline void apic_set_vector(int vec, void *bitmap)
  88 {
  89         set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  90 }
  91
  92 static inline void apic_clear_vector(int vec, void *bitmap)
  93 {
  94         clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  95 }
  96
  97 static inline int apic_hw_enabled(struct kvm_lapic *apic)
  98 {
  99         return (apic)->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
 100 }
 101
 102 static inline int  apic_sw_enabled(struct kvm_lapic *apic)
 103 {
 104         return apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED;
 105 }
 106
 107 static inline int apic_enabled(struct kvm_lapic *apic)
 108 {
 109         return apic_sw_enabled(apic) && apic_hw_enabled(apic);
 110 }
 111
 112 #define LVT_MASK        \
 113         (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
 114
 115 #define LINT_MASK       \
 116         (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
 117          APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
 118
 119 static inline int kvm_apic_id(struct kvm_lapic *apic)
 120 {
 121         return (apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
 122 }
 123
 124 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
 125 {
 126         return !(apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
 127 }
 128
 129 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
 130 {
 131         return apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
 132 }
 133
 134 static inline int apic_lvtt_period(struct kvm_lapic *apic)
 135 {
 136         return apic_get_reg(apic, APIC_LVTT) & APIC_LVT_TIMER_PERIODIC;
 137 }
 138
 139 static inline int apic_lvt_nmi_mode(u32 lvt_val)
 140 {
 141         return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
 142 }
 143
 144 static unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
 145         LVT_MASK | APIC_LVT_TIMER_PERIODIC,     /* LVTT */
 146         LVT_MASK | APIC_MODE_MASK,      /* LVTTHMR */
 147         LVT_MASK | APIC_MODE_MASK,      /* LVTPC */
 148         LINT_MASK, LINT_MASK,   /* LVT0-1 */
 149         LVT_MASK                /* LVTERR */
 150 };
 151
 152 static int find_highest_vector(void *bitmap)
 153 {
 154         u32 *word = bitmap;
 155         int word_offset = MAX_APIC_VECTOR >> 5;
 156
 157         while ((word_offset != 0) && (word[(--word_offset) << 2] == 0))
 158                 continue;
 159
 160         if (likely(!word_offset && !word[0]))
 161                 return -1;
 162         else
 163                 return fls(word[word_offset << 2]) - 1 + (word_offset << 5);
 164 }
 165
 166 static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic)
 167 {
 168         return apic_test_and_set_vector(vec, apic->regs + APIC_IRR);
 169 }
 170
 171 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
 172 {
 173         apic_clear_vector(vec, apic->regs + APIC_IRR);
 174 }
 175
 176 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
 177 {
 178         int result;
 179
 180         result = find_highest_vector(apic->regs + APIC_IRR);
 181         ASSERT(result == -1 || result >= 16);
 182
 183         return result;
 184 }
 185
 186 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
 187 {
 188         struct kvm_lapic *apic = vcpu->arch.apic;
 189         int highest_irr;
 190
 191         if (!apic)
 192                 return 0;
 193         highest_irr = apic_find_highest_irr(apic);
 194
 195         return highest_irr;
 196 }
 197 EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr);
 198
 199 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 200                              int vector, int level, int trig_mode);
 201
 202 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, u8 vec, u8 dmode, u8 trig)
 203 {
 204         struct kvm_lapic *apic = vcpu->arch.apic;
 205         int lapic_dmode;
 206
 207         switch (dmode) {
 208         case IOAPIC_LOWEST_PRIORITY:
 209                 lapic_dmode = APIC_DM_LOWEST;
 210                 break;
 211         case IOAPIC_FIXED:
 212                 lapic_dmode = APIC_DM_FIXED;
 213                 break;
 214         case IOAPIC_NMI:
 215                 lapic_dmode = APIC_DM_NMI;
 216                 break;
 217         default:
 218                 printk(KERN_DEBUG"Ignoring delivery mode %d\n", dmode);
 219                 return 0;
 220                 break;
 221         }
 222         return __apic_accept_irq(apic, lapic_dmode, vec, 1, trig);
 223 }
 224
 225 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
 226 {
 227         int result;
 228
 229         result = find_highest_vector(apic->regs + APIC_ISR);
 230         ASSERT(result == -1 || result >= 16);
 231
 232         return result;
 233 }
 234
 235 static void apic_update_ppr(struct kvm_lapic *apic)
 236 {
 237         u32 tpr, isrv, ppr;
 238         int isr;
 239
 240         tpr = apic_get_reg(apic, APIC_TASKPRI);
 241         isr = apic_find_highest_isr(apic);
 242         isrv = (isr != -1) ? isr : 0;
 243
 244         if ((tpr & 0xf0) >= (isrv & 0xf0))
 245                 ppr = tpr & 0xff;
 246         else
 247                 ppr = isrv & 0xf0;
 248
 249         apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
 250                    apic, ppr, isr, isrv);
 251
 252         apic_set_reg(apic, APIC_PROCPRI, ppr);
 253 }
 254
 255 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
 256 {
 257         apic_set_reg(apic, APIC_TASKPRI, tpr);
 258         apic_update_ppr(apic);
 259 }
 260
 261 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest)
 262 {
 263         return kvm_apic_id(apic) == dest;
 264 }
 265
 266 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
 267 {
 268         int result = 0;
 269         u8 logical_id;
 270
 271         logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR));
 272
 273         switch (apic_get_reg(apic, APIC_DFR)) {
 274         case APIC_DFR_FLAT:
 275                 if (logical_id & mda)
 276                         result = 1;
 277                 break;
 278         case APIC_DFR_CLUSTER:
 279                 if (((logical_id >> 4) == (mda >> 0x4))
 280                     && (logical_id & mda & 0xf))
 281                         result = 1;
 282                 break;
 283         default:
 284                 printk(KERN_WARNING "Bad DFR vcpu %d: %08x\n",
 285                        apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR));
 286                 break;
 287         }
 288
 289         return result;
 290 }
 291
 292 static int apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
 293                            int short_hand, int dest, int dest_mode)
 294 {
 295         int result = 0;
 296         struct kvm_lapic *target = vcpu->arch.apic;
 297
 298         apic_debug("target %p, source %p, dest 0x%x, "
 299                    "dest_mode 0x%x, short_hand 0x%x",
 300                    target, source, dest, dest_mode, short_hand);
 301
 302         ASSERT(!target);
 303         switch (short_hand) {
 304         case APIC_DEST_NOSHORT:
 305                 if (dest_mode == 0) {
 306                         /* Physical mode. */
 307                         if ((dest == 0xFF) || (dest == kvm_apic_id(target)))
 308                                 result = 1;
 309                 } else
 310                         /* Logical mode. */
 311                         result = kvm_apic_match_logical_addr(target, dest);
 312                 break;
 313         case APIC_DEST_SELF:
 314                 if (target == source)
 315                         result = 1;
 316                 break;
 317         case APIC_DEST_ALLINC:
 318                 result = 1;
 319                 break;
 320         case APIC_DEST_ALLBUT:
 321                 if (target != source)
 322                         result = 1;
 323                 break;
 324         default:
 325                 printk(KERN_WARNING "Bad dest shorthand value %x\n",
 326                        short_hand);
 327                 break;
 328         }
 329
 330         return result;
 331 }
 332
 333 /*
 334  * Add a pending IRQ into lapic.
 335  * Return 1 if successfully added and 0 if discarded.
 336  */
 337 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 338                              int vector, int level, int trig_mode)
 339 {
 340         int result = 0;
 341         struct kvm_vcpu *vcpu = apic->vcpu;
 342
 343         switch (delivery_mode) {
 344         case APIC_DM_FIXED:
 345         case APIC_DM_LOWEST:
 346                 /* FIXME add logic for vcpu on reset */
 347                 if (unlikely(!apic_enabled(apic)))
 348                         break;
 349
 350                 result = !apic_test_and_set_irr(vector, apic);
 351                 if (!result) {
 352                         if (trig_mode)
 353                                 apic_debug("level trig mode repeatedly for "
 354                                                 "vector %d", vector);
 355                         break;
 356                 }
 357
 358                 if (trig_mode) {
 359                         apic_debug("level trig mode for vector %d", vector);
 360                         apic_set_vector(vector, apic->regs + APIC_TMR);
 361                 } else
 362                         apic_clear_vector(vector, apic->regs + APIC_TMR);
 363                 kvm_vcpu_kick(vcpu);
 364                 break;
 365
 366         case APIC_DM_REMRD:
 367                 printk(KERN_DEBUG "Ignoring delivery mode 3\n");
 368                 break;
 369
 370         case APIC_DM_SMI:
 371                 printk(KERN_DEBUG "Ignoring guest SMI\n");
 372                 break;
 373
 374         case APIC_DM_NMI:
 375                 result = 1;
 376                 kvm_inject_nmi(vcpu);
 377                 kvm_vcpu_kick(vcpu);
 378                 break;
 379
 380         case APIC_DM_INIT:
 381                 if (level) {
 382                         result = 1;
 383                         if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
 384                                 printk(KERN_DEBUG
 385                                        "INIT on a runnable vcpu %d\n",
 386                                        vcpu->vcpu_id);
 387                         vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
 388                         kvm_vcpu_kick(vcpu);
 389                 } else {
 390                         apic_debug("Ignoring de-assert INIT to vcpu %d\n",
 391                                    vcpu->vcpu_id);
 392                 }
 393                 break;
 394
 395         case APIC_DM_STARTUP:
 396                 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
 397                            vcpu->vcpu_id, vector);
 398                 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
 399                         result = 1;
 400                         vcpu->arch.sipi_vector = vector;
 401                         vcpu->arch.mp_state = KVM_MP_STATE_SIPI_RECEIVED;
 402                         kvm_vcpu_kick(vcpu);
 403                 }
 404                 break;
 405
 406         case APIC_DM_EXTINT:
 407                 /*
 408                  * Should only be called by kvm_apic_local_deliver() with LVT0,
 409                  * before NMI watchdog was enabled. Already handled by
 410                  * kvm_apic_accept_pic_intr().
 411                  */
 412                 break;
 413
 414         default:
 415                 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
 416                        delivery_mode);
 417                 break;
 418         }
 419         return result;
 420 }
 421
 422 static struct kvm_lapic *kvm_apic_round_robin(struct kvm *kvm, u8 vector,
 423                                        unsigned long *bitmap)
 424 {
 425         int last;
 426         int next;
 427         struct kvm_lapic *apic = NULL;
 428
 429         last = kvm->arch.round_robin_prev_vcpu;
 430         next = last;
 431
 432         do {
 433                 if (++next == KVM_MAX_VCPUS)
 434                         next = 0;
 435                 if (kvm->vcpus[next] == NULL || !test_bit(next, bitmap))
 436                         continue;
 437                 apic = kvm->vcpus[next]->arch.apic;
 438                 if (apic && apic_enabled(apic))
 439                         break;
 440                 apic = NULL;
 441         } while (next != last);
 442         kvm->arch.round_robin_prev_vcpu = next;
 443
 444         if (!apic)
 445                 printk(KERN_DEBUG "vcpu not ready for apic_round_robin\n");
 446
 447         return apic;
 448 }
 449
 450 struct kvm_vcpu *kvm_get_lowest_prio_vcpu(struct kvm *kvm, u8 vector,
 451                 unsigned long *bitmap)
 452 {
 453         struct kvm_lapic *apic;
 454
 455         apic = kvm_apic_round_robin(kvm, vector, bitmap);
 456         if (apic)
 457                 return apic->vcpu;
 458         return NULL;
 459 }
 460
 461 static void apic_set_eoi(struct kvm_lapic *apic)
 462 {
 463         int vector = apic_find_highest_isr(apic);
 464         int trigger_mode;
 465         /*
 466          * Not every write EOI will has corresponding ISR,
 467          * one example is when Kernel check timer on setup_IO_APIC
 468          */
 469         if (vector == -1)
 470                 return;
 471
 472         apic_clear_vector(vector, apic->regs + APIC_ISR);
 473         apic_update_ppr(apic);
 474
 475         if (apic_test_and_clear_vector(vector, apic->regs + APIC_TMR))
 476                 trigger_mode = IOAPIC_LEVEL_TRIG;
 477         else
 478                 trigger_mode = IOAPIC_EDGE_TRIG;
 479         kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode);
 480 }
 481
 482 static void apic_send_ipi(struct kvm_lapic *apic)
 483 {
 484         u32 icr_low = apic_get_reg(apic, APIC_ICR);
 485         u32 icr_high = apic_get_reg(apic, APIC_ICR2);
 486
 487         unsigned int dest = GET_APIC_DEST_FIELD(icr_high);
 488         unsigned int short_hand = icr_low & APIC_SHORT_MASK;
 489         unsigned int trig_mode = icr_low & APIC_INT_LEVELTRIG;
 490         unsigned int level = icr_low & APIC_INT_ASSERT;
 491         unsigned int dest_mode = icr_low & APIC_DEST_MASK;
 492         unsigned int delivery_mode = icr_low & APIC_MODE_MASK;
 493         unsigned int vector = icr_low & APIC_VECTOR_MASK;
 494
 495         struct kvm_vcpu *target;
 496         struct kvm_vcpu *vcpu;
 497         DECLARE_BITMAP(lpr_map, KVM_MAX_VCPUS);
 498         int i;
 499
 500         bitmap_zero(lpr_map, KVM_MAX_VCPUS);
 501         apic_debug("icr_high 0x%x, icr_low 0x%x, "
 502                    "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
 503                    "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
 504                    icr_high, icr_low, short_hand, dest,
 505                    trig_mode, level, dest_mode, delivery_mode, vector);
 506
 507         for (i = 0; i < KVM_MAX_VCPUS; i++) {
 508                 vcpu = apic->vcpu->kvm->vcpus[i];
 509                 if (!vcpu)
 510                         continue;
 511
 512                 if (vcpu->arch.apic &&
 513                     apic_match_dest(vcpu, apic, short_hand, dest, dest_mode)) {
 514                         if (delivery_mode == APIC_DM_LOWEST)
 515                                 __set_bit(vcpu->vcpu_id, lpr_map);
 516                         else
 517                                 __apic_accept_irq(vcpu->arch.apic, delivery_mode,
 518                                                   vector, level, trig_mode);
 519                 }
 520         }
 521
 522         if (delivery_mode == APIC_DM_LOWEST) {
 523                 target = kvm_get_lowest_prio_vcpu(vcpu->kvm, vector, lpr_map);
 524                 if (target != NULL)
 525                         __apic_accept_irq(target->arch.apic, delivery_mode,
 526                                           vector, level, trig_mode);
 527         }
 528 }
 529
 530 static u32 apic_get_tmcct(struct kvm_lapic *apic)
 531 {
 532         ktime_t remaining;
 533         s64 ns;
 534         u32 tmcct;
 535
 536         ASSERT(apic != NULL);
 537
 538         /* if initial count is 0, current count should also be 0 */
 539         if (apic_get_reg(apic, APIC_TMICT) == 0)
 540                 return 0;
 541
 542         remaining = hrtimer_expires_remaining(&apic->lapic_timer.timer);
 543         if (ktime_to_ns(remaining) < 0)
 544                 remaining = ktime_set(0, 0);
 545
 546         ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
 547         tmcct = div64_u64(ns,
 548                          (APIC_BUS_CYCLE_NS * apic->divide_count));
 549
 550         return tmcct;
 551 }
 552
 553 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
 554 {
 555         struct kvm_vcpu *vcpu = apic->vcpu;
 556         struct kvm_run *run = vcpu->run;
 557
 558         set_bit(KVM_REQ_REPORT_TPR_ACCESS, &vcpu->requests);
 559         run->tpr_access.rip = kvm_rip_read(vcpu);
 560         run->tpr_access.is_write = write;
 561 }
 562
 563 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
 564 {
 565         if (apic->vcpu->arch.tpr_access_reporting)
 566                 __report_tpr_access(apic, write);
 567 }
 568
 569 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
 570 {
 571         u32 val = 0;
 572
 573         KVMTRACE_1D(APIC_ACCESS, apic->vcpu, (u32)offset, handler);
 574
 575         if (offset >= LAPIC_MMIO_LENGTH)
 576                 return 0;
 577
 578         switch (offset) {
 579         case APIC_ARBPRI:
 580                 printk(KERN_WARNING "Access APIC ARBPRI register "
 581                        "which is for P6\n");
 582                 break;
 583
 584         case APIC_TMCCT:        /* Timer CCR */
 585                 val = apic_get_tmcct(apic);
 586                 break;
 587
 588         case APIC_TASKPRI:
 589                 report_tpr_access(apic, false);
 590                 /* fall thru */
 591         default:
 592                 apic_update_ppr(apic);
 593                 val = apic_get_reg(apic, offset);
 594                 break;
 595         }
 596
 597         return val;
 598 }
 599
 600 static void apic_mmio_read(struct kvm_io_device *this,
 601                            gpa_t address, int len, void *data)
 602 {
 603         struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
 604         unsigned int offset = address - apic->base_address;
 605         unsigned char alignment = offset & 0xf;
 606         u32 result;
 607
 608         if ((alignment + len) > 4) {
 609                 printk(KERN_ERR "KVM_APIC_READ: alignment error %lx %d",
 610                        (unsigned long)address, len);
 611                 return;
 612         }
 613         result = __apic_read(apic, offset & ~0xf);
 614
 615         switch (len) {
 616         case 1:
 617         case 2:
 618         case 4:
 619                 memcpy(data, (char *)&result + alignment, len);
 620                 break;
 621         default:
 622                 printk(KERN_ERR "Local APIC read with len = %x, "
 623                        "should be 1,2, or 4 instead\n", len);
 624                 break;
 625         }
 626 }
 627
 628 static void update_divide_count(struct kvm_lapic *apic)
 629 {
 630         u32 tmp1, tmp2, tdcr;
 631
 632         tdcr = apic_get_reg(apic, APIC_TDCR);
 633         tmp1 = tdcr & 0xf;
 634         tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
 635         apic->divide_count = 0x1 << (tmp2 & 0x7);
 636
 637         apic_debug("timer divide count is 0x%x\n",
 638                                    apic->lapic_timer.divide_count);
 639 }
 640
 641 static void start_apic_timer(struct kvm_lapic *apic)
 642 {
 643         ktime_t now = apic->lapic_timer.timer.base->get_time();
 644
 645         apic->lapic_timer.period = apic_get_reg(apic, APIC_TMICT) *
 646                     APIC_BUS_CYCLE_NS * apic->divide_count;
 647         atomic_set(&apic->lapic_timer.pending, 0);
 648
 649         if (!apic->lapic_timer.period)
 650                 return;
 651
 652         hrtimer_start(&apic->lapic_timer.timer,
 653                       ktime_add_ns(now, apic->lapic_timer.period),
 654                       HRTIMER_MODE_ABS);
 655
 656         apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
 657                            PRIx64 ", "
 658                            "timer initial count 0x%x, period %lldns, "
 659                            "expire @ 0x%016" PRIx64 ".\n", __func__,
 660                            APIC_BUS_CYCLE_NS, ktime_to_ns(now),
 661                            apic_get_reg(apic, APIC_TMICT),
 662                            apic->lapic_timer.period,
 663                            ktime_to_ns(ktime_add_ns(now,
 664                                         apic->lapic_timer.period)));
 665 }
 666
 667 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
 668 {
 669         int nmi_wd_enabled = apic_lvt_nmi_mode(apic_get_reg(apic, APIC_LVT0));
 670
 671         if (apic_lvt_nmi_mode(lvt0_val)) {
 672                 if (!nmi_wd_enabled) {
 673                         apic_debug("Receive NMI setting on APIC_LVT0 "
 674                                    "for cpu %d\n", apic->vcpu->vcpu_id);
 675                         apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
 676                 }
 677         } else if (nmi_wd_enabled)
 678                 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
 679 }
 680
 681 static void apic_mmio_write(struct kvm_io_device *this,
 682                             gpa_t address, int len, const void *data)
 683 {
 684         struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
 685         unsigned int offset = address - apic->base_address;
 686         unsigned char alignment = offset & 0xf;
 687         u32 val;
 688
 689         /*
 690          * APIC register must be aligned on 128-bits boundary.
 691          * 32/64/128 bits registers must be accessed thru 32 bits.
 692          * Refer SDM 8.4.1
 693          */
 694         if (len != 4 || alignment) {
 695                 /* Don't shout loud, $infamous_os would cause only noise. */
 696                 apic_debug("apic write: bad size=%d %lx\n",
 697                            len, (long)address);
 698                 return;
 699         }
 700
 701         val = *(u32 *) data;
 702
 703         /* too common printing */
 704         if (offset != APIC_EOI)
 705                 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
 706                            "0x%x\n", __func__, offset, len, val);
 707
 708         offset &= 0xff0;
 709
 710         KVMTRACE_1D(APIC_ACCESS, apic->vcpu, (u32)offset, handler);
 711
 712         switch (offset) {
 713         case APIC_ID:           /* Local APIC ID */
 714                 apic_set_reg(apic, APIC_ID, val);
 715                 break;
 716
 717         case APIC_TASKPRI:
 718                 report_tpr_access(apic, true);
 719                 apic_set_tpr(apic, val & 0xff);
 720                 break;
 721
 722         case APIC_EOI:
 723                 apic_set_eoi(apic);
 724                 break;
 725
 726         case APIC_LDR:
 727                 apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK);
 728                 break;
 729
 730         case APIC_DFR:
 731                 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
 732                 break;
 733
 734         case APIC_SPIV:
 735                 apic_set_reg(apic, APIC_SPIV, val & 0x3ff);
 736                 if (!(val & APIC_SPIV_APIC_ENABLED)) {
 737                         int i;
 738                         u32 lvt_val;
 739
 740                         for (i = 0; i < APIC_LVT_NUM; i++) {
 741                                 lvt_val = apic_get_reg(apic,
 742                                                        APIC_LVTT + 0x10 * i);
 743                                 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
 744                                              lvt_val | APIC_LVT_MASKED);
 745                         }
 746                         atomic_set(&apic->lapic_timer.pending, 0);
 747
 748                 }
 749                 break;
 750
 751         case APIC_ICR:
 752                 /* No delay here, so we always clear the pending bit */
 753                 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
 754                 apic_send_ipi(apic);
 755                 break;
 756
 757         case APIC_ICR2:
 758                 apic_set_reg(apic, APIC_ICR2, val & 0xff000000);
 759                 break;
 760
 761         case APIC_LVT0:
 762                 apic_manage_nmi_watchdog(apic, val);
 763         case APIC_LVTT:
 764         case APIC_LVTTHMR:
 765         case APIC_LVTPC:
 766         case APIC_LVT1:
 767         case APIC_LVTERR:
 768                 /* TODO: Check vector */
 769                 if (!apic_sw_enabled(apic))
 770                         val |= APIC_LVT_MASKED;
 771
 772                 val &= apic_lvt_mask[(offset - APIC_LVTT) >> 4];
 773                 apic_set_reg(apic, offset, val);
 774
 775                 break;
 776
 777         case APIC_TMICT:
 778                 hrtimer_cancel(&apic->lapic_timer.timer);
 779                 apic_set_reg(apic, APIC_TMICT, val);
 780                 start_apic_timer(apic);
 781                 return;
 782
 783         case APIC_TDCR:
 784                 if (val & 4)
 785                         printk(KERN_ERR "KVM_WRITE:TDCR %x\n", val);
 786                 apic_set_reg(apic, APIC_TDCR, val);
 787                 update_divide_count(apic);
 788                 break;
 789
 790         default:
 791                 apic_debug("Local APIC Write to read-only register %x\n",
 792                            offset);
 793                 break;
 794         }
 795
 796 }
 797
 798 static int apic_mmio_range(struct kvm_io_device *this, gpa_t addr,
 799                            int len, int size)
 800 {
 801         struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
 802         int ret = 0;
 803
 804
 805         if (apic_hw_enabled(apic) &&
 806             (addr >= apic->base_address) &&
 807             (addr < (apic->base_address + LAPIC_MMIO_LENGTH)))
 808                 ret = 1;
 809
 810         return ret;
 811 }
 812
 813 void kvm_free_lapic(struct kvm_vcpu *vcpu)
 814 {
 815         if (!vcpu->arch.apic)
 816                 return;
 817
 818         hrtimer_cancel(&vcpu->arch.apic->lapic_timer.timer);
 819
 820         if (vcpu->arch.apic->regs_page)
 821                 __free_page(vcpu->arch.apic->regs_page);
 822
 823         kfree(vcpu->arch.apic);
 824 }
 825
 826 /*
 827  *----------------------------------------------------------------------
 828  * LAPIC interface
 829  *----------------------------------------------------------------------
 830  */
 831
 832 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
 833 {
 834         struct kvm_lapic *apic = vcpu->arch.apic;
 835
 836         if (!apic)
 837                 return;
 838         apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
 839                      | (apic_get_reg(apic, APIC_TASKPRI) & 4));
 840 }
 841 EXPORT_SYMBOL_GPL(kvm_lapic_set_tpr);
 842
 843 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
 844 {
 845         struct kvm_lapic *apic = vcpu->arch.apic;
 846         u64 tpr;
 847
 848         if (!apic)
 849                 return 0;
 850         tpr = (u64) apic_get_reg(apic, APIC_TASKPRI);
 851
 852         return (tpr & 0xf0) >> 4;
 853 }
 854 EXPORT_SYMBOL_GPL(kvm_lapic_get_cr8);
 855
 856 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
 857 {
 858         struct kvm_lapic *apic = vcpu->arch.apic;
 859
 860         if (!apic) {
 861                 value |= MSR_IA32_APICBASE_BSP;
 862                 vcpu->arch.apic_base = value;
 863                 return;
 864         }
 865         if (apic->vcpu->vcpu_id)
 866                 value &= ~MSR_IA32_APICBASE_BSP;
 867
 868         vcpu->arch.apic_base = value;
 869         apic->base_address = apic->vcpu->arch.apic_base &
 870                              MSR_IA32_APICBASE_BASE;
 871
 872         /* with FSB delivery interrupt, we can restart APIC functionality */
 873         apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
 874                    "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
 875
 876 }
 877
 878 u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu)
 879 {
 880         return vcpu->arch.apic_base;
 881 }
 882 EXPORT_SYMBOL_GPL(kvm_lapic_get_base);
 883
 884 void kvm_lapic_reset(struct kvm_vcpu *vcpu)
 885 {
 886         struct kvm_lapic *apic;
 887         int i;
 888
 889         apic_debug("%s\n", __func__);
 890
 891         ASSERT(vcpu);
 892         apic = vcpu->arch.apic;
 893         ASSERT(apic != NULL);
 894
 895         /* Stop the timer in case it's a reset to an active apic */
 896         hrtimer_cancel(&apic->lapic_timer.timer);
 897
 898         apic_set_reg(apic, APIC_ID, vcpu->vcpu_id << 24);
 899         apic_set_reg(apic, APIC_LVR, APIC_VERSION);
 900
 901         for (i = 0; i < APIC_LVT_NUM; i++)
 902                 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
 903         apic_set_reg(apic, APIC_LVT0,
 904                      SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
 905
 906         apic_set_reg(apic, APIC_DFR, 0xffffffffU);
 907         apic_set_reg(apic, APIC_SPIV, 0xff);
 908         apic_set_reg(apic, APIC_TASKPRI, 0);
 909         apic_set_reg(apic, APIC_LDR, 0);
 910         apic_set_reg(apic, APIC_ESR, 0);
 911         apic_set_reg(apic, APIC_ICR, 0);
 912         apic_set_reg(apic, APIC_ICR2, 0);
 913         apic_set_reg(apic, APIC_TDCR, 0);
 914         apic_set_reg(apic, APIC_TMICT, 0);
 915         for (i = 0; i < 8; i++) {
 916                 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
 917                 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
 918                 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
 919         }
 920         update_divide_count(apic);
 921         atomic_set(&apic->lapic_timer.pending, 0);
 922         if (vcpu->vcpu_id == 0)
 923                 vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP;
 924         apic_update_ppr(apic);
 925
 926         apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr="
 927                    "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
 928                    vcpu, kvm_apic_id(apic),
 929                    vcpu->arch.apic_base, apic->base_address);
 930 }
 931 EXPORT_SYMBOL_GPL(kvm_lapic_reset);
 932
 933 int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
 934 {
 935         struct kvm_lapic *apic = vcpu->arch.apic;
 936         int ret = 0;
 937
 938         if (!apic)
 939                 return 0;
 940         ret = apic_enabled(apic);
 941
 942         return ret;
 943 }
 944 EXPORT_SYMBOL_GPL(kvm_lapic_enabled);
 945
 946 /*
 947  *----------------------------------------------------------------------
 948  * timer interface
 949  *----------------------------------------------------------------------
 950  */
 951
 952 static bool lapic_is_periodic(struct kvm_timer *ktimer)
 953 {
 954         struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic,
 955                                               lapic_timer);
 956         return apic_lvtt_period(apic);
 957 }
 958
 959 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
 960 {
 961         struct kvm_lapic *lapic = vcpu->arch.apic;
 962
 963         if (lapic && apic_enabled(lapic) && apic_lvt_enabled(lapic, APIC_LVTT))
 964                 return atomic_read(&lapic->lapic_timer.pending);
 965
 966         return 0;
 967 }
 968
 969 static int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
 970 {
 971         u32 reg = apic_get_reg(apic, lvt_type);
 972         int vector, mode, trig_mode;
 973
 974         if (apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
 975                 vector = reg & APIC_VECTOR_MASK;
 976                 mode = reg & APIC_MODE_MASK;
 977                 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
 978                 return __apic_accept_irq(apic, mode, vector, 1, trig_mode);
 979         }
 980         return 0;
 981 }
 982
 983 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
 984 {
 985         struct kvm_lapic *apic = vcpu->arch.apic;
 986
 987         if (apic)
 988                 kvm_apic_local_deliver(apic, APIC_LVT0);
 989 }
 990
 991 struct kvm_timer_ops lapic_timer_ops = {
 992         .is_periodic = lapic_is_periodic,
 993 };
 994
 995 int kvm_create_lapic(struct kvm_vcpu *vcpu)
 996 {
 997         struct kvm_lapic *apic;
 998
 999         ASSERT(vcpu != NULL);
1000         apic_debug("apic_init %d\n", vcpu->vcpu_id);
1001
1002         apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1003         if (!apic)
1004                 goto nomem;
1005
1006         vcpu->arch.apic = apic;
1007
1008         apic->regs_page = alloc_page(GFP_KERNEL);
1009         if (apic->regs_page == NULL) {
1010                 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1011                        vcpu->vcpu_id);
1012                 goto nomem_free_apic;
1013         }
1014         apic->regs = page_address(apic->regs_page);
1015         memset(apic->regs, 0, PAGE_SIZE);
1016         apic->vcpu = vcpu;
1017
1018         hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1019                      HRTIMER_MODE_ABS);
1020         apic->lapic_timer.timer.function = kvm_timer_fn;
1021         apic->lapic_timer.t_ops = &lapic_timer_ops;
1022         apic->lapic_timer.kvm = vcpu->kvm;
1023         apic->lapic_timer.vcpu_id = vcpu->vcpu_id;
1024
1025         apic->base_address = APIC_DEFAULT_PHYS_BASE;
1026         vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE;
1027
1028         kvm_lapic_reset(vcpu);
1029         apic->dev.read = apic_mmio_read;
1030         apic->dev.write = apic_mmio_write;
1031         apic->dev.in_range = apic_mmio_range;
1032         apic->dev.private = apic;
1033
1034         return 0;
1035 nomem_free_apic:
1036         kfree(apic);
1037 nomem:
1038         return -ENOMEM;
1039 }
1040 EXPORT_SYMBOL_GPL(kvm_create_lapic);
1041
1042 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1043 {
1044         struct kvm_lapic *apic = vcpu->arch.apic;
1045         int highest_irr;
1046
1047         if (!apic || !apic_enabled(apic))
1048                 return -1;
1049
1050         apic_update_ppr(apic);
1051         highest_irr = apic_find_highest_irr(apic);
1052         if ((highest_irr == -1) ||
1053             ((highest_irr & 0xF0) <= apic_get_reg(apic, APIC_PROCPRI)))
1054                 return -1;
1055         return highest_irr;
1056 }
1057
1058 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1059 {
1060         u32 lvt0 = apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1061         int r = 0;
1062
1063         if (vcpu->vcpu_id == 0) {
1064                 if (!apic_hw_enabled(vcpu->arch.apic))
1065                         r = 1;
1066                 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1067                     GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1068                         r = 1;
1069         }
1070         return r;
1071 }
1072
1073 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1074 {
1075         struct kvm_lapic *apic = vcpu->arch.apic;
1076
1077         if (apic && atomic_read(&apic->lapic_timer.pending) > 0) {
1078                 if (kvm_apic_local_deliver(apic, APIC_LVTT))
1079                         atomic_dec(&apic->lapic_timer.pending);
1080         }
1081 }
1082
1083 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1084 {
1085         int vector = kvm_apic_has_interrupt(vcpu);
1086         struct kvm_lapic *apic = vcpu->arch.apic;
1087
1088         if (vector == -1)
1089                 return -1;
1090
1091         apic_set_vector(vector, apic->regs + APIC_ISR);
1092         apic_update_ppr(apic);
1093         apic_clear_irr(vector, apic);
1094         return vector;
1095 }
1096
1097 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu)
1098 {
1099         struct kvm_lapic *apic = vcpu->arch.apic;
1100
1101         apic->base_address = vcpu->arch.apic_base &
1102                              MSR_IA32_APICBASE_BASE;
1103         apic_set_reg(apic, APIC_LVR, APIC_VERSION);
1104         apic_update_ppr(apic);
1105         hrtimer_cancel(&apic->lapic_timer.timer);
1106         update_divide_count(apic);
1107         start_apic_timer(apic);
1108 }
1109
1110 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1111 {
1112         struct kvm_lapic *apic = vcpu->arch.apic;
1113         struct hrtimer *timer;
1114
1115         if (!apic)
1116                 return;
1117
1118         timer = &apic->lapic_timer.timer;
1119         if (hrtimer_cancel(timer))
1120                 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
1121 }
1122
1123 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1124 {
1125         u32 data;
1126         void *vapic;
1127
1128         if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1129                 return;
1130
1131         vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1132         data = *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr));
1133         kunmap_atomic(vapic, KM_USER0);
1134
1135         apic_set_tpr(vcpu->arch.apic, data & 0xff);
1136 }
1137
1138 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1139 {
1140         u32 data, tpr;
1141         int max_irr, max_isr;
1142         struct kvm_lapic *apic;
1143         void *vapic;
1144
1145         if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1146                 return;
1147
1148         apic = vcpu->arch.apic;
1149         tpr = apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1150         max_irr = apic_find_highest_irr(apic);
1151         if (max_irr < 0)
1152                 max_irr = 0;
1153         max_isr = apic_find_highest_isr(apic);
1154         if (max_isr < 0)
1155                 max_isr = 0;
1156         data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1157
1158         vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1159         *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)) = data;
1160         kunmap_atomic(vapic, KM_USER0);
1161 }
1162
1163 void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1164 {
1165         if (!irqchip_in_kernel(vcpu->kvm))
1166                 return;
1167
1168         vcpu->arch.apic->vapic_addr = vapic_addr;
1169 }