SAFE public projects git trees. - safe/jmp/linux-2.6/blob - arch/x86/kvm/lapic.c

   1
   2 /*
   3  * Local APIC virtualization
   4  *
   5  * Copyright (C) 2006 Qumranet, Inc.
   6  * Copyright (C) 2007 Novell
   7  * Copyright (C) 2007 Intel
   8  *
   9  * Authors:
  10  *   Dor Laor <dor.laor@qumranet.com>
  11  *   Gregory Haskins <ghaskins@novell.com>
  12  *   Yaozu (Eddie) Dong <eddie.dong@intel.com>
  13  *
  14  * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
  15  *
  16  * This work is licensed under the terms of the GNU GPL, version 2.  See
  17  * the COPYING file in the top-level directory.
  18  */
  19
  20 #include <linux/kvm_host.h>
  21 #include <linux/kvm.h>
  22 #include <linux/mm.h>
  23 #include <linux/highmem.h>
  24 #include <linux/smp.h>
  25 #include <linux/hrtimer.h>
  26 #include <linux/io.h>
  27 #include <linux/module.h>
  28 #include <linux/math64.h>
  29 #include <asm/processor.h>
  30 #include <asm/msr.h>
  31 #include <asm/page.h>
  32 #include <asm/current.h>
  33 #include <asm/apicdef.h>
  34 #include <asm/atomic.h>
  35 #include <asm/apicdef.h>
  36 #include "kvm_cache_regs.h"
  37 #include "irq.h"
  38 #include "trace.h"
  39 #include "x86.h"
  40
  41 #ifndef CONFIG_X86_64
  42 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
  43 #else
  44 #define mod_64(x, y) ((x) % (y))
  45 #endif
  46
  47 #define PRId64 "d"
  48 #define PRIx64 "llx"
  49 #define PRIu64 "u"
  50 #define PRIo64 "o"
  51
  52 #define APIC_BUS_CYCLE_NS 1
  53
  54 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
  55 #define apic_debug(fmt, arg...)
  56
  57 #define APIC_LVT_NUM                    6
  58 /* 14 is the version for Xeon and Pentium 8.4.8*/
  59 #define APIC_VERSION                    (0x14UL | ((APIC_LVT_NUM - 1) << 16))
  60 #define LAPIC_MMIO_LENGTH               (1 << 12)
  61 /* followed define is not in apicdef.h */
  62 #define APIC_SHORT_MASK                 0xc0000
  63 #define APIC_DEST_NOSHORT               0x0
  64 #define APIC_DEST_MASK                  0x800
  65 #define MAX_APIC_VECTOR                 256
  66
  67 #define VEC_POS(v) ((v) & (32 - 1))
  68 #define REG_POS(v) (((v) >> 5) << 4)
  69
  70 static inline u32 apic_get_reg(struct kvm_lapic *apic, int reg_off)
  71 {
  72         return *((u32 *) (apic->regs + reg_off));
  73 }
  74
  75 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
  76 {
  77         *((u32 *) (apic->regs + reg_off)) = val;
  78 }
  79
  80 static inline int apic_test_and_set_vector(int vec, void *bitmap)
  81 {
  82         return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  83 }
  84
  85 static inline int apic_test_and_clear_vector(int vec, void *bitmap)
  86 {
  87         return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  88 }
  89
  90 static inline void apic_set_vector(int vec, void *bitmap)
  91 {
  92         set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  93 }
  94
  95 static inline void apic_clear_vector(int vec, void *bitmap)
  96 {
  97         clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  98 }
  99
 100 static inline int apic_hw_enabled(struct kvm_lapic *apic)
 101 {
 102         return (apic)->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
 103 }
 104
 105 static inline int  apic_sw_enabled(struct kvm_lapic *apic)
 106 {
 107         return apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED;
 108 }
 109
 110 static inline int apic_enabled(struct kvm_lapic *apic)
 111 {
 112         return apic_sw_enabled(apic) && apic_hw_enabled(apic);
 113 }
 114
 115 #define LVT_MASK        \
 116         (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
 117
 118 #define LINT_MASK       \
 119         (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
 120          APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
 121
 122 static inline int kvm_apic_id(struct kvm_lapic *apic)
 123 {
 124         return (apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
 125 }
 126
 127 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
 128 {
 129         return !(apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
 130 }
 131
 132 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
 133 {
 134         return apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
 135 }
 136
 137 static inline int apic_lvtt_period(struct kvm_lapic *apic)
 138 {
 139         return apic_get_reg(apic, APIC_LVTT) & APIC_LVT_TIMER_PERIODIC;
 140 }
 141
 142 static inline int apic_lvt_nmi_mode(u32 lvt_val)
 143 {
 144         return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
 145 }
 146
 147 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
 148 {
 149         struct kvm_lapic *apic = vcpu->arch.apic;
 150         struct kvm_cpuid_entry2 *feat;
 151         u32 v = APIC_VERSION;
 152
 153         if (!irqchip_in_kernel(vcpu->kvm))
 154                 return;
 155
 156         feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
 157         if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
 158                 v |= APIC_LVR_DIRECTED_EOI;
 159         apic_set_reg(apic, APIC_LVR, v);
 160 }
 161
 162 static inline int apic_x2apic_mode(struct kvm_lapic *apic)
 163 {
 164         return apic->vcpu->arch.apic_base & X2APIC_ENABLE;
 165 }
 166
 167 static unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
 168         LVT_MASK | APIC_LVT_TIMER_PERIODIC,     /* LVTT */
 169         LVT_MASK | APIC_MODE_MASK,      /* LVTTHMR */
 170         LVT_MASK | APIC_MODE_MASK,      /* LVTPC */
 171         LINT_MASK, LINT_MASK,   /* LVT0-1 */
 172         LVT_MASK                /* LVTERR */
 173 };
 174
 175 static int find_highest_vector(void *bitmap)
 176 {
 177         u32 *word = bitmap;
 178         int word_offset = MAX_APIC_VECTOR >> 5;
 179
 180         while ((word_offset != 0) && (word[(--word_offset) << 2] == 0))
 181                 continue;
 182
 183         if (likely(!word_offset && !word[0]))
 184                 return -1;
 185         else
 186                 return fls(word[word_offset << 2]) - 1 + (word_offset << 5);
 187 }
 188
 189 static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic)
 190 {
 191         apic->irr_pending = true;
 192         return apic_test_and_set_vector(vec, apic->regs + APIC_IRR);
 193 }
 194
 195 static inline int apic_search_irr(struct kvm_lapic *apic)
 196 {
 197         return find_highest_vector(apic->regs + APIC_IRR);
 198 }
 199
 200 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
 201 {
 202         int result;
 203
 204         if (!apic->irr_pending)
 205                 return -1;
 206
 207         result = apic_search_irr(apic);
 208         ASSERT(result == -1 || result >= 16);
 209
 210         return result;
 211 }
 212
 213 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
 214 {
 215         apic->irr_pending = false;
 216         apic_clear_vector(vec, apic->regs + APIC_IRR);
 217         if (apic_search_irr(apic) != -1)
 218                 apic->irr_pending = true;
 219 }
 220
 221 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
 222 {
 223         struct kvm_lapic *apic = vcpu->arch.apic;
 224         int highest_irr;
 225
 226         /* This may race with setting of irr in __apic_accept_irq() and
 227          * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
 228          * will cause vmexit immediately and the value will be recalculated
 229          * on the next vmentry.
 230          */
 231         if (!apic)
 232                 return 0;
 233         highest_irr = apic_find_highest_irr(apic);
 234
 235         return highest_irr;
 236 }
 237
 238 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 239                              int vector, int level, int trig_mode);
 240
 241 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq)
 242 {
 243         struct kvm_lapic *apic = vcpu->arch.apic;
 244
 245         return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
 246                         irq->level, irq->trig_mode);
 247 }
 248
 249 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
 250 {
 251         int result;
 252
 253         result = find_highest_vector(apic->regs + APIC_ISR);
 254         ASSERT(result == -1 || result >= 16);
 255
 256         return result;
 257 }
 258
 259 static void apic_update_ppr(struct kvm_lapic *apic)
 260 {
 261         u32 tpr, isrv, ppr;
 262         int isr;
 263
 264         tpr = apic_get_reg(apic, APIC_TASKPRI);
 265         isr = apic_find_highest_isr(apic);
 266         isrv = (isr != -1) ? isr : 0;
 267
 268         if ((tpr & 0xf0) >= (isrv & 0xf0))
 269                 ppr = tpr & 0xff;
 270         else
 271                 ppr = isrv & 0xf0;
 272
 273         apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
 274                    apic, ppr, isr, isrv);
 275
 276         apic_set_reg(apic, APIC_PROCPRI, ppr);
 277 }
 278
 279 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
 280 {
 281         apic_set_reg(apic, APIC_TASKPRI, tpr);
 282         apic_update_ppr(apic);
 283 }
 284
 285 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest)
 286 {
 287         return dest == 0xff || kvm_apic_id(apic) == dest;
 288 }
 289
 290 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
 291 {
 292         int result = 0;
 293         u32 logical_id;
 294
 295         if (apic_x2apic_mode(apic)) {
 296                 logical_id = apic_get_reg(apic, APIC_LDR);
 297                 return logical_id & mda;
 298         }
 299
 300         logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR));
 301
 302         switch (apic_get_reg(apic, APIC_DFR)) {
 303         case APIC_DFR_FLAT:
 304                 if (logical_id & mda)
 305                         result = 1;
 306                 break;
 307         case APIC_DFR_CLUSTER:
 308                 if (((logical_id >> 4) == (mda >> 0x4))
 309                     && (logical_id & mda & 0xf))
 310                         result = 1;
 311                 break;
 312         default:
 313                 printk(KERN_WARNING "Bad DFR vcpu %d: %08x\n",
 314                        apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR));
 315                 break;
 316         }
 317
 318         return result;
 319 }
 320
 321 int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
 322                            int short_hand, int dest, int dest_mode)
 323 {
 324         int result = 0;
 325         struct kvm_lapic *target = vcpu->arch.apic;
 326
 327         apic_debug("target %p, source %p, dest 0x%x, "
 328                    "dest_mode 0x%x, short_hand 0x%x\n",
 329                    target, source, dest, dest_mode, short_hand);
 330
 331         ASSERT(!target);
 332         switch (short_hand) {
 333         case APIC_DEST_NOSHORT:
 334                 if (dest_mode == 0)
 335                         /* Physical mode. */
 336                         result = kvm_apic_match_physical_addr(target, dest);
 337                 else
 338                         /* Logical mode. */
 339                         result = kvm_apic_match_logical_addr(target, dest);
 340                 break;
 341         case APIC_DEST_SELF:
 342                 result = (target == source);
 343                 break;
 344         case APIC_DEST_ALLINC:
 345                 result = 1;
 346                 break;
 347         case APIC_DEST_ALLBUT:
 348                 result = (target != source);
 349                 break;
 350         default:
 351                 printk(KERN_WARNING "Bad dest shorthand value %x\n",
 352                        short_hand);
 353                 break;
 354         }
 355
 356         return result;
 357 }
 358
 359 /*
 360  * Add a pending IRQ into lapic.
 361  * Return 1 if successfully added and 0 if discarded.
 362  */
 363 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 364                              int vector, int level, int trig_mode)
 365 {
 366         int result = 0;
 367         struct kvm_vcpu *vcpu = apic->vcpu;
 368
 369         switch (delivery_mode) {
 370         case APIC_DM_LOWEST:
 371                 vcpu->arch.apic_arb_prio++;
 372         case APIC_DM_FIXED:
 373                 /* FIXME add logic for vcpu on reset */
 374                 if (unlikely(!apic_enabled(apic)))
 375                         break;
 376
 377                 result = !apic_test_and_set_irr(vector, apic);
 378                 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
 379                                           trig_mode, vector, !result);
 380                 if (!result) {
 381                         if (trig_mode)
 382                                 apic_debug("level trig mode repeatedly for "
 383                                                 "vector %d", vector);
 384                         break;
 385                 }
 386
 387                 if (trig_mode) {
 388                         apic_debug("level trig mode for vector %d", vector);
 389                         apic_set_vector(vector, apic->regs + APIC_TMR);
 390                 } else
 391                         apic_clear_vector(vector, apic->regs + APIC_TMR);
 392                 kvm_vcpu_kick(vcpu);
 393                 break;
 394
 395         case APIC_DM_REMRD:
 396                 printk(KERN_DEBUG "Ignoring delivery mode 3\n");
 397                 break;
 398
 399         case APIC_DM_SMI:
 400                 printk(KERN_DEBUG "Ignoring guest SMI\n");
 401                 break;
 402
 403         case APIC_DM_NMI:
 404                 result = 1;
 405                 kvm_inject_nmi(vcpu);
 406                 kvm_vcpu_kick(vcpu);
 407                 break;
 408
 409         case APIC_DM_INIT:
 410                 if (level) {
 411                         result = 1;
 412                         if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
 413                                 printk(KERN_DEBUG
 414                                        "INIT on a runnable vcpu %d\n",
 415                                        vcpu->vcpu_id);
 416                         vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
 417                         kvm_vcpu_kick(vcpu);
 418                 } else {
 419                         apic_debug("Ignoring de-assert INIT to vcpu %d\n",
 420                                    vcpu->vcpu_id);
 421                 }
 422                 break;
 423
 424         case APIC_DM_STARTUP:
 425                 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
 426                            vcpu->vcpu_id, vector);
 427                 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
 428                         result = 1;
 429                         vcpu->arch.sipi_vector = vector;
 430                         vcpu->arch.mp_state = KVM_MP_STATE_SIPI_RECEIVED;
 431                         kvm_vcpu_kick(vcpu);
 432                 }
 433                 break;
 434
 435         case APIC_DM_EXTINT:
 436                 /*
 437                  * Should only be called by kvm_apic_local_deliver() with LVT0,
 438                  * before NMI watchdog was enabled. Already handled by
 439                  * kvm_apic_accept_pic_intr().
 440                  */
 441                 break;
 442
 443         default:
 444                 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
 445                        delivery_mode);
 446                 break;
 447         }
 448         return result;
 449 }
 450
 451 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
 452 {
 453         return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
 454 }
 455
 456 static void apic_set_eoi(struct kvm_lapic *apic)
 457 {
 458         int vector = apic_find_highest_isr(apic);
 459         int trigger_mode;
 460         /*
 461          * Not every write EOI will has corresponding ISR,
 462          * one example is when Kernel check timer on setup_IO_APIC
 463          */
 464         if (vector == -1)
 465                 return;
 466
 467         apic_clear_vector(vector, apic->regs + APIC_ISR);
 468         apic_update_ppr(apic);
 469
 470         if (apic_test_and_clear_vector(vector, apic->regs + APIC_TMR))
 471                 trigger_mode = IOAPIC_LEVEL_TRIG;
 472         else
 473                 trigger_mode = IOAPIC_EDGE_TRIG;
 474         if (!(apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI))
 475                 kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode);
 476 }
 477
 478 static void apic_send_ipi(struct kvm_lapic *apic)
 479 {
 480         u32 icr_low = apic_get_reg(apic, APIC_ICR);
 481         u32 icr_high = apic_get_reg(apic, APIC_ICR2);
 482         struct kvm_lapic_irq irq;
 483
 484         irq.vector = icr_low & APIC_VECTOR_MASK;
 485         irq.delivery_mode = icr_low & APIC_MODE_MASK;
 486         irq.dest_mode = icr_low & APIC_DEST_MASK;
 487         irq.level = icr_low & APIC_INT_ASSERT;
 488         irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
 489         irq.shorthand = icr_low & APIC_SHORT_MASK;
 490         if (apic_x2apic_mode(apic))
 491                 irq.dest_id = icr_high;
 492         else
 493                 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
 494
 495         trace_kvm_apic_ipi(icr_low, irq.dest_id);
 496
 497         apic_debug("icr_high 0x%x, icr_low 0x%x, "
 498                    "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
 499                    "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
 500                    icr_high, icr_low, irq.shorthand, irq.dest_id,
 501                    irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
 502                    irq.vector);
 503
 504         kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq);
 505 }
 506
 507 static u32 apic_get_tmcct(struct kvm_lapic *apic)
 508 {
 509         ktime_t remaining;
 510         s64 ns;
 511         u32 tmcct;
 512
 513         ASSERT(apic != NULL);
 514
 515         /* if initial count is 0, current count should also be 0 */
 516         if (apic_get_reg(apic, APIC_TMICT) == 0)
 517                 return 0;
 518
 519         remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
 520         if (ktime_to_ns(remaining) < 0)
 521                 remaining = ktime_set(0, 0);
 522
 523         ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
 524         tmcct = div64_u64(ns,
 525                          (APIC_BUS_CYCLE_NS * apic->divide_count));
 526
 527         return tmcct;
 528 }
 529
 530 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
 531 {
 532         struct kvm_vcpu *vcpu = apic->vcpu;
 533         struct kvm_run *run = vcpu->run;
 534
 535         set_bit(KVM_REQ_REPORT_TPR_ACCESS, &vcpu->requests);
 536         run->tpr_access.rip = kvm_rip_read(vcpu);
 537         run->tpr_access.is_write = write;
 538 }
 539
 540 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
 541 {
 542         if (apic->vcpu->arch.tpr_access_reporting)
 543                 __report_tpr_access(apic, write);
 544 }
 545
 546 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
 547 {
 548         u32 val = 0;
 549
 550         if (offset >= LAPIC_MMIO_LENGTH)
 551                 return 0;
 552
 553         switch (offset) {
 554         case APIC_ID:
 555                 if (apic_x2apic_mode(apic))
 556                         val = kvm_apic_id(apic);
 557                 else
 558                         val = kvm_apic_id(apic) << 24;
 559                 break;
 560         case APIC_ARBPRI:
 561                 printk(KERN_WARNING "Access APIC ARBPRI register "
 562                        "which is for P6\n");
 563                 break;
 564
 565         case APIC_TMCCT:        /* Timer CCR */
 566                 val = apic_get_tmcct(apic);
 567                 break;
 568
 569         case APIC_TASKPRI:
 570                 report_tpr_access(apic, false);
 571                 /* fall thru */
 572         default:
 573                 apic_update_ppr(apic);
 574                 val = apic_get_reg(apic, offset);
 575                 break;
 576         }
 577
 578         return val;
 579 }
 580
 581 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
 582 {
 583         return container_of(dev, struct kvm_lapic, dev);
 584 }
 585
 586 static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
 587                 void *data)
 588 {
 589         unsigned char alignment = offset & 0xf;
 590         u32 result;
 591         /* this bitmask has a bit cleared for each reserver register */
 592         static const u64 rmask = 0x43ff01ffffffe70cULL;
 593
 594         if ((alignment + len) > 4) {
 595                 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
 596                            offset, len);
 597                 return 1;
 598         }
 599
 600         if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
 601                 apic_debug("KVM_APIC_READ: read reserved register %x\n",
 602                            offset);
 603                 return 1;
 604         }
 605
 606         result = __apic_read(apic, offset & ~0xf);
 607
 608         trace_kvm_apic_read(offset, result);
 609
 610         switch (len) {
 611         case 1:
 612         case 2:
 613         case 4:
 614                 memcpy(data, (char *)&result + alignment, len);
 615                 break;
 616         default:
 617                 printk(KERN_ERR "Local APIC read with len = %x, "
 618                        "should be 1,2, or 4 instead\n", len);
 619                 break;
 620         }
 621         return 0;
 622 }
 623
 624 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
 625 {
 626         return apic_hw_enabled(apic) &&
 627             addr >= apic->base_address &&
 628             addr < apic->base_address + LAPIC_MMIO_LENGTH;
 629 }
 630
 631 static int apic_mmio_read(struct kvm_io_device *this,
 632                            gpa_t address, int len, void *data)
 633 {
 634         struct kvm_lapic *apic = to_lapic(this);
 635         u32 offset = address - apic->base_address;
 636
 637         if (!apic_mmio_in_range(apic, address))
 638                 return -EOPNOTSUPP;
 639
 640         apic_reg_read(apic, offset, len, data);
 641
 642         return 0;
 643 }
 644
 645 static void update_divide_count(struct kvm_lapic *apic)
 646 {
 647         u32 tmp1, tmp2, tdcr;
 648
 649         tdcr = apic_get_reg(apic, APIC_TDCR);
 650         tmp1 = tdcr & 0xf;
 651         tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
 652         apic->divide_count = 0x1 << (tmp2 & 0x7);
 653
 654         apic_debug("timer divide count is 0x%x\n",
 655                                    apic->divide_count);
 656 }
 657
 658 static void start_apic_timer(struct kvm_lapic *apic)
 659 {
 660         ktime_t now = apic->lapic_timer.timer.base->get_time();
 661
 662         apic->lapic_timer.period = (u64)apic_get_reg(apic, APIC_TMICT) *
 663                     APIC_BUS_CYCLE_NS * apic->divide_count;
 664         atomic_set(&apic->lapic_timer.pending, 0);
 665
 666         if (!apic->lapic_timer.period)
 667                 return;
 668         /*
 669          * Do not allow the guest to program periodic timers with small
 670          * interval, since the hrtimers are not throttled by the host
 671          * scheduler.
 672          */
 673         if (apic_lvtt_period(apic)) {
 674                 if (apic->lapic_timer.period < NSEC_PER_MSEC/2)
 675                         apic->lapic_timer.period = NSEC_PER_MSEC/2;
 676         }
 677
 678         hrtimer_start(&apic->lapic_timer.timer,
 679                       ktime_add_ns(now, apic->lapic_timer.period),
 680                       HRTIMER_MODE_ABS);
 681
 682         apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
 683                            PRIx64 ", "
 684                            "timer initial count 0x%x, period %lldns, "
 685                            "expire @ 0x%016" PRIx64 ".\n", __func__,
 686                            APIC_BUS_CYCLE_NS, ktime_to_ns(now),
 687                            apic_get_reg(apic, APIC_TMICT),
 688                            apic->lapic_timer.period,
 689                            ktime_to_ns(ktime_add_ns(now,
 690                                         apic->lapic_timer.period)));
 691 }
 692
 693 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
 694 {
 695         int nmi_wd_enabled = apic_lvt_nmi_mode(apic_get_reg(apic, APIC_LVT0));
 696
 697         if (apic_lvt_nmi_mode(lvt0_val)) {
 698                 if (!nmi_wd_enabled) {
 699                         apic_debug("Receive NMI setting on APIC_LVT0 "
 700                                    "for cpu %d\n", apic->vcpu->vcpu_id);
 701                         apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
 702                 }
 703         } else if (nmi_wd_enabled)
 704                 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
 705 }
 706
 707 static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
 708 {
 709         int ret = 0;
 710
 711         trace_kvm_apic_write(reg, val);
 712
 713         switch (reg) {
 714         case APIC_ID:           /* Local APIC ID */
 715                 if (!apic_x2apic_mode(apic))
 716                         apic_set_reg(apic, APIC_ID, val);
 717                 else
 718                         ret = 1;
 719                 break;
 720
 721         case APIC_TASKPRI:
 722                 report_tpr_access(apic, true);
 723                 apic_set_tpr(apic, val & 0xff);
 724                 break;
 725
 726         case APIC_EOI:
 727                 apic_set_eoi(apic);
 728                 break;
 729
 730         case APIC_LDR:
 731                 if (!apic_x2apic_mode(apic))
 732                         apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK);
 733                 else
 734                         ret = 1;
 735                 break;
 736
 737         case APIC_DFR:
 738                 if (!apic_x2apic_mode(apic))
 739                         apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
 740                 else
 741                         ret = 1;
 742                 break;
 743
 744         case APIC_SPIV: {
 745                 u32 mask = 0x3ff;
 746                 if (apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
 747                         mask |= APIC_SPIV_DIRECTED_EOI;
 748                 apic_set_reg(apic, APIC_SPIV, val & mask);
 749                 if (!(val & APIC_SPIV_APIC_ENABLED)) {
 750                         int i;
 751                         u32 lvt_val;
 752
 753                         for (i = 0; i < APIC_LVT_NUM; i++) {
 754                                 lvt_val = apic_get_reg(apic,
 755                                                        APIC_LVTT + 0x10 * i);
 756                                 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
 757                                              lvt_val | APIC_LVT_MASKED);
 758                         }
 759                         atomic_set(&apic->lapic_timer.pending, 0);
 760
 761                 }
 762                 break;
 763         }
 764         case APIC_ICR:
 765                 /* No delay here, so we always clear the pending bit */
 766                 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
 767                 apic_send_ipi(apic);
 768                 break;
 769
 770         case APIC_ICR2:
 771                 if (!apic_x2apic_mode(apic))
 772                         val &= 0xff000000;
 773                 apic_set_reg(apic, APIC_ICR2, val);
 774                 break;
 775
 776         case APIC_LVT0:
 777                 apic_manage_nmi_watchdog(apic, val);
 778         case APIC_LVTT:
 779         case APIC_LVTTHMR:
 780         case APIC_LVTPC:
 781         case APIC_LVT1:
 782         case APIC_LVTERR:
 783                 /* TODO: Check vector */
 784                 if (!apic_sw_enabled(apic))
 785                         val |= APIC_LVT_MASKED;
 786
 787                 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
 788                 apic_set_reg(apic, reg, val);
 789
 790                 break;
 791
 792         case APIC_TMICT:
 793                 hrtimer_cancel(&apic->lapic_timer.timer);
 794                 apic_set_reg(apic, APIC_TMICT, val);
 795                 start_apic_timer(apic);
 796                 break;
 797
 798         case APIC_TDCR:
 799                 if (val & 4)
 800                         printk(KERN_ERR "KVM_WRITE:TDCR %x\n", val);
 801                 apic_set_reg(apic, APIC_TDCR, val);
 802                 update_divide_count(apic);
 803                 break;
 804
 805         case APIC_ESR:
 806                 if (apic_x2apic_mode(apic) && val != 0) {
 807                         printk(KERN_ERR "KVM_WRITE:ESR not zero %x\n", val);
 808                         ret = 1;
 809                 }
 810                 break;
 811
 812         case APIC_SELF_IPI:
 813                 if (apic_x2apic_mode(apic)) {
 814                         apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
 815                 } else
 816                         ret = 1;
 817                 break;
 818         default:
 819                 ret = 1;
 820                 break;
 821         }
 822         if (ret)
 823                 apic_debug("Local APIC Write to read-only register %x\n", reg);
 824         return ret;
 825 }
 826
 827 static int apic_mmio_write(struct kvm_io_device *this,
 828                             gpa_t address, int len, const void *data)
 829 {
 830         struct kvm_lapic *apic = to_lapic(this);
 831         unsigned int offset = address - apic->base_address;
 832         u32 val;
 833
 834         if (!apic_mmio_in_range(apic, address))
 835                 return -EOPNOTSUPP;
 836
 837         /*
 838          * APIC register must be aligned on 128-bits boundary.
 839          * 32/64/128 bits registers must be accessed thru 32 bits.
 840          * Refer SDM 8.4.1
 841          */
 842         if (len != 4 || (offset & 0xf)) {
 843                 /* Don't shout loud, $infamous_os would cause only noise. */
 844                 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
 845                 return 0;
 846         }
 847
 848         val = *(u32*)data;
 849
 850         /* too common printing */
 851         if (offset != APIC_EOI)
 852                 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
 853                            "0x%x\n", __func__, offset, len, val);
 854
 855         apic_reg_write(apic, offset & 0xff0, val);
 856
 857         return 0;
 858 }
 859
 860 void kvm_free_lapic(struct kvm_vcpu *vcpu)
 861 {
 862         if (!vcpu->arch.apic)
 863                 return;
 864
 865         hrtimer_cancel(&vcpu->arch.apic->lapic_timer.timer);
 866
 867         if (vcpu->arch.apic->regs_page)
 868                 __free_page(vcpu->arch.apic->regs_page);
 869
 870         kfree(vcpu->arch.apic);
 871 }
 872
 873 /*
 874  *----------------------------------------------------------------------
 875  * LAPIC interface
 876  *----------------------------------------------------------------------
 877  */
 878
 879 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
 880 {
 881         struct kvm_lapic *apic = vcpu->arch.apic;
 882
 883         if (!apic)
 884                 return;
 885         apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
 886                      | (apic_get_reg(apic, APIC_TASKPRI) & 4));
 887 }
 888
 889 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
 890 {
 891         struct kvm_lapic *apic = vcpu->arch.apic;
 892         u64 tpr;
 893
 894         if (!apic)
 895                 return 0;
 896         tpr = (u64) apic_get_reg(apic, APIC_TASKPRI);
 897
 898         return (tpr & 0xf0) >> 4;
 899 }
 900
 901 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
 902 {
 903         struct kvm_lapic *apic = vcpu->arch.apic;
 904
 905         if (!apic) {
 906                 value |= MSR_IA32_APICBASE_BSP;
 907                 vcpu->arch.apic_base = value;
 908                 return;
 909         }
 910
 911         if (!kvm_vcpu_is_bsp(apic->vcpu))
 912                 value &= ~MSR_IA32_APICBASE_BSP;
 913
 914         vcpu->arch.apic_base = value;
 915         if (apic_x2apic_mode(apic)) {
 916                 u32 id = kvm_apic_id(apic);
 917                 u32 ldr = ((id & ~0xf) << 16) | (1 << (id & 0xf));
 918                 apic_set_reg(apic, APIC_LDR, ldr);
 919         }
 920         apic->base_address = apic->vcpu->arch.apic_base &
 921                              MSR_IA32_APICBASE_BASE;
 922
 923         /* with FSB delivery interrupt, we can restart APIC functionality */
 924         apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
 925                    "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
 926
 927 }
 928
 929 void kvm_lapic_reset(struct kvm_vcpu *vcpu)
 930 {
 931         struct kvm_lapic *apic;
 932         int i;
 933
 934         apic_debug("%s\n", __func__);
 935
 936         ASSERT(vcpu);
 937         apic = vcpu->arch.apic;
 938         ASSERT(apic != NULL);
 939
 940         /* Stop the timer in case it's a reset to an active apic */
 941         hrtimer_cancel(&apic->lapic_timer.timer);
 942
 943         apic_set_reg(apic, APIC_ID, vcpu->vcpu_id << 24);
 944         kvm_apic_set_version(apic->vcpu);
 945
 946         for (i = 0; i < APIC_LVT_NUM; i++)
 947                 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
 948         apic_set_reg(apic, APIC_LVT0,
 949                      SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
 950
 951         apic_set_reg(apic, APIC_DFR, 0xffffffffU);
 952         apic_set_reg(apic, APIC_SPIV, 0xff);
 953         apic_set_reg(apic, APIC_TASKPRI, 0);
 954         apic_set_reg(apic, APIC_LDR, 0);
 955         apic_set_reg(apic, APIC_ESR, 0);
 956         apic_set_reg(apic, APIC_ICR, 0);
 957         apic_set_reg(apic, APIC_ICR2, 0);
 958         apic_set_reg(apic, APIC_TDCR, 0);
 959         apic_set_reg(apic, APIC_TMICT, 0);
 960         for (i = 0; i < 8; i++) {
 961                 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
 962                 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
 963                 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
 964         }
 965         apic->irr_pending = false;
 966         update_divide_count(apic);
 967         atomic_set(&apic->lapic_timer.pending, 0);
 968         if (kvm_vcpu_is_bsp(vcpu))
 969                 vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP;
 970         apic_update_ppr(apic);
 971
 972         vcpu->arch.apic_arb_prio = 0;
 973
 974         apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr="
 975                    "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
 976                    vcpu, kvm_apic_id(apic),
 977                    vcpu->arch.apic_base, apic->base_address);
 978 }
 979
 980 bool kvm_apic_present(struct kvm_vcpu *vcpu)
 981 {
 982         return vcpu->arch.apic && apic_hw_enabled(vcpu->arch.apic);
 983 }
 984
 985 int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
 986 {
 987         return kvm_apic_present(vcpu) && apic_sw_enabled(vcpu->arch.apic);
 988 }
 989
 990 /*
 991  *----------------------------------------------------------------------
 992  * timer interface
 993  *----------------------------------------------------------------------
 994  */
 995
 996 static bool lapic_is_periodic(struct kvm_timer *ktimer)
 997 {
 998         struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic,
 999                                               lapic_timer);
1000         return apic_lvtt_period(apic);
1001 }
1002
1003 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1004 {
1005         struct kvm_lapic *lapic = vcpu->arch.apic;
1006
1007         if (lapic && apic_enabled(lapic) && apic_lvt_enabled(lapic, APIC_LVTT))
1008                 return atomic_read(&lapic->lapic_timer.pending);
1009
1010         return 0;
1011 }
1012
1013 static int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1014 {
1015         u32 reg = apic_get_reg(apic, lvt_type);
1016         int vector, mode, trig_mode;
1017
1018         if (apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
1019                 vector = reg & APIC_VECTOR_MASK;
1020                 mode = reg & APIC_MODE_MASK;
1021                 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
1022                 return __apic_accept_irq(apic, mode, vector, 1, trig_mode);
1023         }
1024         return 0;
1025 }
1026
1027 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
1028 {
1029         struct kvm_lapic *apic = vcpu->arch.apic;
1030
1031         if (apic)
1032                 kvm_apic_local_deliver(apic, APIC_LVT0);
1033 }
1034
1035 static struct kvm_timer_ops lapic_timer_ops = {
1036         .is_periodic = lapic_is_periodic,
1037 };
1038
1039 static const struct kvm_io_device_ops apic_mmio_ops = {
1040         .read     = apic_mmio_read,
1041         .write    = apic_mmio_write,
1042 };
1043
1044 int kvm_create_lapic(struct kvm_vcpu *vcpu)
1045 {
1046         struct kvm_lapic *apic;
1047
1048         ASSERT(vcpu != NULL);
1049         apic_debug("apic_init %d\n", vcpu->vcpu_id);
1050
1051         apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1052         if (!apic)
1053                 goto nomem;
1054
1055         vcpu->arch.apic = apic;
1056
1057         apic->regs_page = alloc_page(GFP_KERNEL);
1058         if (apic->regs_page == NULL) {
1059                 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1060                        vcpu->vcpu_id);
1061                 goto nomem_free_apic;
1062         }
1063         apic->regs = page_address(apic->regs_page);
1064         memset(apic->regs, 0, PAGE_SIZE);
1065         apic->vcpu = vcpu;
1066
1067         hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1068                      HRTIMER_MODE_ABS);
1069         apic->lapic_timer.timer.function = kvm_timer_fn;
1070         apic->lapic_timer.t_ops = &lapic_timer_ops;
1071         apic->lapic_timer.kvm = vcpu->kvm;
1072         apic->lapic_timer.vcpu = vcpu;
1073
1074         apic->base_address = APIC_DEFAULT_PHYS_BASE;
1075         vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE;
1076
1077         kvm_lapic_reset(vcpu);
1078         kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
1079
1080         return 0;
1081 nomem_free_apic:
1082         kfree(apic);
1083 nomem:
1084         return -ENOMEM;
1085 }
1086
1087 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1088 {
1089         struct kvm_lapic *apic = vcpu->arch.apic;
1090         int highest_irr;
1091
1092         if (!apic || !apic_enabled(apic))
1093                 return -1;
1094
1095         apic_update_ppr(apic);
1096         highest_irr = apic_find_highest_irr(apic);
1097         if ((highest_irr == -1) ||
1098             ((highest_irr & 0xF0) <= apic_get_reg(apic, APIC_PROCPRI)))
1099                 return -1;
1100         return highest_irr;
1101 }
1102
1103 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1104 {
1105         u32 lvt0 = apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1106         int r = 0;
1107
1108         if (kvm_vcpu_is_bsp(vcpu)) {
1109                 if (!apic_hw_enabled(vcpu->arch.apic))
1110                         r = 1;
1111                 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1112                     GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1113                         r = 1;
1114         }
1115         return r;
1116 }
1117
1118 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1119 {
1120         struct kvm_lapic *apic = vcpu->arch.apic;
1121
1122         if (apic && atomic_read(&apic->lapic_timer.pending) > 0) {
1123                 if (kvm_apic_local_deliver(apic, APIC_LVTT))
1124                         atomic_dec(&apic->lapic_timer.pending);
1125         }
1126 }
1127
1128 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1129 {
1130         int vector = kvm_apic_has_interrupt(vcpu);
1131         struct kvm_lapic *apic = vcpu->arch.apic;
1132
1133         if (vector == -1)
1134                 return -1;
1135
1136         apic_set_vector(vector, apic->regs + APIC_ISR);
1137         apic_update_ppr(apic);
1138         apic_clear_irr(vector, apic);
1139         return vector;
1140 }
1141
1142 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu)
1143 {
1144         struct kvm_lapic *apic = vcpu->arch.apic;
1145
1146         apic->base_address = vcpu->arch.apic_base &
1147                              MSR_IA32_APICBASE_BASE;
1148         kvm_apic_set_version(vcpu);
1149
1150         apic_update_ppr(apic);
1151         hrtimer_cancel(&apic->lapic_timer.timer);
1152         update_divide_count(apic);
1153         start_apic_timer(apic);
1154 }
1155
1156 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1157 {
1158         struct kvm_lapic *apic = vcpu->arch.apic;
1159         struct hrtimer *timer;
1160
1161         if (!apic)
1162                 return;
1163
1164         timer = &apic->lapic_timer.timer;
1165         if (hrtimer_cancel(timer))
1166                 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
1167 }
1168
1169 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1170 {
1171         u32 data;
1172         void *vapic;
1173
1174         if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1175                 return;
1176
1177         vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1178         data = *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr));
1179         kunmap_atomic(vapic, KM_USER0);
1180
1181         apic_set_tpr(vcpu->arch.apic, data & 0xff);
1182 }
1183
1184 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1185 {
1186         u32 data, tpr;
1187         int max_irr, max_isr;
1188         struct kvm_lapic *apic;
1189         void *vapic;
1190
1191         if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1192                 return;
1193
1194         apic = vcpu->arch.apic;
1195         tpr = apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1196         max_irr = apic_find_highest_irr(apic);
1197         if (max_irr < 0)
1198                 max_irr = 0;
1199         max_isr = apic_find_highest_isr(apic);
1200         if (max_isr < 0)
1201                 max_isr = 0;
1202         data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1203
1204         vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1205         *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)) = data;
1206         kunmap_atomic(vapic, KM_USER0);
1207 }
1208
1209 void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1210 {
1211         if (!irqchip_in_kernel(vcpu->kvm))
1212                 return;
1213
1214         vcpu->arch.apic->vapic_addr = vapic_addr;
1215 }
1216
1217 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1218 {
1219         struct kvm_lapic *apic = vcpu->arch.apic;
1220         u32 reg = (msr - APIC_BASE_MSR) << 4;
1221
1222         if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1223                 return 1;
1224
1225         /* if this is ICR write vector before command */
1226         if (msr == 0x830)
1227                 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1228         return apic_reg_write(apic, reg, (u32)data);
1229 }
1230
1231 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
1232 {
1233         struct kvm_lapic *apic = vcpu->arch.apic;
1234         u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
1235
1236         if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1237                 return 1;
1238
1239         if (apic_reg_read(apic, reg, 4, &low))
1240                 return 1;
1241         if (msr == 0x830)
1242                 apic_reg_read(apic, APIC_ICR2, 4, &high);
1243
1244         *data = (((u64)high) << 32) | low;
1245
1246         return 0;
1247 }