3 * Local APIC virtualization
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
10 * Dor Laor <dor.laor@qumranet.com>
11 * Gregory Haskins <ghaskins@novell.com>
12 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
14 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
20 #include <linux/kvm_host.h>
21 #include <linux/kvm.h>
23 #include <linux/highmem.h>
24 #include <linux/smp.h>
25 #include <linux/hrtimer.h>
27 #include <linux/module.h>
28 #include <linux/math64.h>
29 #include <asm/processor.h>
32 #include <asm/current.h>
33 #include <asm/apicdef.h>
34 #include <asm/atomic.h>
35 #include "kvm_cache_regs.h"
39 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
41 #define mod_64(x, y) ((x) % (y))
49 #define APIC_BUS_CYCLE_NS 1
51 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
52 #define apic_debug(fmt, arg...)
54 #define APIC_LVT_NUM 6
55 /* 14 is the version for Xeon and Pentium 8.4.8*/
56 #define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
57 #define LAPIC_MMIO_LENGTH (1 << 12)
58 /* followed define is not in apicdef.h */
59 #define APIC_SHORT_MASK 0xc0000
60 #define APIC_DEST_NOSHORT 0x0
61 #define APIC_DEST_MASK 0x800
62 #define MAX_APIC_VECTOR 256
64 #define VEC_POS(v) ((v) & (32 - 1))
65 #define REG_POS(v) (((v) >> 5) << 4)
67 static inline u32 apic_get_reg(struct kvm_lapic *apic, int reg_off)
69 return *((u32 *) (apic->regs + reg_off));
72 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
74 *((u32 *) (apic->regs + reg_off)) = val;
77 static inline int apic_test_and_set_vector(int vec, void *bitmap)
79 return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
82 static inline int apic_test_and_clear_vector(int vec, void *bitmap)
84 return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
87 static inline void apic_set_vector(int vec, void *bitmap)
89 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
92 static inline void apic_clear_vector(int vec, void *bitmap)
94 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
97 static inline int apic_hw_enabled(struct kvm_lapic *apic)
99 return (apic)->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
102 static inline int apic_sw_enabled(struct kvm_lapic *apic)
104 return apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED;
107 static inline int apic_enabled(struct kvm_lapic *apic)
109 return apic_sw_enabled(apic) && apic_hw_enabled(apic);
113 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
116 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
117 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
119 static inline int kvm_apic_id(struct kvm_lapic *apic)
121 return (apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
124 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
126 return !(apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
129 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
131 return apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
134 static inline int apic_lvtt_period(struct kvm_lapic *apic)
136 return apic_get_reg(apic, APIC_LVTT) & APIC_LVT_TIMER_PERIODIC;
139 static inline int apic_lvt_nmi_mode(u32 lvt_val)
141 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
144 static unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
145 LVT_MASK | APIC_LVT_TIMER_PERIODIC, /* LVTT */
146 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
147 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
148 LINT_MASK, LINT_MASK, /* LVT0-1 */
149 LVT_MASK /* LVTERR */
152 static int find_highest_vector(void *bitmap)
155 int word_offset = MAX_APIC_VECTOR >> 5;
157 while ((word_offset != 0) && (word[(--word_offset) << 2] == 0))
160 if (likely(!word_offset && !word[0]))
163 return fls(word[word_offset << 2]) - 1 + (word_offset << 5);
166 static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic)
168 return apic_test_and_set_vector(vec, apic->regs + APIC_IRR);
171 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
173 apic_clear_vector(vec, apic->regs + APIC_IRR);
176 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
180 result = find_highest_vector(apic->regs + APIC_IRR);
181 ASSERT(result == -1 || result >= 16);
186 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
188 struct kvm_lapic *apic = vcpu->arch.apic;
193 highest_irr = apic_find_highest_irr(apic);
197 EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr);
199 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
200 int vector, int level, int trig_mode);
202 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, u8 vec, u8 dmode, u8 trig)
204 struct kvm_lapic *apic = vcpu->arch.apic;
208 case IOAPIC_LOWEST_PRIORITY:
209 lapic_dmode = APIC_DM_LOWEST;
212 lapic_dmode = APIC_DM_FIXED;
215 lapic_dmode = APIC_DM_NMI;
218 printk(KERN_DEBUG"Ignoring delivery mode %d\n", dmode);
222 return __apic_accept_irq(apic, lapic_dmode, vec, 1, trig);
225 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
229 result = find_highest_vector(apic->regs + APIC_ISR);
230 ASSERT(result == -1 || result >= 16);
235 static void apic_update_ppr(struct kvm_lapic *apic)
240 tpr = apic_get_reg(apic, APIC_TASKPRI);
241 isr = apic_find_highest_isr(apic);
242 isrv = (isr != -1) ? isr : 0;
244 if ((tpr & 0xf0) >= (isrv & 0xf0))
249 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
250 apic, ppr, isr, isrv);
252 apic_set_reg(apic, APIC_PROCPRI, ppr);
255 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
257 apic_set_reg(apic, APIC_TASKPRI, tpr);
258 apic_update_ppr(apic);
261 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest)
263 return dest == 0xff || kvm_apic_id(apic) == dest;
266 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
271 logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR));
273 switch (apic_get_reg(apic, APIC_DFR)) {
275 if (logical_id & mda)
278 case APIC_DFR_CLUSTER:
279 if (((logical_id >> 4) == (mda >> 0x4))
280 && (logical_id & mda & 0xf))
284 printk(KERN_WARNING "Bad DFR vcpu %d: %08x\n",
285 apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR));
292 int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
293 int short_hand, int dest, int dest_mode)
296 struct kvm_lapic *target = vcpu->arch.apic;
298 apic_debug("target %p, source %p, dest 0x%x, "
299 "dest_mode 0x%x, short_hand 0x%x\n",
300 target, source, dest, dest_mode, short_hand);
303 switch (short_hand) {
304 case APIC_DEST_NOSHORT:
307 result = kvm_apic_match_physical_addr(target, dest);
310 result = kvm_apic_match_logical_addr(target, dest);
313 result = (target == source);
315 case APIC_DEST_ALLINC:
318 case APIC_DEST_ALLBUT:
319 result = (target != source);
322 printk(KERN_WARNING "Bad dest shorthand value %x\n",
331 * Add a pending IRQ into lapic.
332 * Return 1 if successfully added and 0 if discarded.
334 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
335 int vector, int level, int trig_mode)
338 struct kvm_vcpu *vcpu = apic->vcpu;
340 switch (delivery_mode) {
343 /* FIXME add logic for vcpu on reset */
344 if (unlikely(!apic_enabled(apic)))
347 result = !apic_test_and_set_irr(vector, apic);
350 apic_debug("level trig mode repeatedly for "
351 "vector %d", vector);
356 apic_debug("level trig mode for vector %d", vector);
357 apic_set_vector(vector, apic->regs + APIC_TMR);
359 apic_clear_vector(vector, apic->regs + APIC_TMR);
364 printk(KERN_DEBUG "Ignoring delivery mode 3\n");
368 printk(KERN_DEBUG "Ignoring guest SMI\n");
373 kvm_inject_nmi(vcpu);
380 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
382 "INIT on a runnable vcpu %d\n",
384 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
387 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
392 case APIC_DM_STARTUP:
393 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
394 vcpu->vcpu_id, vector);
395 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
397 vcpu->arch.sipi_vector = vector;
398 vcpu->arch.mp_state = KVM_MP_STATE_SIPI_RECEIVED;
405 * Should only be called by kvm_apic_local_deliver() with LVT0,
406 * before NMI watchdog was enabled. Already handled by
407 * kvm_apic_accept_pic_intr().
412 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
419 static struct kvm_lapic *kvm_apic_round_robin(struct kvm *kvm, u8 vector,
420 unsigned long *bitmap)
424 struct kvm_lapic *apic = NULL;
426 last = kvm->arch.round_robin_prev_vcpu;
430 if (++next == KVM_MAX_VCPUS)
432 if (kvm->vcpus[next] == NULL || !test_bit(next, bitmap))
434 apic = kvm->vcpus[next]->arch.apic;
435 if (apic && apic_enabled(apic))
438 } while (next != last);
439 kvm->arch.round_robin_prev_vcpu = next;
442 printk(KERN_DEBUG "vcpu not ready for apic_round_robin\n");
447 struct kvm_vcpu *kvm_get_lowest_prio_vcpu(struct kvm *kvm, u8 vector,
448 unsigned long *bitmap)
450 struct kvm_lapic *apic;
452 apic = kvm_apic_round_robin(kvm, vector, bitmap);
458 static void apic_set_eoi(struct kvm_lapic *apic)
460 int vector = apic_find_highest_isr(apic);
463 * Not every write EOI will has corresponding ISR,
464 * one example is when Kernel check timer on setup_IO_APIC
469 apic_clear_vector(vector, apic->regs + APIC_ISR);
470 apic_update_ppr(apic);
472 if (apic_test_and_clear_vector(vector, apic->regs + APIC_TMR))
473 trigger_mode = IOAPIC_LEVEL_TRIG;
475 trigger_mode = IOAPIC_EDGE_TRIG;
476 kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode);
479 static void apic_send_ipi(struct kvm_lapic *apic)
481 u32 icr_low = apic_get_reg(apic, APIC_ICR);
482 u32 icr_high = apic_get_reg(apic, APIC_ICR2);
484 unsigned int dest = GET_APIC_DEST_FIELD(icr_high);
485 unsigned int short_hand = icr_low & APIC_SHORT_MASK;
486 unsigned int trig_mode = icr_low & APIC_INT_LEVELTRIG;
487 unsigned int level = icr_low & APIC_INT_ASSERT;
488 unsigned int dest_mode = icr_low & APIC_DEST_MASK;
489 unsigned int delivery_mode = icr_low & APIC_MODE_MASK;
490 unsigned int vector = icr_low & APIC_VECTOR_MASK;
492 DECLARE_BITMAP(deliver_bitmask, KVM_MAX_VCPUS);
495 apic_debug("icr_high 0x%x, icr_low 0x%x, "
496 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
497 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
498 icr_high, icr_low, short_hand, dest,
499 trig_mode, level, dest_mode, delivery_mode, vector);
501 kvm_get_intr_delivery_bitmask(apic->vcpu->kvm, apic, dest, dest_mode,
502 delivery_mode == APIC_DM_LOWEST, short_hand,
505 while ((i = find_first_bit(deliver_bitmask, KVM_MAX_VCPUS))
507 struct kvm_vcpu *vcpu = apic->vcpu->kvm->vcpus[i];
508 __clear_bit(i, deliver_bitmask);
510 __apic_accept_irq(vcpu->arch.apic, delivery_mode,
511 vector, level, trig_mode);
515 static u32 apic_get_tmcct(struct kvm_lapic *apic)
521 ASSERT(apic != NULL);
523 /* if initial count is 0, current count should also be 0 */
524 if (apic_get_reg(apic, APIC_TMICT) == 0)
527 remaining = hrtimer_expires_remaining(&apic->lapic_timer.timer);
528 if (ktime_to_ns(remaining) < 0)
529 remaining = ktime_set(0, 0);
531 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
532 tmcct = div64_u64(ns,
533 (APIC_BUS_CYCLE_NS * apic->divide_count));
538 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
540 struct kvm_vcpu *vcpu = apic->vcpu;
541 struct kvm_run *run = vcpu->run;
543 set_bit(KVM_REQ_REPORT_TPR_ACCESS, &vcpu->requests);
544 run->tpr_access.rip = kvm_rip_read(vcpu);
545 run->tpr_access.is_write = write;
548 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
550 if (apic->vcpu->arch.tpr_access_reporting)
551 __report_tpr_access(apic, write);
554 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
558 KVMTRACE_1D(APIC_ACCESS, apic->vcpu, (u32)offset, handler);
560 if (offset >= LAPIC_MMIO_LENGTH)
565 printk(KERN_WARNING "Access APIC ARBPRI register "
566 "which is for P6\n");
569 case APIC_TMCCT: /* Timer CCR */
570 val = apic_get_tmcct(apic);
574 report_tpr_access(apic, false);
577 apic_update_ppr(apic);
578 val = apic_get_reg(apic, offset);
585 static void apic_mmio_read(struct kvm_io_device *this,
586 gpa_t address, int len, void *data)
588 struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
589 unsigned int offset = address - apic->base_address;
590 unsigned char alignment = offset & 0xf;
593 if ((alignment + len) > 4) {
594 printk(KERN_ERR "KVM_APIC_READ: alignment error %lx %d",
595 (unsigned long)address, len);
598 result = __apic_read(apic, offset & ~0xf);
604 memcpy(data, (char *)&result + alignment, len);
607 printk(KERN_ERR "Local APIC read with len = %x, "
608 "should be 1,2, or 4 instead\n", len);
613 static void update_divide_count(struct kvm_lapic *apic)
615 u32 tmp1, tmp2, tdcr;
617 tdcr = apic_get_reg(apic, APIC_TDCR);
619 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
620 apic->divide_count = 0x1 << (tmp2 & 0x7);
622 apic_debug("timer divide count is 0x%x\n",
623 apic->lapic_timer.divide_count);
626 static void start_apic_timer(struct kvm_lapic *apic)
628 ktime_t now = apic->lapic_timer.timer.base->get_time();
630 apic->lapic_timer.period = apic_get_reg(apic, APIC_TMICT) *
631 APIC_BUS_CYCLE_NS * apic->divide_count;
632 atomic_set(&apic->lapic_timer.pending, 0);
634 if (!apic->lapic_timer.period)
637 hrtimer_start(&apic->lapic_timer.timer,
638 ktime_add_ns(now, apic->lapic_timer.period),
641 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
643 "timer initial count 0x%x, period %lldns, "
644 "expire @ 0x%016" PRIx64 ".\n", __func__,
645 APIC_BUS_CYCLE_NS, ktime_to_ns(now),
646 apic_get_reg(apic, APIC_TMICT),
647 apic->lapic_timer.period,
648 ktime_to_ns(ktime_add_ns(now,
649 apic->lapic_timer.period)));
652 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
654 int nmi_wd_enabled = apic_lvt_nmi_mode(apic_get_reg(apic, APIC_LVT0));
656 if (apic_lvt_nmi_mode(lvt0_val)) {
657 if (!nmi_wd_enabled) {
658 apic_debug("Receive NMI setting on APIC_LVT0 "
659 "for cpu %d\n", apic->vcpu->vcpu_id);
660 apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
662 } else if (nmi_wd_enabled)
663 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
666 static void apic_mmio_write(struct kvm_io_device *this,
667 gpa_t address, int len, const void *data)
669 struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
670 unsigned int offset = address - apic->base_address;
671 unsigned char alignment = offset & 0xf;
675 * APIC register must be aligned on 128-bits boundary.
676 * 32/64/128 bits registers must be accessed thru 32 bits.
679 if (len != 4 || alignment) {
680 /* Don't shout loud, $infamous_os would cause only noise. */
681 apic_debug("apic write: bad size=%d %lx\n",
688 /* too common printing */
689 if (offset != APIC_EOI)
690 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
691 "0x%x\n", __func__, offset, len, val);
695 KVMTRACE_1D(APIC_ACCESS, apic->vcpu, (u32)offset, handler);
698 case APIC_ID: /* Local APIC ID */
699 apic_set_reg(apic, APIC_ID, val);
703 report_tpr_access(apic, true);
704 apic_set_tpr(apic, val & 0xff);
712 apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK);
716 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
720 apic_set_reg(apic, APIC_SPIV, val & 0x3ff);
721 if (!(val & APIC_SPIV_APIC_ENABLED)) {
725 for (i = 0; i < APIC_LVT_NUM; i++) {
726 lvt_val = apic_get_reg(apic,
727 APIC_LVTT + 0x10 * i);
728 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
729 lvt_val | APIC_LVT_MASKED);
731 atomic_set(&apic->lapic_timer.pending, 0);
737 /* No delay here, so we always clear the pending bit */
738 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
743 apic_set_reg(apic, APIC_ICR2, val & 0xff000000);
747 apic_manage_nmi_watchdog(apic, val);
753 /* TODO: Check vector */
754 if (!apic_sw_enabled(apic))
755 val |= APIC_LVT_MASKED;
757 val &= apic_lvt_mask[(offset - APIC_LVTT) >> 4];
758 apic_set_reg(apic, offset, val);
763 hrtimer_cancel(&apic->lapic_timer.timer);
764 apic_set_reg(apic, APIC_TMICT, val);
765 start_apic_timer(apic);
770 printk(KERN_ERR "KVM_WRITE:TDCR %x\n", val);
771 apic_set_reg(apic, APIC_TDCR, val);
772 update_divide_count(apic);
776 apic_debug("Local APIC Write to read-only register %x\n",
783 static int apic_mmio_range(struct kvm_io_device *this, gpa_t addr,
786 struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
790 if (apic_hw_enabled(apic) &&
791 (addr >= apic->base_address) &&
792 (addr < (apic->base_address + LAPIC_MMIO_LENGTH)))
798 void kvm_free_lapic(struct kvm_vcpu *vcpu)
800 if (!vcpu->arch.apic)
803 hrtimer_cancel(&vcpu->arch.apic->lapic_timer.timer);
805 if (vcpu->arch.apic->regs_page)
806 __free_page(vcpu->arch.apic->regs_page);
808 kfree(vcpu->arch.apic);
812 *----------------------------------------------------------------------
814 *----------------------------------------------------------------------
817 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
819 struct kvm_lapic *apic = vcpu->arch.apic;
823 apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
824 | (apic_get_reg(apic, APIC_TASKPRI) & 4));
826 EXPORT_SYMBOL_GPL(kvm_lapic_set_tpr);
828 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
830 struct kvm_lapic *apic = vcpu->arch.apic;
835 tpr = (u64) apic_get_reg(apic, APIC_TASKPRI);
837 return (tpr & 0xf0) >> 4;
839 EXPORT_SYMBOL_GPL(kvm_lapic_get_cr8);
841 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
843 struct kvm_lapic *apic = vcpu->arch.apic;
846 value |= MSR_IA32_APICBASE_BSP;
847 vcpu->arch.apic_base = value;
850 if (apic->vcpu->vcpu_id)
851 value &= ~MSR_IA32_APICBASE_BSP;
853 vcpu->arch.apic_base = value;
854 apic->base_address = apic->vcpu->arch.apic_base &
855 MSR_IA32_APICBASE_BASE;
857 /* with FSB delivery interrupt, we can restart APIC functionality */
858 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
859 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
863 u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu)
865 return vcpu->arch.apic_base;
867 EXPORT_SYMBOL_GPL(kvm_lapic_get_base);
869 void kvm_lapic_reset(struct kvm_vcpu *vcpu)
871 struct kvm_lapic *apic;
874 apic_debug("%s\n", __func__);
877 apic = vcpu->arch.apic;
878 ASSERT(apic != NULL);
880 /* Stop the timer in case it's a reset to an active apic */
881 hrtimer_cancel(&apic->lapic_timer.timer);
883 apic_set_reg(apic, APIC_ID, vcpu->vcpu_id << 24);
884 apic_set_reg(apic, APIC_LVR, APIC_VERSION);
886 for (i = 0; i < APIC_LVT_NUM; i++)
887 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
888 apic_set_reg(apic, APIC_LVT0,
889 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
891 apic_set_reg(apic, APIC_DFR, 0xffffffffU);
892 apic_set_reg(apic, APIC_SPIV, 0xff);
893 apic_set_reg(apic, APIC_TASKPRI, 0);
894 apic_set_reg(apic, APIC_LDR, 0);
895 apic_set_reg(apic, APIC_ESR, 0);
896 apic_set_reg(apic, APIC_ICR, 0);
897 apic_set_reg(apic, APIC_ICR2, 0);
898 apic_set_reg(apic, APIC_TDCR, 0);
899 apic_set_reg(apic, APIC_TMICT, 0);
900 for (i = 0; i < 8; i++) {
901 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
902 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
903 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
905 update_divide_count(apic);
906 atomic_set(&apic->lapic_timer.pending, 0);
907 if (vcpu->vcpu_id == 0)
908 vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP;
909 apic_update_ppr(apic);
911 apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr="
912 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
913 vcpu, kvm_apic_id(apic),
914 vcpu->arch.apic_base, apic->base_address);
916 EXPORT_SYMBOL_GPL(kvm_lapic_reset);
918 bool kvm_apic_present(struct kvm_vcpu *vcpu)
920 return vcpu->arch.apic && apic_hw_enabled(vcpu->arch.apic);
923 int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
925 return kvm_apic_present(vcpu) && apic_sw_enabled(vcpu->arch.apic);
927 EXPORT_SYMBOL_GPL(kvm_lapic_enabled);
930 *----------------------------------------------------------------------
932 *----------------------------------------------------------------------
935 static bool lapic_is_periodic(struct kvm_timer *ktimer)
937 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic,
939 return apic_lvtt_period(apic);
942 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
944 struct kvm_lapic *lapic = vcpu->arch.apic;
946 if (lapic && apic_enabled(lapic) && apic_lvt_enabled(lapic, APIC_LVTT))
947 return atomic_read(&lapic->lapic_timer.pending);
952 static int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
954 u32 reg = apic_get_reg(apic, lvt_type);
955 int vector, mode, trig_mode;
957 if (apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
958 vector = reg & APIC_VECTOR_MASK;
959 mode = reg & APIC_MODE_MASK;
960 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
961 return __apic_accept_irq(apic, mode, vector, 1, trig_mode);
966 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
968 struct kvm_lapic *apic = vcpu->arch.apic;
971 kvm_apic_local_deliver(apic, APIC_LVT0);
974 struct kvm_timer_ops lapic_timer_ops = {
975 .is_periodic = lapic_is_periodic,
978 int kvm_create_lapic(struct kvm_vcpu *vcpu)
980 struct kvm_lapic *apic;
982 ASSERT(vcpu != NULL);
983 apic_debug("apic_init %d\n", vcpu->vcpu_id);
985 apic = kzalloc(sizeof(*apic), GFP_KERNEL);
989 vcpu->arch.apic = apic;
991 apic->regs_page = alloc_page(GFP_KERNEL);
992 if (apic->regs_page == NULL) {
993 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
995 goto nomem_free_apic;
997 apic->regs = page_address(apic->regs_page);
998 memset(apic->regs, 0, PAGE_SIZE);
1001 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1003 apic->lapic_timer.timer.function = kvm_timer_fn;
1004 apic->lapic_timer.t_ops = &lapic_timer_ops;
1005 apic->lapic_timer.kvm = vcpu->kvm;
1006 apic->lapic_timer.vcpu_id = vcpu->vcpu_id;
1008 apic->base_address = APIC_DEFAULT_PHYS_BASE;
1009 vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE;
1011 kvm_lapic_reset(vcpu);
1012 apic->dev.read = apic_mmio_read;
1013 apic->dev.write = apic_mmio_write;
1014 apic->dev.in_range = apic_mmio_range;
1015 apic->dev.private = apic;
1023 EXPORT_SYMBOL_GPL(kvm_create_lapic);
1025 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1027 struct kvm_lapic *apic = vcpu->arch.apic;
1030 if (!apic || !apic_enabled(apic))
1033 apic_update_ppr(apic);
1034 highest_irr = apic_find_highest_irr(apic);
1035 if ((highest_irr == -1) ||
1036 ((highest_irr & 0xF0) <= apic_get_reg(apic, APIC_PROCPRI)))
1041 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1043 u32 lvt0 = apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1046 if (vcpu->vcpu_id == 0) {
1047 if (!apic_hw_enabled(vcpu->arch.apic))
1049 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1050 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1056 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1058 struct kvm_lapic *apic = vcpu->arch.apic;
1060 if (apic && atomic_read(&apic->lapic_timer.pending) > 0) {
1061 if (kvm_apic_local_deliver(apic, APIC_LVTT))
1062 atomic_dec(&apic->lapic_timer.pending);
1066 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1068 int vector = kvm_apic_has_interrupt(vcpu);
1069 struct kvm_lapic *apic = vcpu->arch.apic;
1074 apic_set_vector(vector, apic->regs + APIC_ISR);
1075 apic_update_ppr(apic);
1076 apic_clear_irr(vector, apic);
1080 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu)
1082 struct kvm_lapic *apic = vcpu->arch.apic;
1084 apic->base_address = vcpu->arch.apic_base &
1085 MSR_IA32_APICBASE_BASE;
1086 apic_set_reg(apic, APIC_LVR, APIC_VERSION);
1087 apic_update_ppr(apic);
1088 hrtimer_cancel(&apic->lapic_timer.timer);
1089 update_divide_count(apic);
1090 start_apic_timer(apic);
1093 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1095 struct kvm_lapic *apic = vcpu->arch.apic;
1096 struct hrtimer *timer;
1101 timer = &apic->lapic_timer.timer;
1102 if (hrtimer_cancel(timer))
1103 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
1106 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1111 if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1114 vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1115 data = *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr));
1116 kunmap_atomic(vapic, KM_USER0);
1118 apic_set_tpr(vcpu->arch.apic, data & 0xff);
1121 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1124 int max_irr, max_isr;
1125 struct kvm_lapic *apic;
1128 if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1131 apic = vcpu->arch.apic;
1132 tpr = apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1133 max_irr = apic_find_highest_irr(apic);
1136 max_isr = apic_find_highest_isr(apic);
1139 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1141 vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1142 *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)) = data;
1143 kunmap_atomic(vapic, KM_USER0);
1146 void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1148 if (!irqchip_in_kernel(vcpu->kvm))
1151 vcpu->arch.apic->vapic_addr = vapic_addr;