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   1
   2 /*
   3  * Local APIC virtualization
   4  *
   5  * Copyright (C) 2006 Qumranet, Inc.
   6  * Copyright (C) 2007 Novell
   7  * Copyright (C) 2007 Intel
   8  *
   9  * Authors:
  10  *   Dor Laor <dor.laor@qumranet.com>
  11  *   Gregory Haskins <ghaskins@novell.com>
  12  *   Yaozu (Eddie) Dong <eddie.dong@intel.com>
  13  *
  14  * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
  15  *
  16  * This work is licensed under the terms of the GNU GPL, version 2.  See
  17  * the COPYING file in the top-level directory.
  18  */
  19
  20 #include <linux/kvm_host.h>
  21 #include <linux/kvm.h>
  22 #include <linux/mm.h>
  23 #include <linux/highmem.h>
  24 #include <linux/smp.h>
  25 #include <linux/hrtimer.h>
  26 #include <linux/io.h>
  27 #include <linux/module.h>
  28 #include <linux/math64.h>
  29 #include <asm/processor.h>
  30 #include <asm/msr.h>
  31 #include <asm/page.h>
  32 #include <asm/current.h>
  33 #include <asm/apicdef.h>
  34 #include <asm/atomic.h>
  35 #include "kvm_cache_regs.h"
  36 #include "irq.h"
  37
  38 #ifndef CONFIG_X86_64
  39 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
  40 #else
  41 #define mod_64(x, y) ((x) % (y))
  42 #endif
  43
  44 #define PRId64 "d"
  45 #define PRIx64 "llx"
  46 #define PRIu64 "u"
  47 #define PRIo64 "o"
  48
  49 #define APIC_BUS_CYCLE_NS 1
  50
  51 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
  52 #define apic_debug(fmt, arg...)
  53
  54 #define APIC_LVT_NUM                    6
  55 /* 14 is the version for Xeon and Pentium 8.4.8*/
  56 #define APIC_VERSION                    (0x14UL | ((APIC_LVT_NUM - 1) << 16))
  57 #define LAPIC_MMIO_LENGTH               (1 << 12)
  58 /* followed define is not in apicdef.h */
  59 #define APIC_SHORT_MASK                 0xc0000
  60 #define APIC_DEST_NOSHORT               0x0
  61 #define APIC_DEST_MASK                  0x800
  62 #define MAX_APIC_VECTOR                 256
  63
  64 #define VEC_POS(v) ((v) & (32 - 1))
  65 #define REG_POS(v) (((v) >> 5) << 4)
  66
  67 static inline u32 apic_get_reg(struct kvm_lapic *apic, int reg_off)
  68 {
  69         return *((u32 *) (apic->regs + reg_off));
  70 }
  71
  72 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
  73 {
  74         *((u32 *) (apic->regs + reg_off)) = val;
  75 }
  76
  77 static inline int apic_test_and_set_vector(int vec, void *bitmap)
  78 {
  79         return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  80 }
  81
  82 static inline int apic_test_and_clear_vector(int vec, void *bitmap)
  83 {
  84         return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  85 }
  86
  87 static inline void apic_set_vector(int vec, void *bitmap)
  88 {
  89         set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  90 }
  91
  92 static inline void apic_clear_vector(int vec, void *bitmap)
  93 {
  94         clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  95 }
  96
  97 static inline int apic_hw_enabled(struct kvm_lapic *apic)
  98 {
  99         return (apic)->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
 100 }
 101
 102 static inline int  apic_sw_enabled(struct kvm_lapic *apic)
 103 {
 104         return apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED;
 105 }
 106
 107 static inline int apic_enabled(struct kvm_lapic *apic)
 108 {
 109         return apic_sw_enabled(apic) && apic_hw_enabled(apic);
 110 }
 111
 112 #define LVT_MASK        \
 113         (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
 114
 115 #define LINT_MASK       \
 116         (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
 117          APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
 118
 119 static inline int kvm_apic_id(struct kvm_lapic *apic)
 120 {
 121         return (apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
 122 }
 123
 124 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
 125 {
 126         return !(apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
 127 }
 128
 129 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
 130 {
 131         return apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
 132 }
 133
 134 static inline int apic_lvtt_period(struct kvm_lapic *apic)
 135 {
 136         return apic_get_reg(apic, APIC_LVTT) & APIC_LVT_TIMER_PERIODIC;
 137 }
 138
 139 static inline int apic_lvt_nmi_mode(u32 lvt_val)
 140 {
 141         return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
 142 }
 143
 144 static unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
 145         LVT_MASK | APIC_LVT_TIMER_PERIODIC,     /* LVTT */
 146         LVT_MASK | APIC_MODE_MASK,      /* LVTTHMR */
 147         LVT_MASK | APIC_MODE_MASK,      /* LVTPC */
 148         LINT_MASK, LINT_MASK,   /* LVT0-1 */
 149         LVT_MASK                /* LVTERR */
 150 };
 151
 152 static int find_highest_vector(void *bitmap)
 153 {
 154         u32 *word = bitmap;
 155         int word_offset = MAX_APIC_VECTOR >> 5;
 156
 157         while ((word_offset != 0) && (word[(--word_offset) << 2] == 0))
 158                 continue;
 159
 160         if (likely(!word_offset && !word[0]))
 161                 return -1;
 162         else
 163                 return fls(word[word_offset << 2]) - 1 + (word_offset << 5);
 164 }
 165
 166 static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic)
 167 {
 168         apic->irr_pending = true;
 169         return apic_test_and_set_vector(vec, apic->regs + APIC_IRR);
 170 }
 171
 172 static inline int apic_search_irr(struct kvm_lapic *apic)
 173 {
 174         return find_highest_vector(apic->regs + APIC_IRR);
 175 }
 176
 177 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
 178 {
 179         int result;
 180
 181         if (!apic->irr_pending)
 182                 return -1;
 183
 184         result = apic_search_irr(apic);
 185         ASSERT(result == -1 || result >= 16);
 186
 187         return result;
 188 }
 189
 190 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
 191 {
 192         apic->irr_pending = false;
 193         apic_clear_vector(vec, apic->regs + APIC_IRR);
 194         if (apic_search_irr(apic) != -1)
 195                 apic->irr_pending = true;
 196 }
 197
 198 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
 199 {
 200         struct kvm_lapic *apic = vcpu->arch.apic;
 201         int highest_irr;
 202
 203         /* This may race with setting of irr in __apic_accept_irq() and
 204          * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
 205          * will cause vmexit immediately and the value will be recalculated
 206          * on the next vmentry.
 207          */
 208         if (!apic)
 209                 return 0;
 210         highest_irr = apic_find_highest_irr(apic);
 211
 212         return highest_irr;
 213 }
 214
 215 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 216                              int vector, int level, int trig_mode);
 217
 218 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq)
 219 {
 220         struct kvm_lapic *apic = vcpu->arch.apic;
 221
 222         return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
 223                         irq->level, irq->trig_mode);
 224 }
 225
 226 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
 227 {
 228         int result;
 229
 230         result = find_highest_vector(apic->regs + APIC_ISR);
 231         ASSERT(result == -1 || result >= 16);
 232
 233         return result;
 234 }
 235
 236 static void apic_update_ppr(struct kvm_lapic *apic)
 237 {
 238         u32 tpr, isrv, ppr;
 239         int isr;
 240
 241         tpr = apic_get_reg(apic, APIC_TASKPRI);
 242         isr = apic_find_highest_isr(apic);
 243         isrv = (isr != -1) ? isr : 0;
 244
 245         if ((tpr & 0xf0) >= (isrv & 0xf0))
 246                 ppr = tpr & 0xff;
 247         else
 248                 ppr = isrv & 0xf0;
 249
 250         apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
 251                    apic, ppr, isr, isrv);
 252
 253         apic_set_reg(apic, APIC_PROCPRI, ppr);
 254 }
 255
 256 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
 257 {
 258         apic_set_reg(apic, APIC_TASKPRI, tpr);
 259         apic_update_ppr(apic);
 260 }
 261
 262 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest)
 263 {
 264         return dest == 0xff || kvm_apic_id(apic) == dest;
 265 }
 266
 267 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
 268 {
 269         int result = 0;
 270         u8 logical_id;
 271
 272         logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR));
 273
 274         switch (apic_get_reg(apic, APIC_DFR)) {
 275         case APIC_DFR_FLAT:
 276                 if (logical_id & mda)
 277                         result = 1;
 278                 break;
 279         case APIC_DFR_CLUSTER:
 280                 if (((logical_id >> 4) == (mda >> 0x4))
 281                     && (logical_id & mda & 0xf))
 282                         result = 1;
 283                 break;
 284         default:
 285                 printk(KERN_WARNING "Bad DFR vcpu %d: %08x\n",
 286                        apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR));
 287                 break;
 288         }
 289
 290         return result;
 291 }
 292
 293 int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
 294                            int short_hand, int dest, int dest_mode)
 295 {
 296         int result = 0;
 297         struct kvm_lapic *target = vcpu->arch.apic;
 298
 299         apic_debug("target %p, source %p, dest 0x%x, "
 300                    "dest_mode 0x%x, short_hand 0x%x\n",
 301                    target, source, dest, dest_mode, short_hand);
 302
 303         ASSERT(!target);
 304         switch (short_hand) {
 305         case APIC_DEST_NOSHORT:
 306                 if (dest_mode == 0)
 307                         /* Physical mode. */
 308                         result = kvm_apic_match_physical_addr(target, dest);
 309                 else
 310                         /* Logical mode. */
 311                         result = kvm_apic_match_logical_addr(target, dest);
 312                 break;
 313         case APIC_DEST_SELF:
 314                 result = (target == source);
 315                 break;
 316         case APIC_DEST_ALLINC:
 317                 result = 1;
 318                 break;
 319         case APIC_DEST_ALLBUT:
 320                 result = (target != source);
 321                 break;
 322         default:
 323                 printk(KERN_WARNING "Bad dest shorthand value %x\n",
 324                        short_hand);
 325                 break;
 326         }
 327
 328         return result;
 329 }
 330
 331 /*
 332  * Add a pending IRQ into lapic.
 333  * Return 1 if successfully added and 0 if discarded.
 334  */
 335 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 336                              int vector, int level, int trig_mode)
 337 {
 338         int result = 0;
 339         struct kvm_vcpu *vcpu = apic->vcpu;
 340
 341         switch (delivery_mode) {
 342         case APIC_DM_LOWEST:
 343                 vcpu->arch.apic_arb_prio++;
 344         case APIC_DM_FIXED:
 345                 /* FIXME add logic for vcpu on reset */
 346                 if (unlikely(!apic_enabled(apic)))
 347                         break;
 348
 349                 result = !apic_test_and_set_irr(vector, apic);
 350                 if (!result) {
 351                         if (trig_mode)
 352                                 apic_debug("level trig mode repeatedly for "
 353                                                 "vector %d", vector);
 354                         break;
 355                 }
 356
 357                 if (trig_mode) {
 358                         apic_debug("level trig mode for vector %d", vector);
 359                         apic_set_vector(vector, apic->regs + APIC_TMR);
 360                 } else
 361                         apic_clear_vector(vector, apic->regs + APIC_TMR);
 362                 kvm_vcpu_kick(vcpu);
 363                 break;
 364
 365         case APIC_DM_REMRD:
 366                 printk(KERN_DEBUG "Ignoring delivery mode 3\n");
 367                 break;
 368
 369         case APIC_DM_SMI:
 370                 printk(KERN_DEBUG "Ignoring guest SMI\n");
 371                 break;
 372
 373         case APIC_DM_NMI:
 374                 result = 1;
 375                 kvm_inject_nmi(vcpu);
 376                 kvm_vcpu_kick(vcpu);
 377                 break;
 378
 379         case APIC_DM_INIT:
 380                 if (level) {
 381                         result = 1;
 382                         if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
 383                                 printk(KERN_DEBUG
 384                                        "INIT on a runnable vcpu %d\n",
 385                                        vcpu->vcpu_id);
 386                         vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
 387                         kvm_vcpu_kick(vcpu);
 388                 } else {
 389                         apic_debug("Ignoring de-assert INIT to vcpu %d\n",
 390                                    vcpu->vcpu_id);
 391                 }
 392                 break;
 393
 394         case APIC_DM_STARTUP:
 395                 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
 396                            vcpu->vcpu_id, vector);
 397                 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
 398                         result = 1;
 399                         vcpu->arch.sipi_vector = vector;
 400                         vcpu->arch.mp_state = KVM_MP_STATE_SIPI_RECEIVED;
 401                         kvm_vcpu_kick(vcpu);
 402                 }
 403                 break;
 404
 405         case APIC_DM_EXTINT:
 406                 /*
 407                  * Should only be called by kvm_apic_local_deliver() with LVT0,
 408                  * before NMI watchdog was enabled. Already handled by
 409                  * kvm_apic_accept_pic_intr().
 410                  */
 411                 break;
 412
 413         default:
 414                 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
 415                        delivery_mode);
 416                 break;
 417         }
 418         return result;
 419 }
 420
 421 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
 422 {
 423         return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
 424 }
 425
 426 static void apic_set_eoi(struct kvm_lapic *apic)
 427 {
 428         int vector = apic_find_highest_isr(apic);
 429         int trigger_mode;
 430         /*
 431          * Not every write EOI will has corresponding ISR,
 432          * one example is when Kernel check timer on setup_IO_APIC
 433          */
 434         if (vector == -1)
 435                 return;
 436
 437         apic_clear_vector(vector, apic->regs + APIC_ISR);
 438         apic_update_ppr(apic);
 439
 440         if (apic_test_and_clear_vector(vector, apic->regs + APIC_TMR))
 441                 trigger_mode = IOAPIC_LEVEL_TRIG;
 442         else
 443                 trigger_mode = IOAPIC_EDGE_TRIG;
 444         mutex_lock(&apic->vcpu->kvm->irq_lock);
 445         kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode);
 446         mutex_unlock(&apic->vcpu->kvm->irq_lock);
 447 }
 448
 449 static void apic_send_ipi(struct kvm_lapic *apic)
 450 {
 451         u32 icr_low = apic_get_reg(apic, APIC_ICR);
 452         u32 icr_high = apic_get_reg(apic, APIC_ICR2);
 453         struct kvm_lapic_irq irq;
 454
 455         irq.vector = icr_low & APIC_VECTOR_MASK;
 456         irq.delivery_mode = icr_low & APIC_MODE_MASK;
 457         irq.dest_mode = icr_low & APIC_DEST_MASK;
 458         irq.level = icr_low & APIC_INT_ASSERT;
 459         irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
 460         irq.shorthand = icr_low & APIC_SHORT_MASK;
 461         irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
 462
 463         apic_debug("icr_high 0x%x, icr_low 0x%x, "
 464                    "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
 465                    "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
 466                    icr_high, icr_low, irq.shorthand, irq.dest_id,
 467                    irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
 468                    irq.vector);
 469
 470         mutex_lock(&apic->vcpu->kvm->irq_lock);
 471         kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq);
 472         mutex_unlock(&apic->vcpu->kvm->irq_lock);
 473 }
 474
 475 static u32 apic_get_tmcct(struct kvm_lapic *apic)
 476 {
 477         ktime_t remaining;
 478         s64 ns;
 479         u32 tmcct;
 480
 481         ASSERT(apic != NULL);
 482
 483         /* if initial count is 0, current count should also be 0 */
 484         if (apic_get_reg(apic, APIC_TMICT) == 0)
 485                 return 0;
 486
 487         remaining = hrtimer_expires_remaining(&apic->lapic_timer.timer);
 488         if (ktime_to_ns(remaining) < 0)
 489                 remaining = ktime_set(0, 0);
 490
 491         ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
 492         tmcct = div64_u64(ns,
 493                          (APIC_BUS_CYCLE_NS * apic->divide_count));
 494
 495         return tmcct;
 496 }
 497
 498 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
 499 {
 500         struct kvm_vcpu *vcpu = apic->vcpu;
 501         struct kvm_run *run = vcpu->run;
 502
 503         set_bit(KVM_REQ_REPORT_TPR_ACCESS, &vcpu->requests);
 504         run->tpr_access.rip = kvm_rip_read(vcpu);
 505         run->tpr_access.is_write = write;
 506 }
 507
 508 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
 509 {
 510         if (apic->vcpu->arch.tpr_access_reporting)
 511                 __report_tpr_access(apic, write);
 512 }
 513
 514 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
 515 {
 516         u32 val = 0;
 517
 518         KVMTRACE_1D(APIC_ACCESS, apic->vcpu, (u32)offset, handler);
 519
 520         if (offset >= LAPIC_MMIO_LENGTH)
 521                 return 0;
 522
 523         switch (offset) {
 524         case APIC_ARBPRI:
 525                 printk(KERN_WARNING "Access APIC ARBPRI register "
 526                        "which is for P6\n");
 527                 break;
 528
 529         case APIC_TMCCT:        /* Timer CCR */
 530                 val = apic_get_tmcct(apic);
 531                 break;
 532
 533         case APIC_TASKPRI:
 534                 report_tpr_access(apic, false);
 535                 /* fall thru */
 536         default:
 537                 apic_update_ppr(apic);
 538                 val = apic_get_reg(apic, offset);
 539                 break;
 540         }
 541
 542         return val;
 543 }
 544
 545 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
 546 {
 547         return container_of(dev, struct kvm_lapic, dev);
 548 }
 549
 550 static void apic_mmio_read(struct kvm_io_device *this,
 551                            gpa_t address, int len, void *data)
 552 {
 553         struct kvm_lapic *apic = to_lapic(this);
 554         unsigned int offset = address - apic->base_address;
 555         unsigned char alignment = offset & 0xf;
 556         u32 result;
 557
 558         if ((alignment + len) > 4) {
 559                 printk(KERN_ERR "KVM_APIC_READ: alignment error %lx %d",
 560                        (unsigned long)address, len);
 561                 return;
 562         }
 563         result = __apic_read(apic, offset & ~0xf);
 564
 565         switch (len) {
 566         case 1:
 567         case 2:
 568         case 4:
 569                 memcpy(data, (char *)&result + alignment, len);
 570                 break;
 571         default:
 572                 printk(KERN_ERR "Local APIC read with len = %x, "
 573                        "should be 1,2, or 4 instead\n", len);
 574                 break;
 575         }
 576 }
 577
 578 static void update_divide_count(struct kvm_lapic *apic)
 579 {
 580         u32 tmp1, tmp2, tdcr;
 581
 582         tdcr = apic_get_reg(apic, APIC_TDCR);
 583         tmp1 = tdcr & 0xf;
 584         tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
 585         apic->divide_count = 0x1 << (tmp2 & 0x7);
 586
 587         apic_debug("timer divide count is 0x%x\n",
 588                                    apic->divide_count);
 589 }
 590
 591 static void start_apic_timer(struct kvm_lapic *apic)
 592 {
 593         ktime_t now = apic->lapic_timer.timer.base->get_time();
 594
 595         apic->lapic_timer.period = apic_get_reg(apic, APIC_TMICT) *
 596                     APIC_BUS_CYCLE_NS * apic->divide_count;
 597         atomic_set(&apic->lapic_timer.pending, 0);
 598
 599         if (!apic->lapic_timer.period)
 600                 return;
 601
 602         hrtimer_start(&apic->lapic_timer.timer,
 603                       ktime_add_ns(now, apic->lapic_timer.period),
 604                       HRTIMER_MODE_ABS);
 605
 606         apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
 607                            PRIx64 ", "
 608                            "timer initial count 0x%x, period %lldns, "
 609                            "expire @ 0x%016" PRIx64 ".\n", __func__,
 610                            APIC_BUS_CYCLE_NS, ktime_to_ns(now),
 611                            apic_get_reg(apic, APIC_TMICT),
 612                            apic->lapic_timer.period,
 613                            ktime_to_ns(ktime_add_ns(now,
 614                                         apic->lapic_timer.period)));
 615 }
 616
 617 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
 618 {
 619         int nmi_wd_enabled = apic_lvt_nmi_mode(apic_get_reg(apic, APIC_LVT0));
 620
 621         if (apic_lvt_nmi_mode(lvt0_val)) {
 622                 if (!nmi_wd_enabled) {
 623                         apic_debug("Receive NMI setting on APIC_LVT0 "
 624                                    "for cpu %d\n", apic->vcpu->vcpu_id);
 625                         apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
 626                 }
 627         } else if (nmi_wd_enabled)
 628                 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
 629 }
 630
 631 static void apic_mmio_write(struct kvm_io_device *this,
 632                             gpa_t address, int len, const void *data)
 633 {
 634         struct kvm_lapic *apic = to_lapic(this);
 635         unsigned int offset = address - apic->base_address;
 636         unsigned char alignment = offset & 0xf;
 637         u32 val;
 638
 639         /*
 640          * APIC register must be aligned on 128-bits boundary.
 641          * 32/64/128 bits registers must be accessed thru 32 bits.
 642          * Refer SDM 8.4.1
 643          */
 644         if (len != 4 || alignment) {
 645                 /* Don't shout loud, $infamous_os would cause only noise. */
 646                 apic_debug("apic write: bad size=%d %lx\n",
 647                            len, (long)address);
 648                 return;
 649         }
 650
 651         val = *(u32 *) data;
 652
 653         /* too common printing */
 654         if (offset != APIC_EOI)
 655                 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
 656                            "0x%x\n", __func__, offset, len, val);
 657
 658         offset &= 0xff0;
 659
 660         KVMTRACE_1D(APIC_ACCESS, apic->vcpu, (u32)offset, handler);
 661
 662         switch (offset) {
 663         case APIC_ID:           /* Local APIC ID */
 664                 apic_set_reg(apic, APIC_ID, val);
 665                 break;
 666
 667         case APIC_TASKPRI:
 668                 report_tpr_access(apic, true);
 669                 apic_set_tpr(apic, val & 0xff);
 670                 break;
 671
 672         case APIC_EOI:
 673                 apic_set_eoi(apic);
 674                 break;
 675
 676         case APIC_LDR:
 677                 apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK);
 678                 break;
 679
 680         case APIC_DFR:
 681                 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
 682                 break;
 683
 684         case APIC_SPIV:
 685                 apic_set_reg(apic, APIC_SPIV, val & 0x3ff);
 686                 if (!(val & APIC_SPIV_APIC_ENABLED)) {
 687                         int i;
 688                         u32 lvt_val;
 689
 690                         for (i = 0; i < APIC_LVT_NUM; i++) {
 691                                 lvt_val = apic_get_reg(apic,
 692                                                        APIC_LVTT + 0x10 * i);
 693                                 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
 694                                              lvt_val | APIC_LVT_MASKED);
 695                         }
 696                         atomic_set(&apic->lapic_timer.pending, 0);
 697
 698                 }
 699                 break;
 700
 701         case APIC_ICR:
 702                 /* No delay here, so we always clear the pending bit */
 703                 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
 704                 apic_send_ipi(apic);
 705                 break;
 706
 707         case APIC_ICR2:
 708                 apic_set_reg(apic, APIC_ICR2, val & 0xff000000);
 709                 break;
 710
 711         case APIC_LVT0:
 712                 apic_manage_nmi_watchdog(apic, val);
 713         case APIC_LVTT:
 714         case APIC_LVTTHMR:
 715         case APIC_LVTPC:
 716         case APIC_LVT1:
 717         case APIC_LVTERR:
 718                 /* TODO: Check vector */
 719                 if (!apic_sw_enabled(apic))
 720                         val |= APIC_LVT_MASKED;
 721
 722                 val &= apic_lvt_mask[(offset - APIC_LVTT) >> 4];
 723                 apic_set_reg(apic, offset, val);
 724
 725                 break;
 726
 727         case APIC_TMICT:
 728                 hrtimer_cancel(&apic->lapic_timer.timer);
 729                 apic_set_reg(apic, APIC_TMICT, val);
 730                 start_apic_timer(apic);
 731                 return;
 732
 733         case APIC_TDCR:
 734                 if (val & 4)
 735                         printk(KERN_ERR "KVM_WRITE:TDCR %x\n", val);
 736                 apic_set_reg(apic, APIC_TDCR, val);
 737                 update_divide_count(apic);
 738                 break;
 739
 740         default:
 741                 apic_debug("Local APIC Write to read-only register %x\n",
 742                            offset);
 743                 break;
 744         }
 745
 746 }
 747
 748 static int apic_mmio_range(struct kvm_io_device *this, gpa_t addr,
 749                            int len, int size)
 750 {
 751         struct kvm_lapic *apic = to_lapic(this);
 752         int ret = 0;
 753
 754
 755         if (apic_hw_enabled(apic) &&
 756             (addr >= apic->base_address) &&
 757             (addr < (apic->base_address + LAPIC_MMIO_LENGTH)))
 758                 ret = 1;
 759
 760         return ret;
 761 }
 762
 763 void kvm_free_lapic(struct kvm_vcpu *vcpu)
 764 {
 765         if (!vcpu->arch.apic)
 766                 return;
 767
 768         hrtimer_cancel(&vcpu->arch.apic->lapic_timer.timer);
 769
 770         if (vcpu->arch.apic->regs_page)
 771                 __free_page(vcpu->arch.apic->regs_page);
 772
 773         kfree(vcpu->arch.apic);
 774 }
 775
 776 /*
 777  *----------------------------------------------------------------------
 778  * LAPIC interface
 779  *----------------------------------------------------------------------
 780  */
 781
 782 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
 783 {
 784         struct kvm_lapic *apic = vcpu->arch.apic;
 785
 786         if (!apic)
 787                 return;
 788         apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
 789                      | (apic_get_reg(apic, APIC_TASKPRI) & 4));
 790 }
 791
 792 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
 793 {
 794         struct kvm_lapic *apic = vcpu->arch.apic;
 795         u64 tpr;
 796
 797         if (!apic)
 798                 return 0;
 799         tpr = (u64) apic_get_reg(apic, APIC_TASKPRI);
 800
 801         return (tpr & 0xf0) >> 4;
 802 }
 803
 804 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
 805 {
 806         struct kvm_lapic *apic = vcpu->arch.apic;
 807
 808         if (!apic) {
 809                 value |= MSR_IA32_APICBASE_BSP;
 810                 vcpu->arch.apic_base = value;
 811                 return;
 812         }
 813
 814         if (!kvm_vcpu_is_bsp(apic->vcpu))
 815                 value &= ~MSR_IA32_APICBASE_BSP;
 816
 817         vcpu->arch.apic_base = value;
 818         apic->base_address = apic->vcpu->arch.apic_base &
 819                              MSR_IA32_APICBASE_BASE;
 820
 821         /* with FSB delivery interrupt, we can restart APIC functionality */
 822         apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
 823                    "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
 824
 825 }
 826
 827 void kvm_lapic_reset(struct kvm_vcpu *vcpu)
 828 {
 829         struct kvm_lapic *apic;
 830         int i;
 831
 832         apic_debug("%s\n", __func__);
 833
 834         ASSERT(vcpu);
 835         apic = vcpu->arch.apic;
 836         ASSERT(apic != NULL);
 837
 838         /* Stop the timer in case it's a reset to an active apic */
 839         hrtimer_cancel(&apic->lapic_timer.timer);
 840
 841         apic_set_reg(apic, APIC_ID, vcpu->vcpu_id << 24);
 842         apic_set_reg(apic, APIC_LVR, APIC_VERSION);
 843
 844         for (i = 0; i < APIC_LVT_NUM; i++)
 845                 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
 846         apic_set_reg(apic, APIC_LVT0,
 847                      SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
 848
 849         apic_set_reg(apic, APIC_DFR, 0xffffffffU);
 850         apic_set_reg(apic, APIC_SPIV, 0xff);
 851         apic_set_reg(apic, APIC_TASKPRI, 0);
 852         apic_set_reg(apic, APIC_LDR, 0);
 853         apic_set_reg(apic, APIC_ESR, 0);
 854         apic_set_reg(apic, APIC_ICR, 0);
 855         apic_set_reg(apic, APIC_ICR2, 0);
 856         apic_set_reg(apic, APIC_TDCR, 0);
 857         apic_set_reg(apic, APIC_TMICT, 0);
 858         for (i = 0; i < 8; i++) {
 859                 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
 860                 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
 861                 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
 862         }
 863         apic->irr_pending = false;
 864         update_divide_count(apic);
 865         atomic_set(&apic->lapic_timer.pending, 0);
 866         if (kvm_vcpu_is_bsp(vcpu))
 867                 vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP;
 868         apic_update_ppr(apic);
 869
 870         vcpu->arch.apic_arb_prio = 0;
 871
 872         apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr="
 873                    "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
 874                    vcpu, kvm_apic_id(apic),
 875                    vcpu->arch.apic_base, apic->base_address);
 876 }
 877
 878 bool kvm_apic_present(struct kvm_vcpu *vcpu)
 879 {
 880         return vcpu->arch.apic && apic_hw_enabled(vcpu->arch.apic);
 881 }
 882
 883 int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
 884 {
 885         return kvm_apic_present(vcpu) && apic_sw_enabled(vcpu->arch.apic);
 886 }
 887
 888 /*
 889  *----------------------------------------------------------------------
 890  * timer interface
 891  *----------------------------------------------------------------------
 892  */
 893
 894 static bool lapic_is_periodic(struct kvm_timer *ktimer)
 895 {
 896         struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic,
 897                                               lapic_timer);
 898         return apic_lvtt_period(apic);
 899 }
 900
 901 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
 902 {
 903         struct kvm_lapic *lapic = vcpu->arch.apic;
 904
 905         if (lapic && apic_enabled(lapic) && apic_lvt_enabled(lapic, APIC_LVTT))
 906                 return atomic_read(&lapic->lapic_timer.pending);
 907
 908         return 0;
 909 }
 910
 911 static int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
 912 {
 913         u32 reg = apic_get_reg(apic, lvt_type);
 914         int vector, mode, trig_mode;
 915
 916         if (apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
 917                 vector = reg & APIC_VECTOR_MASK;
 918                 mode = reg & APIC_MODE_MASK;
 919                 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
 920                 return __apic_accept_irq(apic, mode, vector, 1, trig_mode);
 921         }
 922         return 0;
 923 }
 924
 925 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
 926 {
 927         struct kvm_lapic *apic = vcpu->arch.apic;
 928
 929         if (apic)
 930                 kvm_apic_local_deliver(apic, APIC_LVT0);
 931 }
 932
 933 static struct kvm_timer_ops lapic_timer_ops = {
 934         .is_periodic = lapic_is_periodic,
 935 };
 936
 937 static const struct kvm_io_device_ops apic_mmio_ops = {
 938         .read     = apic_mmio_read,
 939         .write    = apic_mmio_write,
 940         .in_range = apic_mmio_range,
 941 };
 942
 943 int kvm_create_lapic(struct kvm_vcpu *vcpu)
 944 {
 945         struct kvm_lapic *apic;
 946
 947         ASSERT(vcpu != NULL);
 948         apic_debug("apic_init %d\n", vcpu->vcpu_id);
 949
 950         apic = kzalloc(sizeof(*apic), GFP_KERNEL);
 951         if (!apic)
 952                 goto nomem;
 953
 954         vcpu->arch.apic = apic;
 955
 956         apic->regs_page = alloc_page(GFP_KERNEL);
 957         if (apic->regs_page == NULL) {
 958                 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
 959                        vcpu->vcpu_id);
 960                 goto nomem_free_apic;
 961         }
 962         apic->regs = page_address(apic->regs_page);
 963         memset(apic->regs, 0, PAGE_SIZE);
 964         apic->vcpu = vcpu;
 965
 966         hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
 967                      HRTIMER_MODE_ABS);
 968         apic->lapic_timer.timer.function = kvm_timer_fn;
 969         apic->lapic_timer.t_ops = &lapic_timer_ops;
 970         apic->lapic_timer.kvm = vcpu->kvm;
 971         apic->lapic_timer.vcpu = vcpu;
 972
 973         apic->base_address = APIC_DEFAULT_PHYS_BASE;
 974         vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE;
 975
 976         kvm_lapic_reset(vcpu);
 977         kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
 978
 979         return 0;
 980 nomem_free_apic:
 981         kfree(apic);
 982 nomem:
 983         return -ENOMEM;
 984 }
 985
 986 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
 987 {
 988         struct kvm_lapic *apic = vcpu->arch.apic;
 989         int highest_irr;
 990
 991         if (!apic || !apic_enabled(apic))
 992                 return -1;
 993
 994         apic_update_ppr(apic);
 995         highest_irr = apic_find_highest_irr(apic);
 996         if ((highest_irr == -1) ||
 997             ((highest_irr & 0xF0) <= apic_get_reg(apic, APIC_PROCPRI)))
 998                 return -1;
 999         return highest_irr;
1000 }
1001
1002 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1003 {
1004         u32 lvt0 = apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1005         int r = 0;
1006
1007         if (kvm_vcpu_is_bsp(vcpu)) {
1008                 if (!apic_hw_enabled(vcpu->arch.apic))
1009                         r = 1;
1010                 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1011                     GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1012                         r = 1;
1013         }
1014         return r;
1015 }
1016
1017 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1018 {
1019         struct kvm_lapic *apic = vcpu->arch.apic;
1020
1021         if (apic && atomic_read(&apic->lapic_timer.pending) > 0) {
1022                 if (kvm_apic_local_deliver(apic, APIC_LVTT))
1023                         atomic_dec(&apic->lapic_timer.pending);
1024         }
1025 }
1026
1027 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1028 {
1029         int vector = kvm_apic_has_interrupt(vcpu);
1030         struct kvm_lapic *apic = vcpu->arch.apic;
1031
1032         if (vector == -1)
1033                 return -1;
1034
1035         apic_set_vector(vector, apic->regs + APIC_ISR);
1036         apic_update_ppr(apic);
1037         apic_clear_irr(vector, apic);
1038         return vector;
1039 }
1040
1041 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu)
1042 {
1043         struct kvm_lapic *apic = vcpu->arch.apic;
1044
1045         apic->base_address = vcpu->arch.apic_base &
1046                              MSR_IA32_APICBASE_BASE;
1047         apic_set_reg(apic, APIC_LVR, APIC_VERSION);
1048         apic_update_ppr(apic);
1049         hrtimer_cancel(&apic->lapic_timer.timer);
1050         update_divide_count(apic);
1051         start_apic_timer(apic);
1052 }
1053
1054 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1055 {
1056         struct kvm_lapic *apic = vcpu->arch.apic;
1057         struct hrtimer *timer;
1058
1059         if (!apic)
1060                 return;
1061
1062         timer = &apic->lapic_timer.timer;
1063         if (hrtimer_cancel(timer))
1064                 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
1065 }
1066
1067 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1068 {
1069         u32 data;
1070         void *vapic;
1071
1072         if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1073                 return;
1074
1075         vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1076         data = *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr));
1077         kunmap_atomic(vapic, KM_USER0);
1078
1079         apic_set_tpr(vcpu->arch.apic, data & 0xff);
1080 }
1081
1082 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1083 {
1084         u32 data, tpr;
1085         int max_irr, max_isr;
1086         struct kvm_lapic *apic;
1087         void *vapic;
1088
1089         if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1090                 return;
1091
1092         apic = vcpu->arch.apic;
1093         tpr = apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1094         max_irr = apic_find_highest_irr(apic);
1095         if (max_irr < 0)
1096                 max_irr = 0;
1097         max_isr = apic_find_highest_isr(apic);
1098         if (max_isr < 0)
1099                 max_isr = 0;
1100         data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1101
1102         vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1103         *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)) = data;
1104         kunmap_atomic(vapic, KM_USER0);
1105 }
1106
1107 void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1108 {
1109         if (!irqchip_in_kernel(vcpu->kvm))
1110                 return;
1111
1112         vcpu->arch.apic->vapic_addr = vapic_addr;
1113 }