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   1
   2 /*
   3  * Local APIC virtualization
   4  *
   5  * Copyright (C) 2006 Qumranet, Inc.
   6  * Copyright (C) 2007 Novell
   7  * Copyright (C) 2007 Intel
   8  *
   9  * Authors:
  10  *   Dor Laor <dor.laor@qumranet.com>
  11  *   Gregory Haskins <ghaskins@novell.com>
  12  *   Yaozu (Eddie) Dong <eddie.dong@intel.com>
  13  *
  14  * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
  15  *
  16  * This work is licensed under the terms of the GNU GPL, version 2.  See
  17  * the COPYING file in the top-level directory.
  18  */
  19
  20 #include <linux/kvm_host.h>
  21 #include <linux/kvm.h>
  22 #include <linux/mm.h>
  23 #include <linux/highmem.h>
  24 #include <linux/smp.h>
  25 #include <linux/hrtimer.h>
  26 #include <linux/io.h>
  27 #include <linux/module.h>
  28 #include <linux/math64.h>
  29 #include <asm/processor.h>
  30 #include <asm/msr.h>
  31 #include <asm/page.h>
  32 #include <asm/current.h>
  33 #include <asm/apicdef.h>
  34 #include <asm/atomic.h>
  35 #include "kvm_cache_regs.h"
  36 #include "irq.h"
  37
  38 #define PRId64 "d"
  39 #define PRIx64 "llx"
  40 #define PRIu64 "u"
  41 #define PRIo64 "o"
  42
  43 #define APIC_BUS_CYCLE_NS 1
  44
  45 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
  46 #define apic_debug(fmt, arg...)
  47
  48 #define APIC_LVT_NUM                    6
  49 /* 14 is the version for Xeon and Pentium 8.4.8*/
  50 #define APIC_VERSION                    (0x14UL | ((APIC_LVT_NUM - 1) << 16))
  51 #define LAPIC_MMIO_LENGTH               (1 << 12)
  52 /* followed define is not in apicdef.h */
  53 #define APIC_SHORT_MASK                 0xc0000
  54 #define APIC_DEST_NOSHORT               0x0
  55 #define APIC_DEST_MASK                  0x800
  56 #define MAX_APIC_VECTOR                 256
  57
  58 #define VEC_POS(v) ((v) & (32 - 1))
  59 #define REG_POS(v) (((v) >> 5) << 4)
  60
  61 static inline u32 apic_get_reg(struct kvm_lapic *apic, int reg_off)
  62 {
  63         return *((u32 *) (apic->regs + reg_off));
  64 }
  65
  66 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
  67 {
  68         *((u32 *) (apic->regs + reg_off)) = val;
  69 }
  70
  71 static inline int apic_test_and_set_vector(int vec, void *bitmap)
  72 {
  73         return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  74 }
  75
  76 static inline int apic_test_and_clear_vector(int vec, void *bitmap)
  77 {
  78         return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  79 }
  80
  81 static inline void apic_set_vector(int vec, void *bitmap)
  82 {
  83         set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  84 }
  85
  86 static inline void apic_clear_vector(int vec, void *bitmap)
  87 {
  88         clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  89 }
  90
  91 static inline int apic_hw_enabled(struct kvm_lapic *apic)
  92 {
  93         return (apic)->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
  94 }
  95
  96 static inline int  apic_sw_enabled(struct kvm_lapic *apic)
  97 {
  98         return apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED;
  99 }
 100
 101 static inline int apic_enabled(struct kvm_lapic *apic)
 102 {
 103         return apic_sw_enabled(apic) && apic_hw_enabled(apic);
 104 }
 105
 106 #define LVT_MASK        \
 107         (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
 108
 109 #define LINT_MASK       \
 110         (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
 111          APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
 112
 113 static inline int kvm_apic_id(struct kvm_lapic *apic)
 114 {
 115         return (apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
 116 }
 117
 118 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
 119 {
 120         return !(apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
 121 }
 122
 123 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
 124 {
 125         return apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
 126 }
 127
 128 static inline int apic_lvtt_period(struct kvm_lapic *apic)
 129 {
 130         return apic_get_reg(apic, APIC_LVTT) & APIC_LVT_TIMER_PERIODIC;
 131 }
 132
 133 static unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
 134         LVT_MASK | APIC_LVT_TIMER_PERIODIC,     /* LVTT */
 135         LVT_MASK | APIC_MODE_MASK,      /* LVTTHMR */
 136         LVT_MASK | APIC_MODE_MASK,      /* LVTPC */
 137         LINT_MASK, LINT_MASK,   /* LVT0-1 */
 138         LVT_MASK                /* LVTERR */
 139 };
 140
 141 static int find_highest_vector(void *bitmap)
 142 {
 143         u32 *word = bitmap;
 144         int word_offset = MAX_APIC_VECTOR >> 5;
 145
 146         while ((word_offset != 0) && (word[(--word_offset) << 2] == 0))
 147                 continue;
 148
 149         if (likely(!word_offset && !word[0]))
 150                 return -1;
 151         else
 152                 return fls(word[word_offset << 2]) - 1 + (word_offset << 5);
 153 }
 154
 155 static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic)
 156 {
 157         return apic_test_and_set_vector(vec, apic->regs + APIC_IRR);
 158 }
 159
 160 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
 161 {
 162         apic_clear_vector(vec, apic->regs + APIC_IRR);
 163 }
 164
 165 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
 166 {
 167         int result;
 168
 169         result = find_highest_vector(apic->regs + APIC_IRR);
 170         ASSERT(result == -1 || result >= 16);
 171
 172         return result;
 173 }
 174
 175 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
 176 {
 177         struct kvm_lapic *apic = vcpu->arch.apic;
 178         int highest_irr;
 179
 180         if (!apic)
 181                 return 0;
 182         highest_irr = apic_find_highest_irr(apic);
 183
 184         return highest_irr;
 185 }
 186 EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr);
 187
 188 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, u8 vec, u8 trig)
 189 {
 190         struct kvm_lapic *apic = vcpu->arch.apic;
 191
 192         if (!apic_test_and_set_irr(vec, apic)) {
 193                 /* a new pending irq is set in IRR */
 194                 if (trig)
 195                         apic_set_vector(vec, apic->regs + APIC_TMR);
 196                 else
 197                         apic_clear_vector(vec, apic->regs + APIC_TMR);
 198                 kvm_vcpu_kick(apic->vcpu);
 199                 return 1;
 200         }
 201         return 0;
 202 }
 203
 204 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
 205 {
 206         int result;
 207
 208         result = find_highest_vector(apic->regs + APIC_ISR);
 209         ASSERT(result == -1 || result >= 16);
 210
 211         return result;
 212 }
 213
 214 static void apic_update_ppr(struct kvm_lapic *apic)
 215 {
 216         u32 tpr, isrv, ppr;
 217         int isr;
 218
 219         tpr = apic_get_reg(apic, APIC_TASKPRI);
 220         isr = apic_find_highest_isr(apic);
 221         isrv = (isr != -1) ? isr : 0;
 222
 223         if ((tpr & 0xf0) >= (isrv & 0xf0))
 224                 ppr = tpr & 0xff;
 225         else
 226                 ppr = isrv & 0xf0;
 227
 228         apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
 229                    apic, ppr, isr, isrv);
 230
 231         apic_set_reg(apic, APIC_PROCPRI, ppr);
 232 }
 233
 234 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
 235 {
 236         apic_set_reg(apic, APIC_TASKPRI, tpr);
 237         apic_update_ppr(apic);
 238 }
 239
 240 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest)
 241 {
 242         return kvm_apic_id(apic) == dest;
 243 }
 244
 245 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
 246 {
 247         int result = 0;
 248         u8 logical_id;
 249
 250         logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR));
 251
 252         switch (apic_get_reg(apic, APIC_DFR)) {
 253         case APIC_DFR_FLAT:
 254                 if (logical_id & mda)
 255                         result = 1;
 256                 break;
 257         case APIC_DFR_CLUSTER:
 258                 if (((logical_id >> 4) == (mda >> 0x4))
 259                     && (logical_id & mda & 0xf))
 260                         result = 1;
 261                 break;
 262         default:
 263                 printk(KERN_WARNING "Bad DFR vcpu %d: %08x\n",
 264                        apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR));
 265                 break;
 266         }
 267
 268         return result;
 269 }
 270
 271 static int apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
 272                            int short_hand, int dest, int dest_mode)
 273 {
 274         int result = 0;
 275         struct kvm_lapic *target = vcpu->arch.apic;
 276
 277         apic_debug("target %p, source %p, dest 0x%x, "
 278                    "dest_mode 0x%x, short_hand 0x%x",
 279                    target, source, dest, dest_mode, short_hand);
 280
 281         ASSERT(!target);
 282         switch (short_hand) {
 283         case APIC_DEST_NOSHORT:
 284                 if (dest_mode == 0) {
 285                         /* Physical mode. */
 286                         if ((dest == 0xFF) || (dest == kvm_apic_id(target)))
 287                                 result = 1;
 288                 } else
 289                         /* Logical mode. */
 290                         result = kvm_apic_match_logical_addr(target, dest);
 291                 break;
 292         case APIC_DEST_SELF:
 293                 if (target == source)
 294                         result = 1;
 295                 break;
 296         case APIC_DEST_ALLINC:
 297                 result = 1;
 298                 break;
 299         case APIC_DEST_ALLBUT:
 300                 if (target != source)
 301                         result = 1;
 302                 break;
 303         default:
 304                 printk(KERN_WARNING "Bad dest shorthand value %x\n",
 305                        short_hand);
 306                 break;
 307         }
 308
 309         return result;
 310 }
 311
 312 /*
 313  * Add a pending IRQ into lapic.
 314  * Return 1 if successfully added and 0 if discarded.
 315  */
 316 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 317                              int vector, int level, int trig_mode)
 318 {
 319         int orig_irr, result = 0;
 320         struct kvm_vcpu *vcpu = apic->vcpu;
 321
 322         switch (delivery_mode) {
 323         case APIC_DM_FIXED:
 324         case APIC_DM_LOWEST:
 325                 /* FIXME add logic for vcpu on reset */
 326                 if (unlikely(!apic_enabled(apic)))
 327                         break;
 328
 329                 orig_irr = apic_test_and_set_irr(vector, apic);
 330                 if (orig_irr && trig_mode) {
 331                         apic_debug("level trig mode repeatedly for vector %d",
 332                                    vector);
 333                         break;
 334                 }
 335
 336                 if (trig_mode) {
 337                         apic_debug("level trig mode for vector %d", vector);
 338                         apic_set_vector(vector, apic->regs + APIC_TMR);
 339                 } else
 340                         apic_clear_vector(vector, apic->regs + APIC_TMR);
 341
 342                 kvm_vcpu_kick(vcpu);
 343
 344                 result = (orig_irr == 0);
 345                 break;
 346
 347         case APIC_DM_REMRD:
 348                 printk(KERN_DEBUG "Ignoring delivery mode 3\n");
 349                 break;
 350
 351         case APIC_DM_SMI:
 352                 printk(KERN_DEBUG "Ignoring guest SMI\n");
 353                 break;
 354
 355         case APIC_DM_NMI:
 356                 kvm_inject_nmi(vcpu);
 357                 break;
 358
 359         case APIC_DM_INIT:
 360                 if (level) {
 361                         if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
 362                                 printk(KERN_DEBUG
 363                                        "INIT on a runnable vcpu %d\n",
 364                                        vcpu->vcpu_id);
 365                         vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
 366                         kvm_vcpu_kick(vcpu);
 367                 } else {
 368                         apic_debug("Ignoring de-assert INIT to vcpu %d\n",
 369                                    vcpu->vcpu_id);
 370                 }
 371                 break;
 372
 373         case APIC_DM_STARTUP:
 374                 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
 375                            vcpu->vcpu_id, vector);
 376                 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
 377                         vcpu->arch.sipi_vector = vector;
 378                         vcpu->arch.mp_state = KVM_MP_STATE_SIPI_RECEIVED;
 379                         kvm_vcpu_kick(vcpu);
 380                 }
 381                 break;
 382
 383         case APIC_DM_EXTINT:
 384                 /*
 385                  * Should only be called by kvm_apic_local_deliver() with LVT0,
 386                  * before NMI watchdog was enabled. Already handled by
 387                  * kvm_apic_accept_pic_intr().
 388                  */
 389                 break;
 390
 391         default:
 392                 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
 393                        delivery_mode);
 394                 break;
 395         }
 396         return result;
 397 }
 398
 399 static struct kvm_lapic *kvm_apic_round_robin(struct kvm *kvm, u8 vector,
 400                                        unsigned long bitmap)
 401 {
 402         int last;
 403         int next;
 404         struct kvm_lapic *apic = NULL;
 405
 406         last = kvm->arch.round_robin_prev_vcpu;
 407         next = last;
 408
 409         do {
 410                 if (++next == KVM_MAX_VCPUS)
 411                         next = 0;
 412                 if (kvm->vcpus[next] == NULL || !test_bit(next, &bitmap))
 413                         continue;
 414                 apic = kvm->vcpus[next]->arch.apic;
 415                 if (apic && apic_enabled(apic))
 416                         break;
 417                 apic = NULL;
 418         } while (next != last);
 419         kvm->arch.round_robin_prev_vcpu = next;
 420
 421         if (!apic)
 422                 printk(KERN_DEBUG "vcpu not ready for apic_round_robin\n");
 423
 424         return apic;
 425 }
 426
 427 struct kvm_vcpu *kvm_get_lowest_prio_vcpu(struct kvm *kvm, u8 vector,
 428                 unsigned long bitmap)
 429 {
 430         struct kvm_lapic *apic;
 431
 432         apic = kvm_apic_round_robin(kvm, vector, bitmap);
 433         if (apic)
 434                 return apic->vcpu;
 435         return NULL;
 436 }
 437
 438 static void apic_set_eoi(struct kvm_lapic *apic)
 439 {
 440         int vector = apic_find_highest_isr(apic);
 441         int trigger_mode;
 442         /*
 443          * Not every write EOI will has corresponding ISR,
 444          * one example is when Kernel check timer on setup_IO_APIC
 445          */
 446         if (vector == -1)
 447                 return;
 448
 449         apic_clear_vector(vector, apic->regs + APIC_ISR);
 450         apic_update_ppr(apic);
 451
 452         if (apic_test_and_clear_vector(vector, apic->regs + APIC_TMR))
 453                 trigger_mode = IOAPIC_LEVEL_TRIG;
 454         else
 455                 trigger_mode = IOAPIC_EDGE_TRIG;
 456         kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode);
 457 }
 458
 459 static void apic_send_ipi(struct kvm_lapic *apic)
 460 {
 461         u32 icr_low = apic_get_reg(apic, APIC_ICR);
 462         u32 icr_high = apic_get_reg(apic, APIC_ICR2);
 463
 464         unsigned int dest = GET_APIC_DEST_FIELD(icr_high);
 465         unsigned int short_hand = icr_low & APIC_SHORT_MASK;
 466         unsigned int trig_mode = icr_low & APIC_INT_LEVELTRIG;
 467         unsigned int level = icr_low & APIC_INT_ASSERT;
 468         unsigned int dest_mode = icr_low & APIC_DEST_MASK;
 469         unsigned int delivery_mode = icr_low & APIC_MODE_MASK;
 470         unsigned int vector = icr_low & APIC_VECTOR_MASK;
 471
 472         struct kvm_vcpu *target;
 473         struct kvm_vcpu *vcpu;
 474         unsigned long lpr_map = 0;
 475         int i;
 476
 477         apic_debug("icr_high 0x%x, icr_low 0x%x, "
 478                    "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
 479                    "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
 480                    icr_high, icr_low, short_hand, dest,
 481                    trig_mode, level, dest_mode, delivery_mode, vector);
 482
 483         for (i = 0; i < KVM_MAX_VCPUS; i++) {
 484                 vcpu = apic->vcpu->kvm->vcpus[i];
 485                 if (!vcpu)
 486                         continue;
 487
 488                 if (vcpu->arch.apic &&
 489                     apic_match_dest(vcpu, apic, short_hand, dest, dest_mode)) {
 490                         if (delivery_mode == APIC_DM_LOWEST)
 491                                 set_bit(vcpu->vcpu_id, &lpr_map);
 492                         else
 493                                 __apic_accept_irq(vcpu->arch.apic, delivery_mode,
 494                                                   vector, level, trig_mode);
 495                 }
 496         }
 497
 498         if (delivery_mode == APIC_DM_LOWEST) {
 499                 target = kvm_get_lowest_prio_vcpu(vcpu->kvm, vector, lpr_map);
 500                 if (target != NULL)
 501                         __apic_accept_irq(target->arch.apic, delivery_mode,
 502                                           vector, level, trig_mode);
 503         }
 504 }
 505
 506 static u32 apic_get_tmcct(struct kvm_lapic *apic)
 507 {
 508         u64 counter_passed;
 509         ktime_t passed, now;
 510         u32 tmcct;
 511
 512         ASSERT(apic != NULL);
 513
 514         now = apic->timer.dev.base->get_time();
 515         tmcct = apic_get_reg(apic, APIC_TMICT);
 516
 517         /* if initial count is 0, current count should also be 0 */
 518         if (tmcct == 0)
 519                 return 0;
 520
 521         if (unlikely(ktime_to_ns(now) <=
 522                 ktime_to_ns(apic->timer.last_update))) {
 523                 /* Wrap around */
 524                 passed = ktime_add(( {
 525                                     (ktime_t) {
 526                                     .tv64 = KTIME_MAX -
 527                                     (apic->timer.last_update).tv64}; }
 528                                    ), now);
 529                 apic_debug("time elapsed\n");
 530         } else
 531                 passed = ktime_sub(now, apic->timer.last_update);
 532
 533         counter_passed = div64_u64(ktime_to_ns(passed),
 534                                    (APIC_BUS_CYCLE_NS * apic->timer.divide_count));
 535
 536         if (counter_passed > tmcct) {
 537                 if (unlikely(!apic_lvtt_period(apic))) {
 538                         /* one-shot timers stick at 0 until reset */
 539                         tmcct = 0;
 540                 } else {
 541                         /*
 542                          * periodic timers reset to APIC_TMICT when they
 543                          * hit 0. The while loop simulates this happening N
 544                          * times. (counter_passed %= tmcct) would also work,
 545                          * but might be slower or not work on 32-bit??
 546                          */
 547                         while (counter_passed > tmcct)
 548                                 counter_passed -= tmcct;
 549                         tmcct -= counter_passed;
 550                 }
 551         } else {
 552                 tmcct -= counter_passed;
 553         }
 554
 555         return tmcct;
 556 }
 557
 558 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
 559 {
 560         struct kvm_vcpu *vcpu = apic->vcpu;
 561         struct kvm_run *run = vcpu->run;
 562
 563         set_bit(KVM_REQ_REPORT_TPR_ACCESS, &vcpu->requests);
 564         run->tpr_access.rip = kvm_rip_read(vcpu);
 565         run->tpr_access.is_write = write;
 566 }
 567
 568 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
 569 {
 570         if (apic->vcpu->arch.tpr_access_reporting)
 571                 __report_tpr_access(apic, write);
 572 }
 573
 574 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
 575 {
 576         u32 val = 0;
 577
 578         KVMTRACE_1D(APIC_ACCESS, apic->vcpu, (u32)offset, handler);
 579
 580         if (offset >= LAPIC_MMIO_LENGTH)
 581                 return 0;
 582
 583         switch (offset) {
 584         case APIC_ARBPRI:
 585                 printk(KERN_WARNING "Access APIC ARBPRI register "
 586                        "which is for P6\n");
 587                 break;
 588
 589         case APIC_TMCCT:        /* Timer CCR */
 590                 val = apic_get_tmcct(apic);
 591                 break;
 592
 593         case APIC_TASKPRI:
 594                 report_tpr_access(apic, false);
 595                 /* fall thru */
 596         default:
 597                 apic_update_ppr(apic);
 598                 val = apic_get_reg(apic, offset);
 599                 break;
 600         }
 601
 602         return val;
 603 }
 604
 605 static void apic_mmio_read(struct kvm_io_device *this,
 606                            gpa_t address, int len, void *data)
 607 {
 608         struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
 609         unsigned int offset = address - apic->base_address;
 610         unsigned char alignment = offset & 0xf;
 611         u32 result;
 612
 613         if ((alignment + len) > 4) {
 614                 printk(KERN_ERR "KVM_APIC_READ: alignment error %lx %d",
 615                        (unsigned long)address, len);
 616                 return;
 617         }
 618         result = __apic_read(apic, offset & ~0xf);
 619
 620         switch (len) {
 621         case 1:
 622         case 2:
 623         case 4:
 624                 memcpy(data, (char *)&result + alignment, len);
 625                 break;
 626         default:
 627                 printk(KERN_ERR "Local APIC read with len = %x, "
 628                        "should be 1,2, or 4 instead\n", len);
 629                 break;
 630         }
 631 }
 632
 633 static void update_divide_count(struct kvm_lapic *apic)
 634 {
 635         u32 tmp1, tmp2, tdcr;
 636
 637         tdcr = apic_get_reg(apic, APIC_TDCR);
 638         tmp1 = tdcr & 0xf;
 639         tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
 640         apic->timer.divide_count = 0x1 << (tmp2 & 0x7);
 641
 642         apic_debug("timer divide count is 0x%x\n",
 643                                    apic->timer.divide_count);
 644 }
 645
 646 static void start_apic_timer(struct kvm_lapic *apic)
 647 {
 648         ktime_t now = apic->timer.dev.base->get_time();
 649
 650         apic->timer.last_update = now;
 651
 652         apic->timer.period = apic_get_reg(apic, APIC_TMICT) *
 653                     APIC_BUS_CYCLE_NS * apic->timer.divide_count;
 654         atomic_set(&apic->timer.pending, 0);
 655
 656         if (!apic->timer.period)
 657                 return;
 658
 659         hrtimer_start(&apic->timer.dev,
 660                       ktime_add_ns(now, apic->timer.period),
 661                       HRTIMER_MODE_ABS);
 662
 663         apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
 664                            PRIx64 ", "
 665                            "timer initial count 0x%x, period %lldns, "
 666                            "expire @ 0x%016" PRIx64 ".\n", __func__,
 667                            APIC_BUS_CYCLE_NS, ktime_to_ns(now),
 668                            apic_get_reg(apic, APIC_TMICT),
 669                            apic->timer.period,
 670                            ktime_to_ns(ktime_add_ns(now,
 671                                         apic->timer.period)));
 672 }
 673
 674 static void apic_mmio_write(struct kvm_io_device *this,
 675                             gpa_t address, int len, const void *data)
 676 {
 677         struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
 678         unsigned int offset = address - apic->base_address;
 679         unsigned char alignment = offset & 0xf;
 680         u32 val;
 681
 682         /*
 683          * APIC register must be aligned on 128-bits boundary.
 684          * 32/64/128 bits registers must be accessed thru 32 bits.
 685          * Refer SDM 8.4.1
 686          */
 687         if (len != 4 || alignment) {
 688                 /* Don't shout loud, $infamous_os would cause only noise. */
 689                 apic_debug("apic write: bad size=%d %lx\n",
 690                            len, (long)address);
 691                 return;
 692         }
 693
 694         val = *(u32 *) data;
 695
 696         /* too common printing */
 697         if (offset != APIC_EOI)
 698                 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
 699                            "0x%x\n", __func__, offset, len, val);
 700
 701         offset &= 0xff0;
 702
 703         KVMTRACE_1D(APIC_ACCESS, apic->vcpu, (u32)offset, handler);
 704
 705         switch (offset) {
 706         case APIC_ID:           /* Local APIC ID */
 707                 apic_set_reg(apic, APIC_ID, val);
 708                 break;
 709
 710         case APIC_TASKPRI:
 711                 report_tpr_access(apic, true);
 712                 apic_set_tpr(apic, val & 0xff);
 713                 break;
 714
 715         case APIC_EOI:
 716                 apic_set_eoi(apic);
 717                 break;
 718
 719         case APIC_LDR:
 720                 apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK);
 721                 break;
 722
 723         case APIC_DFR:
 724                 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
 725                 break;
 726
 727         case APIC_SPIV:
 728                 apic_set_reg(apic, APIC_SPIV, val & 0x3ff);
 729                 if (!(val & APIC_SPIV_APIC_ENABLED)) {
 730                         int i;
 731                         u32 lvt_val;
 732
 733                         for (i = 0; i < APIC_LVT_NUM; i++) {
 734                                 lvt_val = apic_get_reg(apic,
 735                                                        APIC_LVTT + 0x10 * i);
 736                                 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
 737                                              lvt_val | APIC_LVT_MASKED);
 738                         }
 739                         atomic_set(&apic->timer.pending, 0);
 740
 741                 }
 742                 break;
 743
 744         case APIC_ICR:
 745                 /* No delay here, so we always clear the pending bit */
 746                 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
 747                 apic_send_ipi(apic);
 748                 break;
 749
 750         case APIC_ICR2:
 751                 apic_set_reg(apic, APIC_ICR2, val & 0xff000000);
 752                 break;
 753
 754         case APIC_LVT0:
 755                 if (val == APIC_DM_NMI)
 756                         apic_debug("Receive NMI setting on APIC_LVT0 "
 757                                 "for cpu %d\n", apic->vcpu->vcpu_id);
 758         case APIC_LVTT:
 759         case APIC_LVTTHMR:
 760         case APIC_LVTPC:
 761         case APIC_LVT1:
 762         case APIC_LVTERR:
 763                 /* TODO: Check vector */
 764                 if (!apic_sw_enabled(apic))
 765                         val |= APIC_LVT_MASKED;
 766
 767                 val &= apic_lvt_mask[(offset - APIC_LVTT) >> 4];
 768                 apic_set_reg(apic, offset, val);
 769
 770                 break;
 771
 772         case APIC_TMICT:
 773                 hrtimer_cancel(&apic->timer.dev);
 774                 apic_set_reg(apic, APIC_TMICT, val);
 775                 start_apic_timer(apic);
 776                 return;
 777
 778         case APIC_TDCR:
 779                 if (val & 4)
 780                         printk(KERN_ERR "KVM_WRITE:TDCR %x\n", val);
 781                 apic_set_reg(apic, APIC_TDCR, val);
 782                 update_divide_count(apic);
 783                 break;
 784
 785         default:
 786                 apic_debug("Local APIC Write to read-only register %x\n",
 787                            offset);
 788                 break;
 789         }
 790
 791 }
 792
 793 static int apic_mmio_range(struct kvm_io_device *this, gpa_t addr,
 794                            int len, int size)
 795 {
 796         struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
 797         int ret = 0;
 798
 799
 800         if (apic_hw_enabled(apic) &&
 801             (addr >= apic->base_address) &&
 802             (addr < (apic->base_address + LAPIC_MMIO_LENGTH)))
 803                 ret = 1;
 804
 805         return ret;
 806 }
 807
 808 void kvm_free_lapic(struct kvm_vcpu *vcpu)
 809 {
 810         if (!vcpu->arch.apic)
 811                 return;
 812
 813         hrtimer_cancel(&vcpu->arch.apic->timer.dev);
 814
 815         if (vcpu->arch.apic->regs_page)
 816                 __free_page(vcpu->arch.apic->regs_page);
 817
 818         kfree(vcpu->arch.apic);
 819 }
 820
 821 /*
 822  *----------------------------------------------------------------------
 823  * LAPIC interface
 824  *----------------------------------------------------------------------
 825  */
 826
 827 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
 828 {
 829         struct kvm_lapic *apic = vcpu->arch.apic;
 830
 831         if (!apic)
 832                 return;
 833         apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
 834                      | (apic_get_reg(apic, APIC_TASKPRI) & 4));
 835 }
 836 EXPORT_SYMBOL_GPL(kvm_lapic_set_tpr);
 837
 838 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
 839 {
 840         struct kvm_lapic *apic = vcpu->arch.apic;
 841         u64 tpr;
 842
 843         if (!apic)
 844                 return 0;
 845         tpr = (u64) apic_get_reg(apic, APIC_TASKPRI);
 846
 847         return (tpr & 0xf0) >> 4;
 848 }
 849 EXPORT_SYMBOL_GPL(kvm_lapic_get_cr8);
 850
 851 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
 852 {
 853         struct kvm_lapic *apic = vcpu->arch.apic;
 854
 855         if (!apic) {
 856                 value |= MSR_IA32_APICBASE_BSP;
 857                 vcpu->arch.apic_base = value;
 858                 return;
 859         }
 860         if (apic->vcpu->vcpu_id)
 861                 value &= ~MSR_IA32_APICBASE_BSP;
 862
 863         vcpu->arch.apic_base = value;
 864         apic->base_address = apic->vcpu->arch.apic_base &
 865                              MSR_IA32_APICBASE_BASE;
 866
 867         /* with FSB delivery interrupt, we can restart APIC functionality */
 868         apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
 869                    "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
 870
 871 }
 872
 873 u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu)
 874 {
 875         return vcpu->arch.apic_base;
 876 }
 877 EXPORT_SYMBOL_GPL(kvm_lapic_get_base);
 878
 879 void kvm_lapic_reset(struct kvm_vcpu *vcpu)
 880 {
 881         struct kvm_lapic *apic;
 882         int i;
 883
 884         apic_debug("%s\n", __func__);
 885
 886         ASSERT(vcpu);
 887         apic = vcpu->arch.apic;
 888         ASSERT(apic != NULL);
 889
 890         /* Stop the timer in case it's a reset to an active apic */
 891         hrtimer_cancel(&apic->timer.dev);
 892
 893         apic_set_reg(apic, APIC_ID, vcpu->vcpu_id << 24);
 894         apic_set_reg(apic, APIC_LVR, APIC_VERSION);
 895
 896         for (i = 0; i < APIC_LVT_NUM; i++)
 897                 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
 898         apic_set_reg(apic, APIC_LVT0,
 899                      SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
 900
 901         apic_set_reg(apic, APIC_DFR, 0xffffffffU);
 902         apic_set_reg(apic, APIC_SPIV, 0xff);
 903         apic_set_reg(apic, APIC_TASKPRI, 0);
 904         apic_set_reg(apic, APIC_LDR, 0);
 905         apic_set_reg(apic, APIC_ESR, 0);
 906         apic_set_reg(apic, APIC_ICR, 0);
 907         apic_set_reg(apic, APIC_ICR2, 0);
 908         apic_set_reg(apic, APIC_TDCR, 0);
 909         apic_set_reg(apic, APIC_TMICT, 0);
 910         for (i = 0; i < 8; i++) {
 911                 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
 912                 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
 913                 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
 914         }
 915         update_divide_count(apic);
 916         atomic_set(&apic->timer.pending, 0);
 917         if (vcpu->vcpu_id == 0)
 918                 vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP;
 919         apic_update_ppr(apic);
 920
 921         apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr="
 922                    "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
 923                    vcpu, kvm_apic_id(apic),
 924                    vcpu->arch.apic_base, apic->base_address);
 925 }
 926 EXPORT_SYMBOL_GPL(kvm_lapic_reset);
 927
 928 int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
 929 {
 930         struct kvm_lapic *apic = vcpu->arch.apic;
 931         int ret = 0;
 932
 933         if (!apic)
 934                 return 0;
 935         ret = apic_enabled(apic);
 936
 937         return ret;
 938 }
 939 EXPORT_SYMBOL_GPL(kvm_lapic_enabled);
 940
 941 /*
 942  *----------------------------------------------------------------------
 943  * timer interface
 944  *----------------------------------------------------------------------
 945  */
 946
 947 /* TODO: make sure __apic_timer_fn runs in current pCPU */
 948 static int __apic_timer_fn(struct kvm_lapic *apic)
 949 {
 950         int result = 0;
 951         wait_queue_head_t *q = &apic->vcpu->wq;
 952
 953         if(!atomic_inc_and_test(&apic->timer.pending))
 954                 set_bit(KVM_REQ_PENDING_TIMER, &apic->vcpu->requests);
 955         if (waitqueue_active(q))
 956                 wake_up_interruptible(q);
 957
 958         if (apic_lvtt_period(apic)) {
 959                 result = 1;
 960                 hrtimer_add_expires_ns(&apic->timer.dev, apic->timer.period);
 961         }
 962         return result;
 963 }
 964
 965 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
 966 {
 967         struct kvm_lapic *lapic = vcpu->arch.apic;
 968
 969         if (lapic && apic_enabled(lapic) && apic_lvt_enabled(lapic, APIC_LVTT))
 970                 return atomic_read(&lapic->timer.pending);
 971
 972         return 0;
 973 }
 974
 975 int kvm_apic_local_deliver(struct kvm_vcpu *vcpu, int lvt_type)
 976 {
 977         struct kvm_lapic *apic = vcpu->arch.apic;
 978         int vector, mode, trig_mode;
 979         u32 reg;
 980
 981         if (apic && apic_enabled(apic)) {
 982                 reg = apic_get_reg(apic, lvt_type);
 983                 vector = reg & APIC_VECTOR_MASK;
 984                 mode = reg & APIC_MODE_MASK;
 985                 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
 986                 return __apic_accept_irq(apic, mode, vector, 1, trig_mode);
 987         }
 988         return 0;
 989 }
 990
 991 static inline int __inject_apic_timer_irq(struct kvm_lapic *apic)
 992 {
 993         return kvm_apic_local_deliver(apic->vcpu, APIC_LVTT);
 994 }
 995
 996 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
 997 {
 998         struct kvm_lapic *apic;
 999         int restart_timer = 0;
1000
1001         apic = container_of(data, struct kvm_lapic, timer.dev);
1002
1003         restart_timer = __apic_timer_fn(apic);
1004
1005         if (restart_timer)
1006                 return HRTIMER_RESTART;
1007         else
1008                 return HRTIMER_NORESTART;
1009 }
1010
1011 int kvm_create_lapic(struct kvm_vcpu *vcpu)
1012 {
1013         struct kvm_lapic *apic;
1014
1015         ASSERT(vcpu != NULL);
1016         apic_debug("apic_init %d\n", vcpu->vcpu_id);
1017
1018         apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1019         if (!apic)
1020                 goto nomem;
1021
1022         vcpu->arch.apic = apic;
1023
1024         apic->regs_page = alloc_page(GFP_KERNEL);
1025         if (apic->regs_page == NULL) {
1026                 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1027                        vcpu->vcpu_id);
1028                 goto nomem_free_apic;
1029         }
1030         apic->regs = page_address(apic->regs_page);
1031         memset(apic->regs, 0, PAGE_SIZE);
1032         apic->vcpu = vcpu;
1033
1034         hrtimer_init(&apic->timer.dev, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
1035         apic->timer.dev.function = apic_timer_fn;
1036         apic->base_address = APIC_DEFAULT_PHYS_BASE;
1037         vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE;
1038
1039         kvm_lapic_reset(vcpu);
1040         apic->dev.read = apic_mmio_read;
1041         apic->dev.write = apic_mmio_write;
1042         apic->dev.in_range = apic_mmio_range;
1043         apic->dev.private = apic;
1044
1045         return 0;
1046 nomem_free_apic:
1047         kfree(apic);
1048 nomem:
1049         return -ENOMEM;
1050 }
1051 EXPORT_SYMBOL_GPL(kvm_create_lapic);
1052
1053 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1054 {
1055         struct kvm_lapic *apic = vcpu->arch.apic;
1056         int highest_irr;
1057
1058         if (!apic || !apic_enabled(apic))
1059                 return -1;
1060
1061         apic_update_ppr(apic);
1062         highest_irr = apic_find_highest_irr(apic);
1063         if ((highest_irr == -1) ||
1064             ((highest_irr & 0xF0) <= apic_get_reg(apic, APIC_PROCPRI)))
1065                 return -1;
1066         return highest_irr;
1067 }
1068
1069 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1070 {
1071         u32 lvt0 = apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1072         int r = 0;
1073
1074         if (vcpu->vcpu_id == 0) {
1075                 if (!apic_hw_enabled(vcpu->arch.apic))
1076                         r = 1;
1077                 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1078                     GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1079                         r = 1;
1080         }
1081         return r;
1082 }
1083
1084 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1085 {
1086         struct kvm_lapic *apic = vcpu->arch.apic;
1087
1088         if (apic && apic_lvt_enabled(apic, APIC_LVTT) &&
1089                 atomic_read(&apic->timer.pending) > 0) {
1090                 if (__inject_apic_timer_irq(apic))
1091                         atomic_dec(&apic->timer.pending);
1092         }
1093 }
1094
1095 void kvm_apic_timer_intr_post(struct kvm_vcpu *vcpu, int vec)
1096 {
1097         struct kvm_lapic *apic = vcpu->arch.apic;
1098
1099         if (apic && apic_lvt_vector(apic, APIC_LVTT) == vec)
1100                 apic->timer.last_update = ktime_add_ns(
1101                                 apic->timer.last_update,
1102                                 apic->timer.period);
1103 }
1104
1105 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1106 {
1107         int vector = kvm_apic_has_interrupt(vcpu);
1108         struct kvm_lapic *apic = vcpu->arch.apic;
1109
1110         if (vector == -1)
1111                 return -1;
1112
1113         apic_set_vector(vector, apic->regs + APIC_ISR);
1114         apic_update_ppr(apic);
1115         apic_clear_irr(vector, apic);
1116         return vector;
1117 }
1118
1119 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu)
1120 {
1121         struct kvm_lapic *apic = vcpu->arch.apic;
1122
1123         apic->base_address = vcpu->arch.apic_base &
1124                              MSR_IA32_APICBASE_BASE;
1125         apic_set_reg(apic, APIC_LVR, APIC_VERSION);
1126         apic_update_ppr(apic);
1127         hrtimer_cancel(&apic->timer.dev);
1128         update_divide_count(apic);
1129         start_apic_timer(apic);
1130 }
1131
1132 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1133 {
1134         struct kvm_lapic *apic = vcpu->arch.apic;
1135         struct hrtimer *timer;
1136
1137         if (!apic)
1138                 return;
1139
1140         timer = &apic->timer.dev;
1141         if (hrtimer_cancel(timer))
1142                 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
1143 }
1144
1145 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1146 {
1147         u32 data;
1148         void *vapic;
1149
1150         if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1151                 return;
1152
1153         vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1154         data = *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr));
1155         kunmap_atomic(vapic, KM_USER0);
1156
1157         apic_set_tpr(vcpu->arch.apic, data & 0xff);
1158 }
1159
1160 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1161 {
1162         u32 data, tpr;
1163         int max_irr, max_isr;
1164         struct kvm_lapic *apic;
1165         void *vapic;
1166
1167         if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1168                 return;
1169
1170         apic = vcpu->arch.apic;
1171         tpr = apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1172         max_irr = apic_find_highest_irr(apic);
1173         if (max_irr < 0)
1174                 max_irr = 0;
1175         max_isr = apic_find_highest_isr(apic);
1176         if (max_isr < 0)
1177                 max_isr = 0;
1178         data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1179
1180         vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1181         *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)) = data;
1182         kunmap_atomic(vapic, KM_USER0);
1183 }
1184
1185 void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1186 {
1187         if (!irqchip_in_kernel(vcpu->kvm))
1188                 return;
1189
1190         vcpu->arch.apic->vapic_addr = vapic_addr;
1191 }