SAFE public projects git trees. - safe/jmp/linux-2.6/blob - arch/x86/kvm/lapic.c

   1
   2 /*
   3  * Local APIC virtualization
   4  *
   5  * Copyright (C) 2006 Qumranet, Inc.
   6  * Copyright (C) 2007 Novell
   7  * Copyright (C) 2007 Intel
   8  *
   9  * Authors:
  10  *   Dor Laor <dor.laor@qumranet.com>
  11  *   Gregory Haskins <ghaskins@novell.com>
  12  *   Yaozu (Eddie) Dong <eddie.dong@intel.com>
  13  *
  14  * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
  15  *
  16  * This work is licensed under the terms of the GNU GPL, version 2.  See
  17  * the COPYING file in the top-level directory.
  18  */
  19
  20 #include <linux/kvm_host.h>
  21 #include <linux/kvm.h>
  22 #include <linux/mm.h>
  23 #include <linux/highmem.h>
  24 #include <linux/smp.h>
  25 #include <linux/hrtimer.h>
  26 #include <linux/io.h>
  27 #include <linux/module.h>
  28 #include <linux/math64.h>
  29 #include <asm/processor.h>
  30 #include <asm/msr.h>
  31 #include <asm/page.h>
  32 #include <asm/current.h>
  33 #include <asm/apicdef.h>
  34 #include <asm/atomic.h>
  35 #include "kvm_cache_regs.h"
  36 #include "irq.h"
  37
  38 #ifndef CONFIG_X86_64
  39 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
  40 #else
  41 #define mod_64(x, y) ((x) % (y))
  42 #endif
  43
  44 #define PRId64 "d"
  45 #define PRIx64 "llx"
  46 #define PRIu64 "u"
  47 #define PRIo64 "o"
  48
  49 #define APIC_BUS_CYCLE_NS 1
  50
  51 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
  52 #define apic_debug(fmt, arg...)
  53
  54 #define APIC_LVT_NUM                    6
  55 /* 14 is the version for Xeon and Pentium 8.4.8*/
  56 #define APIC_VERSION                    (0x14UL | ((APIC_LVT_NUM - 1) << 16))
  57 #define LAPIC_MMIO_LENGTH               (1 << 12)
  58 /* followed define is not in apicdef.h */
  59 #define APIC_SHORT_MASK                 0xc0000
  60 #define APIC_DEST_NOSHORT               0x0
  61 #define APIC_DEST_MASK                  0x800
  62 #define MAX_APIC_VECTOR                 256
  63
  64 #define VEC_POS(v) ((v) & (32 - 1))
  65 #define REG_POS(v) (((v) >> 5) << 4)
  66
  67 static inline u32 apic_get_reg(struct kvm_lapic *apic, int reg_off)
  68 {
  69         return *((u32 *) (apic->regs + reg_off));
  70 }
  71
  72 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
  73 {
  74         *((u32 *) (apic->regs + reg_off)) = val;
  75 }
  76
  77 static inline int apic_test_and_set_vector(int vec, void *bitmap)
  78 {
  79         return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  80 }
  81
  82 static inline int apic_test_and_clear_vector(int vec, void *bitmap)
  83 {
  84         return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  85 }
  86
  87 static inline void apic_set_vector(int vec, void *bitmap)
  88 {
  89         set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  90 }
  91
  92 static inline void apic_clear_vector(int vec, void *bitmap)
  93 {
  94         clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  95 }
  96
  97 static inline int apic_hw_enabled(struct kvm_lapic *apic)
  98 {
  99         return (apic)->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
 100 }
 101
 102 static inline int  apic_sw_enabled(struct kvm_lapic *apic)
 103 {
 104         return apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED;
 105 }
 106
 107 static inline int apic_enabled(struct kvm_lapic *apic)
 108 {
 109         return apic_sw_enabled(apic) && apic_hw_enabled(apic);
 110 }
 111
 112 #define LVT_MASK        \
 113         (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
 114
 115 #define LINT_MASK       \
 116         (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
 117          APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
 118
 119 static inline int kvm_apic_id(struct kvm_lapic *apic)
 120 {
 121         return (apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
 122 }
 123
 124 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
 125 {
 126         return !(apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
 127 }
 128
 129 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
 130 {
 131         return apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
 132 }
 133
 134 static inline int apic_lvtt_period(struct kvm_lapic *apic)
 135 {
 136         return apic_get_reg(apic, APIC_LVTT) & APIC_LVT_TIMER_PERIODIC;
 137 }
 138
 139 static inline int apic_lvt_nmi_mode(u32 lvt_val)
 140 {
 141         return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
 142 }
 143
 144 static unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
 145         LVT_MASK | APIC_LVT_TIMER_PERIODIC,     /* LVTT */
 146         LVT_MASK | APIC_MODE_MASK,      /* LVTTHMR */
 147         LVT_MASK | APIC_MODE_MASK,      /* LVTPC */
 148         LINT_MASK, LINT_MASK,   /* LVT0-1 */
 149         LVT_MASK                /* LVTERR */
 150 };
 151
 152 static int find_highest_vector(void *bitmap)
 153 {
 154         u32 *word = bitmap;
 155         int word_offset = MAX_APIC_VECTOR >> 5;
 156
 157         while ((word_offset != 0) && (word[(--word_offset) << 2] == 0))
 158                 continue;
 159
 160         if (likely(!word_offset && !word[0]))
 161                 return -1;
 162         else
 163                 return fls(word[word_offset << 2]) - 1 + (word_offset << 5);
 164 }
 165
 166 static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic)
 167 {
 168         return apic_test_and_set_vector(vec, apic->regs + APIC_IRR);
 169 }
 170
 171 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
 172 {
 173         apic_clear_vector(vec, apic->regs + APIC_IRR);
 174 }
 175
 176 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
 177 {
 178         int result;
 179
 180         result = find_highest_vector(apic->regs + APIC_IRR);
 181         ASSERT(result == -1 || result >= 16);
 182
 183         return result;
 184 }
 185
 186 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
 187 {
 188         struct kvm_lapic *apic = vcpu->arch.apic;
 189         int highest_irr;
 190
 191         if (!apic)
 192                 return 0;
 193         highest_irr = apic_find_highest_irr(apic);
 194
 195         return highest_irr;
 196 }
 197
 198 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 199                              int vector, int level, int trig_mode);
 200
 201 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq)
 202 {
 203         struct kvm_lapic *apic = vcpu->arch.apic;
 204
 205         return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
 206                         irq->level, irq->trig_mode);
 207 }
 208
 209 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
 210 {
 211         int result;
 212
 213         result = find_highest_vector(apic->regs + APIC_ISR);
 214         ASSERT(result == -1 || result >= 16);
 215
 216         return result;
 217 }
 218
 219 static void apic_update_ppr(struct kvm_lapic *apic)
 220 {
 221         u32 tpr, isrv, ppr;
 222         int isr;
 223
 224         tpr = apic_get_reg(apic, APIC_TASKPRI);
 225         isr = apic_find_highest_isr(apic);
 226         isrv = (isr != -1) ? isr : 0;
 227
 228         if ((tpr & 0xf0) >= (isrv & 0xf0))
 229                 ppr = tpr & 0xff;
 230         else
 231                 ppr = isrv & 0xf0;
 232
 233         apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
 234                    apic, ppr, isr, isrv);
 235
 236         apic_set_reg(apic, APIC_PROCPRI, ppr);
 237 }
 238
 239 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
 240 {
 241         apic_set_reg(apic, APIC_TASKPRI, tpr);
 242         apic_update_ppr(apic);
 243 }
 244
 245 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest)
 246 {
 247         return dest == 0xff || kvm_apic_id(apic) == dest;
 248 }
 249
 250 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
 251 {
 252         int result = 0;
 253         u8 logical_id;
 254
 255         logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR));
 256
 257         switch (apic_get_reg(apic, APIC_DFR)) {
 258         case APIC_DFR_FLAT:
 259                 if (logical_id & mda)
 260                         result = 1;
 261                 break;
 262         case APIC_DFR_CLUSTER:
 263                 if (((logical_id >> 4) == (mda >> 0x4))
 264                     && (logical_id & mda & 0xf))
 265                         result = 1;
 266                 break;
 267         default:
 268                 printk(KERN_WARNING "Bad DFR vcpu %d: %08x\n",
 269                        apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR));
 270                 break;
 271         }
 272
 273         return result;
 274 }
 275
 276 int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
 277                            int short_hand, int dest, int dest_mode)
 278 {
 279         int result = 0;
 280         struct kvm_lapic *target = vcpu->arch.apic;
 281
 282         apic_debug("target %p, source %p, dest 0x%x, "
 283                    "dest_mode 0x%x, short_hand 0x%x\n",
 284                    target, source, dest, dest_mode, short_hand);
 285
 286         ASSERT(!target);
 287         switch (short_hand) {
 288         case APIC_DEST_NOSHORT:
 289                 if (dest_mode == 0)
 290                         /* Physical mode. */
 291                         result = kvm_apic_match_physical_addr(target, dest);
 292                 else
 293                         /* Logical mode. */
 294                         result = kvm_apic_match_logical_addr(target, dest);
 295                 break;
 296         case APIC_DEST_SELF:
 297                 result = (target == source);
 298                 break;
 299         case APIC_DEST_ALLINC:
 300                 result = 1;
 301                 break;
 302         case APIC_DEST_ALLBUT:
 303                 result = (target != source);
 304                 break;
 305         default:
 306                 printk(KERN_WARNING "Bad dest shorthand value %x\n",
 307                        short_hand);
 308                 break;
 309         }
 310
 311         return result;
 312 }
 313
 314 /*
 315  * Add a pending IRQ into lapic.
 316  * Return 1 if successfully added and 0 if discarded.
 317  */
 318 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 319                              int vector, int level, int trig_mode)
 320 {
 321         int result = 0;
 322         struct kvm_vcpu *vcpu = apic->vcpu;
 323
 324         switch (delivery_mode) {
 325         case APIC_DM_LOWEST:
 326                 vcpu->arch.apic_arb_prio++;
 327         case APIC_DM_FIXED:
 328                 /* FIXME add logic for vcpu on reset */
 329                 if (unlikely(!apic_enabled(apic)))
 330                         break;
 331
 332                 result = !apic_test_and_set_irr(vector, apic);
 333                 if (!result) {
 334                         if (trig_mode)
 335                                 apic_debug("level trig mode repeatedly for "
 336                                                 "vector %d", vector);
 337                         break;
 338                 }
 339
 340                 if (trig_mode) {
 341                         apic_debug("level trig mode for vector %d", vector);
 342                         apic_set_vector(vector, apic->regs + APIC_TMR);
 343                 } else
 344                         apic_clear_vector(vector, apic->regs + APIC_TMR);
 345                 kvm_vcpu_kick(vcpu);
 346                 break;
 347
 348         case APIC_DM_REMRD:
 349                 printk(KERN_DEBUG "Ignoring delivery mode 3\n");
 350                 break;
 351
 352         case APIC_DM_SMI:
 353                 printk(KERN_DEBUG "Ignoring guest SMI\n");
 354                 break;
 355
 356         case APIC_DM_NMI:
 357                 result = 1;
 358                 kvm_inject_nmi(vcpu);
 359                 kvm_vcpu_kick(vcpu);
 360                 break;
 361
 362         case APIC_DM_INIT:
 363                 if (level) {
 364                         result = 1;
 365                         if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
 366                                 printk(KERN_DEBUG
 367                                        "INIT on a runnable vcpu %d\n",
 368                                        vcpu->vcpu_id);
 369                         vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
 370                         kvm_vcpu_kick(vcpu);
 371                 } else {
 372                         apic_debug("Ignoring de-assert INIT to vcpu %d\n",
 373                                    vcpu->vcpu_id);
 374                 }
 375                 break;
 376
 377         case APIC_DM_STARTUP:
 378                 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
 379                            vcpu->vcpu_id, vector);
 380                 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
 381                         result = 1;
 382                         vcpu->arch.sipi_vector = vector;
 383                         vcpu->arch.mp_state = KVM_MP_STATE_SIPI_RECEIVED;
 384                         kvm_vcpu_kick(vcpu);
 385                 }
 386                 break;
 387
 388         case APIC_DM_EXTINT:
 389                 /*
 390                  * Should only be called by kvm_apic_local_deliver() with LVT0,
 391                  * before NMI watchdog was enabled. Already handled by
 392                  * kvm_apic_accept_pic_intr().
 393                  */
 394                 break;
 395
 396         default:
 397                 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
 398                        delivery_mode);
 399                 break;
 400         }
 401         return result;
 402 }
 403
 404 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
 405 {
 406         return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
 407 }
 408
 409 static void apic_set_eoi(struct kvm_lapic *apic)
 410 {
 411         int vector = apic_find_highest_isr(apic);
 412         int trigger_mode;
 413         /*
 414          * Not every write EOI will has corresponding ISR,
 415          * one example is when Kernel check timer on setup_IO_APIC
 416          */
 417         if (vector == -1)
 418                 return;
 419
 420         apic_clear_vector(vector, apic->regs + APIC_ISR);
 421         apic_update_ppr(apic);
 422
 423         if (apic_test_and_clear_vector(vector, apic->regs + APIC_TMR))
 424                 trigger_mode = IOAPIC_LEVEL_TRIG;
 425         else
 426                 trigger_mode = IOAPIC_EDGE_TRIG;
 427         kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode);
 428 }
 429
 430 static void apic_send_ipi(struct kvm_lapic *apic)
 431 {
 432         u32 icr_low = apic_get_reg(apic, APIC_ICR);
 433         u32 icr_high = apic_get_reg(apic, APIC_ICR2);
 434         struct kvm_lapic_irq irq;
 435
 436         irq.vector = icr_low & APIC_VECTOR_MASK;
 437         irq.delivery_mode = icr_low & APIC_MODE_MASK;
 438         irq.dest_mode = icr_low & APIC_DEST_MASK;
 439         irq.level = icr_low & APIC_INT_ASSERT;
 440         irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
 441         irq.shorthand = icr_low & APIC_SHORT_MASK;
 442         irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
 443
 444         apic_debug("icr_high 0x%x, icr_low 0x%x, "
 445                    "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
 446                    "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
 447                    icr_high, icr_low, irq.shorthand, irq.dest_id,
 448                    irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
 449                    irq.vector);
 450
 451         kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq);
 452 }
 453
 454 static u32 apic_get_tmcct(struct kvm_lapic *apic)
 455 {
 456         ktime_t remaining;
 457         s64 ns;
 458         u32 tmcct;
 459
 460         ASSERT(apic != NULL);
 461
 462         /* if initial count is 0, current count should also be 0 */
 463         if (apic_get_reg(apic, APIC_TMICT) == 0)
 464                 return 0;
 465
 466         remaining = hrtimer_expires_remaining(&apic->lapic_timer.timer);
 467         if (ktime_to_ns(remaining) < 0)
 468                 remaining = ktime_set(0, 0);
 469
 470         ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
 471         tmcct = div64_u64(ns,
 472                          (APIC_BUS_CYCLE_NS * apic->divide_count));
 473
 474         return tmcct;
 475 }
 476
 477 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
 478 {
 479         struct kvm_vcpu *vcpu = apic->vcpu;
 480         struct kvm_run *run = vcpu->run;
 481
 482         set_bit(KVM_REQ_REPORT_TPR_ACCESS, &vcpu->requests);
 483         run->tpr_access.rip = kvm_rip_read(vcpu);
 484         run->tpr_access.is_write = write;
 485 }
 486
 487 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
 488 {
 489         if (apic->vcpu->arch.tpr_access_reporting)
 490                 __report_tpr_access(apic, write);
 491 }
 492
 493 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
 494 {
 495         u32 val = 0;
 496
 497         KVMTRACE_1D(APIC_ACCESS, apic->vcpu, (u32)offset, handler);
 498
 499         if (offset >= LAPIC_MMIO_LENGTH)
 500                 return 0;
 501
 502         switch (offset) {
 503         case APIC_ARBPRI:
 504                 printk(KERN_WARNING "Access APIC ARBPRI register "
 505                        "which is for P6\n");
 506                 break;
 507
 508         case APIC_TMCCT:        /* Timer CCR */
 509                 val = apic_get_tmcct(apic);
 510                 break;
 511
 512         case APIC_TASKPRI:
 513                 report_tpr_access(apic, false);
 514                 /* fall thru */
 515         default:
 516                 apic_update_ppr(apic);
 517                 val = apic_get_reg(apic, offset);
 518                 break;
 519         }
 520
 521         return val;
 522 }
 523
 524 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
 525 {
 526         return container_of(dev, struct kvm_lapic, dev);
 527 }
 528
 529 static void apic_mmio_read(struct kvm_io_device *this,
 530                            gpa_t address, int len, void *data)
 531 {
 532         struct kvm_lapic *apic = to_lapic(this);
 533         unsigned int offset = address - apic->base_address;
 534         unsigned char alignment = offset & 0xf;
 535         u32 result;
 536
 537         if ((alignment + len) > 4) {
 538                 printk(KERN_ERR "KVM_APIC_READ: alignment error %lx %d",
 539                        (unsigned long)address, len);
 540                 return;
 541         }
 542         result = __apic_read(apic, offset & ~0xf);
 543
 544         switch (len) {
 545         case 1:
 546         case 2:
 547         case 4:
 548                 memcpy(data, (char *)&result + alignment, len);
 549                 break;
 550         default:
 551                 printk(KERN_ERR "Local APIC read with len = %x, "
 552                        "should be 1,2, or 4 instead\n", len);
 553                 break;
 554         }
 555 }
 556
 557 static void update_divide_count(struct kvm_lapic *apic)
 558 {
 559         u32 tmp1, tmp2, tdcr;
 560
 561         tdcr = apic_get_reg(apic, APIC_TDCR);
 562         tmp1 = tdcr & 0xf;
 563         tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
 564         apic->divide_count = 0x1 << (tmp2 & 0x7);
 565
 566         apic_debug("timer divide count is 0x%x\n",
 567                                    apic->divide_count);
 568 }
 569
 570 static void start_apic_timer(struct kvm_lapic *apic)
 571 {
 572         ktime_t now = apic->lapic_timer.timer.base->get_time();
 573
 574         apic->lapic_timer.period = apic_get_reg(apic, APIC_TMICT) *
 575                     APIC_BUS_CYCLE_NS * apic->divide_count;
 576         atomic_set(&apic->lapic_timer.pending, 0);
 577
 578         if (!apic->lapic_timer.period)
 579                 return;
 580
 581         hrtimer_start(&apic->lapic_timer.timer,
 582                       ktime_add_ns(now, apic->lapic_timer.period),
 583                       HRTIMER_MODE_ABS);
 584
 585         apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
 586                            PRIx64 ", "
 587                            "timer initial count 0x%x, period %lldns, "
 588                            "expire @ 0x%016" PRIx64 ".\n", __func__,
 589                            APIC_BUS_CYCLE_NS, ktime_to_ns(now),
 590                            apic_get_reg(apic, APIC_TMICT),
 591                            apic->lapic_timer.period,
 592                            ktime_to_ns(ktime_add_ns(now,
 593                                         apic->lapic_timer.period)));
 594 }
 595
 596 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
 597 {
 598         int nmi_wd_enabled = apic_lvt_nmi_mode(apic_get_reg(apic, APIC_LVT0));
 599
 600         if (apic_lvt_nmi_mode(lvt0_val)) {
 601                 if (!nmi_wd_enabled) {
 602                         apic_debug("Receive NMI setting on APIC_LVT0 "
 603                                    "for cpu %d\n", apic->vcpu->vcpu_id);
 604                         apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
 605                 }
 606         } else if (nmi_wd_enabled)
 607                 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
 608 }
 609
 610 static void apic_mmio_write(struct kvm_io_device *this,
 611                             gpa_t address, int len, const void *data)
 612 {
 613         struct kvm_lapic *apic = to_lapic(this);
 614         unsigned int offset = address - apic->base_address;
 615         unsigned char alignment = offset & 0xf;
 616         u32 val;
 617
 618         /*
 619          * APIC register must be aligned on 128-bits boundary.
 620          * 32/64/128 bits registers must be accessed thru 32 bits.
 621          * Refer SDM 8.4.1
 622          */
 623         if (len != 4 || alignment) {
 624                 /* Don't shout loud, $infamous_os would cause only noise. */
 625                 apic_debug("apic write: bad size=%d %lx\n",
 626                            len, (long)address);
 627                 return;
 628         }
 629
 630         val = *(u32 *) data;
 631
 632         /* too common printing */
 633         if (offset != APIC_EOI)
 634                 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
 635                            "0x%x\n", __func__, offset, len, val);
 636
 637         offset &= 0xff0;
 638
 639         KVMTRACE_1D(APIC_ACCESS, apic->vcpu, (u32)offset, handler);
 640
 641         switch (offset) {
 642         case APIC_ID:           /* Local APIC ID */
 643                 apic_set_reg(apic, APIC_ID, val);
 644                 break;
 645
 646         case APIC_TASKPRI:
 647                 report_tpr_access(apic, true);
 648                 apic_set_tpr(apic, val & 0xff);
 649                 break;
 650
 651         case APIC_EOI:
 652                 apic_set_eoi(apic);
 653                 break;
 654
 655         case APIC_LDR:
 656                 apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK);
 657                 break;
 658
 659         case APIC_DFR:
 660                 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
 661                 break;
 662
 663         case APIC_SPIV:
 664                 apic_set_reg(apic, APIC_SPIV, val & 0x3ff);
 665                 if (!(val & APIC_SPIV_APIC_ENABLED)) {
 666                         int i;
 667                         u32 lvt_val;
 668
 669                         for (i = 0; i < APIC_LVT_NUM; i++) {
 670                                 lvt_val = apic_get_reg(apic,
 671                                                        APIC_LVTT + 0x10 * i);
 672                                 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
 673                                              lvt_val | APIC_LVT_MASKED);
 674                         }
 675                         atomic_set(&apic->lapic_timer.pending, 0);
 676
 677                 }
 678                 break;
 679
 680         case APIC_ICR:
 681                 /* No delay here, so we always clear the pending bit */
 682                 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
 683                 apic_send_ipi(apic);
 684                 break;
 685
 686         case APIC_ICR2:
 687                 apic_set_reg(apic, APIC_ICR2, val & 0xff000000);
 688                 break;
 689
 690         case APIC_LVT0:
 691                 apic_manage_nmi_watchdog(apic, val);
 692         case APIC_LVTT:
 693         case APIC_LVTTHMR:
 694         case APIC_LVTPC:
 695         case APIC_LVT1:
 696         case APIC_LVTERR:
 697                 /* TODO: Check vector */
 698                 if (!apic_sw_enabled(apic))
 699                         val |= APIC_LVT_MASKED;
 700
 701                 val &= apic_lvt_mask[(offset - APIC_LVTT) >> 4];
 702                 apic_set_reg(apic, offset, val);
 703
 704                 break;
 705
 706         case APIC_TMICT:
 707                 hrtimer_cancel(&apic->lapic_timer.timer);
 708                 apic_set_reg(apic, APIC_TMICT, val);
 709                 start_apic_timer(apic);
 710                 return;
 711
 712         case APIC_TDCR:
 713                 if (val & 4)
 714                         printk(KERN_ERR "KVM_WRITE:TDCR %x\n", val);
 715                 apic_set_reg(apic, APIC_TDCR, val);
 716                 update_divide_count(apic);
 717                 break;
 718
 719         default:
 720                 apic_debug("Local APIC Write to read-only register %x\n",
 721                            offset);
 722                 break;
 723         }
 724
 725 }
 726
 727 static int apic_mmio_range(struct kvm_io_device *this, gpa_t addr,
 728                            int len, int size)
 729 {
 730         struct kvm_lapic *apic = to_lapic(this);
 731         int ret = 0;
 732
 733
 734         if (apic_hw_enabled(apic) &&
 735             (addr >= apic->base_address) &&
 736             (addr < (apic->base_address + LAPIC_MMIO_LENGTH)))
 737                 ret = 1;
 738
 739         return ret;
 740 }
 741
 742 void kvm_free_lapic(struct kvm_vcpu *vcpu)
 743 {
 744         if (!vcpu->arch.apic)
 745                 return;
 746
 747         hrtimer_cancel(&vcpu->arch.apic->lapic_timer.timer);
 748
 749         if (vcpu->arch.apic->regs_page)
 750                 __free_page(vcpu->arch.apic->regs_page);
 751
 752         kfree(vcpu->arch.apic);
 753 }
 754
 755 /*
 756  *----------------------------------------------------------------------
 757  * LAPIC interface
 758  *----------------------------------------------------------------------
 759  */
 760
 761 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
 762 {
 763         struct kvm_lapic *apic = vcpu->arch.apic;
 764
 765         if (!apic)
 766                 return;
 767         apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
 768                      | (apic_get_reg(apic, APIC_TASKPRI) & 4));
 769 }
 770
 771 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
 772 {
 773         struct kvm_lapic *apic = vcpu->arch.apic;
 774         u64 tpr;
 775
 776         if (!apic)
 777                 return 0;
 778         tpr = (u64) apic_get_reg(apic, APIC_TASKPRI);
 779
 780         return (tpr & 0xf0) >> 4;
 781 }
 782
 783 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
 784 {
 785         struct kvm_lapic *apic = vcpu->arch.apic;
 786
 787         if (!apic) {
 788                 value |= MSR_IA32_APICBASE_BSP;
 789                 vcpu->arch.apic_base = value;
 790                 return;
 791         }
 792         if (apic->vcpu->vcpu_id)
 793                 value &= ~MSR_IA32_APICBASE_BSP;
 794
 795         vcpu->arch.apic_base = value;
 796         apic->base_address = apic->vcpu->arch.apic_base &
 797                              MSR_IA32_APICBASE_BASE;
 798
 799         /* with FSB delivery interrupt, we can restart APIC functionality */
 800         apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
 801                    "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
 802
 803 }
 804
 805 void kvm_lapic_reset(struct kvm_vcpu *vcpu)
 806 {
 807         struct kvm_lapic *apic;
 808         int i;
 809
 810         apic_debug("%s\n", __func__);
 811
 812         ASSERT(vcpu);
 813         apic = vcpu->arch.apic;
 814         ASSERT(apic != NULL);
 815
 816         /* Stop the timer in case it's a reset to an active apic */
 817         hrtimer_cancel(&apic->lapic_timer.timer);
 818
 819         apic_set_reg(apic, APIC_ID, vcpu->vcpu_id << 24);
 820         apic_set_reg(apic, APIC_LVR, APIC_VERSION);
 821
 822         for (i = 0; i < APIC_LVT_NUM; i++)
 823                 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
 824         apic_set_reg(apic, APIC_LVT0,
 825                      SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
 826
 827         apic_set_reg(apic, APIC_DFR, 0xffffffffU);
 828         apic_set_reg(apic, APIC_SPIV, 0xff);
 829         apic_set_reg(apic, APIC_TASKPRI, 0);
 830         apic_set_reg(apic, APIC_LDR, 0);
 831         apic_set_reg(apic, APIC_ESR, 0);
 832         apic_set_reg(apic, APIC_ICR, 0);
 833         apic_set_reg(apic, APIC_ICR2, 0);
 834         apic_set_reg(apic, APIC_TDCR, 0);
 835         apic_set_reg(apic, APIC_TMICT, 0);
 836         for (i = 0; i < 8; i++) {
 837                 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
 838                 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
 839                 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
 840         }
 841         update_divide_count(apic);
 842         atomic_set(&apic->lapic_timer.pending, 0);
 843         if (vcpu->vcpu_id == 0)
 844                 vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP;
 845         apic_update_ppr(apic);
 846
 847         vcpu->arch.apic_arb_prio = 0;
 848
 849         apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr="
 850                    "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
 851                    vcpu, kvm_apic_id(apic),
 852                    vcpu->arch.apic_base, apic->base_address);
 853 }
 854
 855 bool kvm_apic_present(struct kvm_vcpu *vcpu)
 856 {
 857         return vcpu->arch.apic && apic_hw_enabled(vcpu->arch.apic);
 858 }
 859
 860 int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
 861 {
 862         return kvm_apic_present(vcpu) && apic_sw_enabled(vcpu->arch.apic);
 863 }
 864
 865 /*
 866  *----------------------------------------------------------------------
 867  * timer interface
 868  *----------------------------------------------------------------------
 869  */
 870
 871 static bool lapic_is_periodic(struct kvm_timer *ktimer)
 872 {
 873         struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic,
 874                                               lapic_timer);
 875         return apic_lvtt_period(apic);
 876 }
 877
 878 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
 879 {
 880         struct kvm_lapic *lapic = vcpu->arch.apic;
 881
 882         if (lapic && apic_enabled(lapic) && apic_lvt_enabled(lapic, APIC_LVTT))
 883                 return atomic_read(&lapic->lapic_timer.pending);
 884
 885         return 0;
 886 }
 887
 888 static int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
 889 {
 890         u32 reg = apic_get_reg(apic, lvt_type);
 891         int vector, mode, trig_mode;
 892
 893         if (apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
 894                 vector = reg & APIC_VECTOR_MASK;
 895                 mode = reg & APIC_MODE_MASK;
 896                 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
 897                 return __apic_accept_irq(apic, mode, vector, 1, trig_mode);
 898         }
 899         return 0;
 900 }
 901
 902 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
 903 {
 904         struct kvm_lapic *apic = vcpu->arch.apic;
 905
 906         if (apic)
 907                 kvm_apic_local_deliver(apic, APIC_LVT0);
 908 }
 909
 910 static struct kvm_timer_ops lapic_timer_ops = {
 911         .is_periodic = lapic_is_periodic,
 912 };
 913
 914 static const struct kvm_io_device_ops apic_mmio_ops = {
 915         .read     = apic_mmio_read,
 916         .write    = apic_mmio_write,
 917         .in_range = apic_mmio_range,
 918 };
 919
 920 int kvm_create_lapic(struct kvm_vcpu *vcpu)
 921 {
 922         struct kvm_lapic *apic;
 923
 924         ASSERT(vcpu != NULL);
 925         apic_debug("apic_init %d\n", vcpu->vcpu_id);
 926
 927         apic = kzalloc(sizeof(*apic), GFP_KERNEL);
 928         if (!apic)
 929                 goto nomem;
 930
 931         vcpu->arch.apic = apic;
 932
 933         apic->regs_page = alloc_page(GFP_KERNEL);
 934         if (apic->regs_page == NULL) {
 935                 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
 936                        vcpu->vcpu_id);
 937                 goto nomem_free_apic;
 938         }
 939         apic->regs = page_address(apic->regs_page);
 940         memset(apic->regs, 0, PAGE_SIZE);
 941         apic->vcpu = vcpu;
 942
 943         hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
 944                      HRTIMER_MODE_ABS);
 945         apic->lapic_timer.timer.function = kvm_timer_fn;
 946         apic->lapic_timer.t_ops = &lapic_timer_ops;
 947         apic->lapic_timer.kvm = vcpu->kvm;
 948         apic->lapic_timer.vcpu_id = vcpu->vcpu_id;
 949
 950         apic->base_address = APIC_DEFAULT_PHYS_BASE;
 951         vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE;
 952
 953         kvm_lapic_reset(vcpu);
 954         kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
 955
 956         return 0;
 957 nomem_free_apic:
 958         kfree(apic);
 959 nomem:
 960         return -ENOMEM;
 961 }
 962
 963 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
 964 {
 965         struct kvm_lapic *apic = vcpu->arch.apic;
 966         int highest_irr;
 967
 968         if (!apic || !apic_enabled(apic))
 969                 return -1;
 970
 971         apic_update_ppr(apic);
 972         highest_irr = apic_find_highest_irr(apic);
 973         if ((highest_irr == -1) ||
 974             ((highest_irr & 0xF0) <= apic_get_reg(apic, APIC_PROCPRI)))
 975                 return -1;
 976         return highest_irr;
 977 }
 978
 979 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
 980 {
 981         u32 lvt0 = apic_get_reg(vcpu->arch.apic, APIC_LVT0);
 982         int r = 0;
 983
 984         if (vcpu->vcpu_id == 0) {
 985                 if (!apic_hw_enabled(vcpu->arch.apic))
 986                         r = 1;
 987                 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
 988                     GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
 989                         r = 1;
 990         }
 991         return r;
 992 }
 993
 994 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
 995 {
 996         struct kvm_lapic *apic = vcpu->arch.apic;
 997
 998         if (apic && atomic_read(&apic->lapic_timer.pending) > 0) {
 999                 if (kvm_apic_local_deliver(apic, APIC_LVTT))
1000                         atomic_dec(&apic->lapic_timer.pending);
1001         }
1002 }
1003
1004 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1005 {
1006         int vector = kvm_apic_has_interrupt(vcpu);
1007         struct kvm_lapic *apic = vcpu->arch.apic;
1008
1009         if (vector == -1)
1010                 return -1;
1011
1012         apic_set_vector(vector, apic->regs + APIC_ISR);
1013         apic_update_ppr(apic);
1014         apic_clear_irr(vector, apic);
1015         return vector;
1016 }
1017
1018 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu)
1019 {
1020         struct kvm_lapic *apic = vcpu->arch.apic;
1021
1022         apic->base_address = vcpu->arch.apic_base &
1023                              MSR_IA32_APICBASE_BASE;
1024         apic_set_reg(apic, APIC_LVR, APIC_VERSION);
1025         apic_update_ppr(apic);
1026         hrtimer_cancel(&apic->lapic_timer.timer);
1027         update_divide_count(apic);
1028         start_apic_timer(apic);
1029 }
1030
1031 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1032 {
1033         struct kvm_lapic *apic = vcpu->arch.apic;
1034         struct hrtimer *timer;
1035
1036         if (!apic)
1037                 return;
1038
1039         timer = &apic->lapic_timer.timer;
1040         if (hrtimer_cancel(timer))
1041                 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
1042 }
1043
1044 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1045 {
1046         u32 data;
1047         void *vapic;
1048
1049         if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1050                 return;
1051
1052         vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1053         data = *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr));
1054         kunmap_atomic(vapic, KM_USER0);
1055
1056         apic_set_tpr(vcpu->arch.apic, data & 0xff);
1057 }
1058
1059 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1060 {
1061         u32 data, tpr;
1062         int max_irr, max_isr;
1063         struct kvm_lapic *apic;
1064         void *vapic;
1065
1066         if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1067                 return;
1068
1069         apic = vcpu->arch.apic;
1070         tpr = apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1071         max_irr = apic_find_highest_irr(apic);
1072         if (max_irr < 0)
1073                 max_irr = 0;
1074         max_isr = apic_find_highest_isr(apic);
1075         if (max_isr < 0)
1076                 max_isr = 0;
1077         data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1078
1079         vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1080         *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)) = data;
1081         kunmap_atomic(vapic, KM_USER0);
1082 }
1083
1084 void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1085 {
1086         if (!irqchip_in_kernel(vcpu->kvm))
1087                 return;
1088
1089         vcpu->arch.apic->vapic_addr = vapic_addr;
1090 }