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   1
   2 /*
   3  * Local APIC virtualization
   4  *
   5  * Copyright (C) 2006 Qumranet, Inc.
   6  * Copyright (C) 2007 Novell
   7  * Copyright (C) 2007 Intel
   8  *
   9  * Authors:
  10  *   Dor Laor <dor.laor@qumranet.com>
  11  *   Gregory Haskins <ghaskins@novell.com>
  12  *   Yaozu (Eddie) Dong <eddie.dong@intel.com>
  13  *
  14  * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
  15  *
  16  * This work is licensed under the terms of the GNU GPL, version 2.  See
  17  * the COPYING file in the top-level directory.
  18  */
  19
  20 #include <linux/kvm_host.h>
  21 #include <linux/kvm.h>
  22 #include <linux/mm.h>
  23 #include <linux/highmem.h>
  24 #include <linux/smp.h>
  25 #include <linux/hrtimer.h>
  26 #include <linux/io.h>
  27 #include <linux/module.h>
  28 #include <linux/math64.h>
  29 #include <asm/processor.h>
  30 #include <asm/msr.h>
  31 #include <asm/page.h>
  32 #include <asm/current.h>
  33 #include <asm/apicdef.h>
  34 #include <asm/atomic.h>
  35 #include "kvm_cache_regs.h"
  36 #include "irq.h"
  37
  38 #define PRId64 "d"
  39 #define PRIx64 "llx"
  40 #define PRIu64 "u"
  41 #define PRIo64 "o"
  42
  43 #define APIC_BUS_CYCLE_NS 1
  44
  45 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
  46 #define apic_debug(fmt, arg...)
  47
  48 #define APIC_LVT_NUM                    6
  49 /* 14 is the version for Xeon and Pentium 8.4.8*/
  50 #define APIC_VERSION                    (0x14UL | ((APIC_LVT_NUM - 1) << 16))
  51 #define LAPIC_MMIO_LENGTH               (1 << 12)
  52 /* followed define is not in apicdef.h */
  53 #define APIC_SHORT_MASK                 0xc0000
  54 #define APIC_DEST_NOSHORT               0x0
  55 #define APIC_DEST_MASK                  0x800
  56 #define MAX_APIC_VECTOR                 256
  57
  58 #define VEC_POS(v) ((v) & (32 - 1))
  59 #define REG_POS(v) (((v) >> 5) << 4)
  60
  61 static inline u32 apic_get_reg(struct kvm_lapic *apic, int reg_off)
  62 {
  63         return *((u32 *) (apic->regs + reg_off));
  64 }
  65
  66 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
  67 {
  68         *((u32 *) (apic->regs + reg_off)) = val;
  69 }
  70
  71 static inline int apic_test_and_set_vector(int vec, void *bitmap)
  72 {
  73         return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  74 }
  75
  76 static inline int apic_test_and_clear_vector(int vec, void *bitmap)
  77 {
  78         return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  79 }
  80
  81 static inline void apic_set_vector(int vec, void *bitmap)
  82 {
  83         set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  84 }
  85
  86 static inline void apic_clear_vector(int vec, void *bitmap)
  87 {
  88         clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  89 }
  90
  91 static inline int apic_hw_enabled(struct kvm_lapic *apic)
  92 {
  93         return (apic)->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
  94 }
  95
  96 static inline int  apic_sw_enabled(struct kvm_lapic *apic)
  97 {
  98         return apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED;
  99 }
 100
 101 static inline int apic_enabled(struct kvm_lapic *apic)
 102 {
 103         return apic_sw_enabled(apic) && apic_hw_enabled(apic);
 104 }
 105
 106 #define LVT_MASK        \
 107         (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
 108
 109 #define LINT_MASK       \
 110         (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
 111          APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
 112
 113 static inline int kvm_apic_id(struct kvm_lapic *apic)
 114 {
 115         return (apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
 116 }
 117
 118 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
 119 {
 120         return !(apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
 121 }
 122
 123 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
 124 {
 125         return apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
 126 }
 127
 128 static inline int apic_lvtt_period(struct kvm_lapic *apic)
 129 {
 130         return apic_get_reg(apic, APIC_LVTT) & APIC_LVT_TIMER_PERIODIC;
 131 }
 132
 133 static unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
 134         LVT_MASK | APIC_LVT_TIMER_PERIODIC,     /* LVTT */
 135         LVT_MASK | APIC_MODE_MASK,      /* LVTTHMR */
 136         LVT_MASK | APIC_MODE_MASK,      /* LVTPC */
 137         LINT_MASK, LINT_MASK,   /* LVT0-1 */
 138         LVT_MASK                /* LVTERR */
 139 };
 140
 141 static int find_highest_vector(void *bitmap)
 142 {
 143         u32 *word = bitmap;
 144         int word_offset = MAX_APIC_VECTOR >> 5;
 145
 146         while ((word_offset != 0) && (word[(--word_offset) << 2] == 0))
 147                 continue;
 148
 149         if (likely(!word_offset && !word[0]))
 150                 return -1;
 151         else
 152                 return fls(word[word_offset << 2]) - 1 + (word_offset << 5);
 153 }
 154
 155 static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic)
 156 {
 157         return apic_test_and_set_vector(vec, apic->regs + APIC_IRR);
 158 }
 159
 160 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
 161 {
 162         apic_clear_vector(vec, apic->regs + APIC_IRR);
 163 }
 164
 165 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
 166 {
 167         int result;
 168
 169         result = find_highest_vector(apic->regs + APIC_IRR);
 170         ASSERT(result == -1 || result >= 16);
 171
 172         return result;
 173 }
 174
 175 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
 176 {
 177         struct kvm_lapic *apic = vcpu->arch.apic;
 178         int highest_irr;
 179
 180         if (!apic)
 181                 return 0;
 182         highest_irr = apic_find_highest_irr(apic);
 183
 184         return highest_irr;
 185 }
 186 EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr);
 187
 188 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, u8 vec, u8 trig)
 189 {
 190         struct kvm_lapic *apic = vcpu->arch.apic;
 191
 192         if (!apic_test_and_set_irr(vec, apic)) {
 193                 /* a new pending irq is set in IRR */
 194                 if (trig)
 195                         apic_set_vector(vec, apic->regs + APIC_TMR);
 196                 else
 197                         apic_clear_vector(vec, apic->regs + APIC_TMR);
 198                 kvm_vcpu_kick(apic->vcpu);
 199                 return 1;
 200         }
 201         return 0;
 202 }
 203
 204 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
 205 {
 206         int result;
 207
 208         result = find_highest_vector(apic->regs + APIC_ISR);
 209         ASSERT(result == -1 || result >= 16);
 210
 211         return result;
 212 }
 213
 214 static void apic_update_ppr(struct kvm_lapic *apic)
 215 {
 216         u32 tpr, isrv, ppr;
 217         int isr;
 218
 219         tpr = apic_get_reg(apic, APIC_TASKPRI);
 220         isr = apic_find_highest_isr(apic);
 221         isrv = (isr != -1) ? isr : 0;
 222
 223         if ((tpr & 0xf0) >= (isrv & 0xf0))
 224                 ppr = tpr & 0xff;
 225         else
 226                 ppr = isrv & 0xf0;
 227
 228         apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
 229                    apic, ppr, isr, isrv);
 230
 231         apic_set_reg(apic, APIC_PROCPRI, ppr);
 232 }
 233
 234 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
 235 {
 236         apic_set_reg(apic, APIC_TASKPRI, tpr);
 237         apic_update_ppr(apic);
 238 }
 239
 240 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest)
 241 {
 242         return kvm_apic_id(apic) == dest;
 243 }
 244
 245 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
 246 {
 247         int result = 0;
 248         u8 logical_id;
 249
 250         logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR));
 251
 252         switch (apic_get_reg(apic, APIC_DFR)) {
 253         case APIC_DFR_FLAT:
 254                 if (logical_id & mda)
 255                         result = 1;
 256                 break;
 257         case APIC_DFR_CLUSTER:
 258                 if (((logical_id >> 4) == (mda >> 0x4))
 259                     && (logical_id & mda & 0xf))
 260                         result = 1;
 261                 break;
 262         default:
 263                 printk(KERN_WARNING "Bad DFR vcpu %d: %08x\n",
 264                        apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR));
 265                 break;
 266         }
 267
 268         return result;
 269 }
 270
 271 static int apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
 272                            int short_hand, int dest, int dest_mode)
 273 {
 274         int result = 0;
 275         struct kvm_lapic *target = vcpu->arch.apic;
 276
 277         apic_debug("target %p, source %p, dest 0x%x, "
 278                    "dest_mode 0x%x, short_hand 0x%x",
 279                    target, source, dest, dest_mode, short_hand);
 280
 281         ASSERT(!target);
 282         switch (short_hand) {
 283         case APIC_DEST_NOSHORT:
 284                 if (dest_mode == 0) {
 285                         /* Physical mode. */
 286                         if ((dest == 0xFF) || (dest == kvm_apic_id(target)))
 287                                 result = 1;
 288                 } else
 289                         /* Logical mode. */
 290                         result = kvm_apic_match_logical_addr(target, dest);
 291                 break;
 292         case APIC_DEST_SELF:
 293                 if (target == source)
 294                         result = 1;
 295                 break;
 296         case APIC_DEST_ALLINC:
 297                 result = 1;
 298                 break;
 299         case APIC_DEST_ALLBUT:
 300                 if (target != source)
 301                         result = 1;
 302                 break;
 303         default:
 304                 printk(KERN_WARNING "Bad dest shorthand value %x\n",
 305                        short_hand);
 306                 break;
 307         }
 308
 309         return result;
 310 }
 311
 312 /*
 313  * Add a pending IRQ into lapic.
 314  * Return 1 if successfully added and 0 if discarded.
 315  */
 316 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 317                              int vector, int level, int trig_mode)
 318 {
 319         int orig_irr, result = 0;
 320         struct kvm_vcpu *vcpu = apic->vcpu;
 321
 322         switch (delivery_mode) {
 323         case APIC_DM_FIXED:
 324         case APIC_DM_LOWEST:
 325                 /* FIXME add logic for vcpu on reset */
 326                 if (unlikely(!apic_enabled(apic)))
 327                         break;
 328
 329                 orig_irr = apic_test_and_set_irr(vector, apic);
 330                 if (orig_irr && trig_mode) {
 331                         apic_debug("level trig mode repeatedly for vector %d",
 332                                    vector);
 333                         break;
 334                 }
 335
 336                 if (trig_mode) {
 337                         apic_debug("level trig mode for vector %d", vector);
 338                         apic_set_vector(vector, apic->regs + APIC_TMR);
 339                 } else
 340                         apic_clear_vector(vector, apic->regs + APIC_TMR);
 341
 342                 kvm_vcpu_kick(vcpu);
 343
 344                 result = (orig_irr == 0);
 345                 break;
 346
 347         case APIC_DM_REMRD:
 348                 printk(KERN_DEBUG "Ignoring delivery mode 3\n");
 349                 break;
 350
 351         case APIC_DM_SMI:
 352                 printk(KERN_DEBUG "Ignoring guest SMI\n");
 353                 break;
 354
 355         case APIC_DM_NMI:
 356                 kvm_inject_nmi(vcpu);
 357                 break;
 358
 359         case APIC_DM_INIT:
 360                 if (level) {
 361                         if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
 362                                 printk(KERN_DEBUG
 363                                        "INIT on a runnable vcpu %d\n",
 364                                        vcpu->vcpu_id);
 365                         vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
 366                         kvm_vcpu_kick(vcpu);
 367                 } else {
 368                         printk(KERN_DEBUG
 369                                "Ignoring de-assert INIT to vcpu %d\n",
 370                                vcpu->vcpu_id);
 371                 }
 372
 373                 break;
 374
 375         case APIC_DM_STARTUP:
 376                 printk(KERN_DEBUG "SIPI to vcpu %d vector 0x%02x\n",
 377                        vcpu->vcpu_id, vector);
 378                 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
 379                         vcpu->arch.sipi_vector = vector;
 380                         vcpu->arch.mp_state = KVM_MP_STATE_SIPI_RECEIVED;
 381                         kvm_vcpu_kick(vcpu);
 382                 }
 383                 break;
 384
 385         default:
 386                 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
 387                        delivery_mode);
 388                 break;
 389         }
 390         return result;
 391 }
 392
 393 static struct kvm_lapic *kvm_apic_round_robin(struct kvm *kvm, u8 vector,
 394                                        unsigned long bitmap)
 395 {
 396         int last;
 397         int next;
 398         struct kvm_lapic *apic = NULL;
 399
 400         last = kvm->arch.round_robin_prev_vcpu;
 401         next = last;
 402
 403         do {
 404                 if (++next == KVM_MAX_VCPUS)
 405                         next = 0;
 406                 if (kvm->vcpus[next] == NULL || !test_bit(next, &bitmap))
 407                         continue;
 408                 apic = kvm->vcpus[next]->arch.apic;
 409                 if (apic && apic_enabled(apic))
 410                         break;
 411                 apic = NULL;
 412         } while (next != last);
 413         kvm->arch.round_robin_prev_vcpu = next;
 414
 415         if (!apic)
 416                 printk(KERN_DEBUG "vcpu not ready for apic_round_robin\n");
 417
 418         return apic;
 419 }
 420
 421 struct kvm_vcpu *kvm_get_lowest_prio_vcpu(struct kvm *kvm, u8 vector,
 422                 unsigned long bitmap)
 423 {
 424         struct kvm_lapic *apic;
 425
 426         apic = kvm_apic_round_robin(kvm, vector, bitmap);
 427         if (apic)
 428                 return apic->vcpu;
 429         return NULL;
 430 }
 431
 432 static void apic_set_eoi(struct kvm_lapic *apic)
 433 {
 434         int vector = apic_find_highest_isr(apic);
 435         int trigger_mode;
 436         /*
 437          * Not every write EOI will has corresponding ISR,
 438          * one example is when Kernel check timer on setup_IO_APIC
 439          */
 440         if (vector == -1)
 441                 return;
 442
 443         apic_clear_vector(vector, apic->regs + APIC_ISR);
 444         apic_update_ppr(apic);
 445
 446         if (apic_test_and_clear_vector(vector, apic->regs + APIC_TMR))
 447                 trigger_mode = IOAPIC_LEVEL_TRIG;
 448         else
 449                 trigger_mode = IOAPIC_EDGE_TRIG;
 450         kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode);
 451 }
 452
 453 static void apic_send_ipi(struct kvm_lapic *apic)
 454 {
 455         u32 icr_low = apic_get_reg(apic, APIC_ICR);
 456         u32 icr_high = apic_get_reg(apic, APIC_ICR2);
 457
 458         unsigned int dest = GET_APIC_DEST_FIELD(icr_high);
 459         unsigned int short_hand = icr_low & APIC_SHORT_MASK;
 460         unsigned int trig_mode = icr_low & APIC_INT_LEVELTRIG;
 461         unsigned int level = icr_low & APIC_INT_ASSERT;
 462         unsigned int dest_mode = icr_low & APIC_DEST_MASK;
 463         unsigned int delivery_mode = icr_low & APIC_MODE_MASK;
 464         unsigned int vector = icr_low & APIC_VECTOR_MASK;
 465
 466         struct kvm_vcpu *target;
 467         struct kvm_vcpu *vcpu;
 468         unsigned long lpr_map = 0;
 469         int i;
 470
 471         apic_debug("icr_high 0x%x, icr_low 0x%x, "
 472                    "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
 473                    "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
 474                    icr_high, icr_low, short_hand, dest,
 475                    trig_mode, level, dest_mode, delivery_mode, vector);
 476
 477         for (i = 0; i < KVM_MAX_VCPUS; i++) {
 478                 vcpu = apic->vcpu->kvm->vcpus[i];
 479                 if (!vcpu)
 480                         continue;
 481
 482                 if (vcpu->arch.apic &&
 483                     apic_match_dest(vcpu, apic, short_hand, dest, dest_mode)) {
 484                         if (delivery_mode == APIC_DM_LOWEST)
 485                                 set_bit(vcpu->vcpu_id, &lpr_map);
 486                         else
 487                                 __apic_accept_irq(vcpu->arch.apic, delivery_mode,
 488                                                   vector, level, trig_mode);
 489                 }
 490         }
 491
 492         if (delivery_mode == APIC_DM_LOWEST) {
 493                 target = kvm_get_lowest_prio_vcpu(vcpu->kvm, vector, lpr_map);
 494                 if (target != NULL)
 495                         __apic_accept_irq(target->arch.apic, delivery_mode,
 496                                           vector, level, trig_mode);
 497         }
 498 }
 499
 500 static u32 apic_get_tmcct(struct kvm_lapic *apic)
 501 {
 502         u64 counter_passed;
 503         ktime_t passed, now;
 504         u32 tmcct;
 505
 506         ASSERT(apic != NULL);
 507
 508         now = apic->timer.dev.base->get_time();
 509         tmcct = apic_get_reg(apic, APIC_TMICT);
 510
 511         /* if initial count is 0, current count should also be 0 */
 512         if (tmcct == 0)
 513                 return 0;
 514
 515         if (unlikely(ktime_to_ns(now) <=
 516                 ktime_to_ns(apic->timer.last_update))) {
 517                 /* Wrap around */
 518                 passed = ktime_add(( {
 519                                     (ktime_t) {
 520                                     .tv64 = KTIME_MAX -
 521                                     (apic->timer.last_update).tv64}; }
 522                                    ), now);
 523                 apic_debug("time elapsed\n");
 524         } else
 525                 passed = ktime_sub(now, apic->timer.last_update);
 526
 527         counter_passed = div64_u64(ktime_to_ns(passed),
 528                                    (APIC_BUS_CYCLE_NS * apic->timer.divide_count));
 529
 530         if (counter_passed > tmcct) {
 531                 if (unlikely(!apic_lvtt_period(apic))) {
 532                         /* one-shot timers stick at 0 until reset */
 533                         tmcct = 0;
 534                 } else {
 535                         /*
 536                          * periodic timers reset to APIC_TMICT when they
 537                          * hit 0. The while loop simulates this happening N
 538                          * times. (counter_passed %= tmcct) would also work,
 539                          * but might be slower or not work on 32-bit??
 540                          */
 541                         while (counter_passed > tmcct)
 542                                 counter_passed -= tmcct;
 543                         tmcct -= counter_passed;
 544                 }
 545         } else {
 546                 tmcct -= counter_passed;
 547         }
 548
 549         return tmcct;
 550 }
 551
 552 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
 553 {
 554         struct kvm_vcpu *vcpu = apic->vcpu;
 555         struct kvm_run *run = vcpu->run;
 556
 557         set_bit(KVM_REQ_REPORT_TPR_ACCESS, &vcpu->requests);
 558         run->tpr_access.rip = kvm_rip_read(vcpu);
 559         run->tpr_access.is_write = write;
 560 }
 561
 562 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
 563 {
 564         if (apic->vcpu->arch.tpr_access_reporting)
 565                 __report_tpr_access(apic, write);
 566 }
 567
 568 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
 569 {
 570         u32 val = 0;
 571
 572         KVMTRACE_1D(APIC_ACCESS, apic->vcpu, (u32)offset, handler);
 573
 574         if (offset >= LAPIC_MMIO_LENGTH)
 575                 return 0;
 576
 577         switch (offset) {
 578         case APIC_ARBPRI:
 579                 printk(KERN_WARNING "Access APIC ARBPRI register "
 580                        "which is for P6\n");
 581                 break;
 582
 583         case APIC_TMCCT:        /* Timer CCR */
 584                 val = apic_get_tmcct(apic);
 585                 break;
 586
 587         case APIC_TASKPRI:
 588                 report_tpr_access(apic, false);
 589                 /* fall thru */
 590         default:
 591                 apic_update_ppr(apic);
 592                 val = apic_get_reg(apic, offset);
 593                 break;
 594         }
 595
 596         return val;
 597 }
 598
 599 static void apic_mmio_read(struct kvm_io_device *this,
 600                            gpa_t address, int len, void *data)
 601 {
 602         struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
 603         unsigned int offset = address - apic->base_address;
 604         unsigned char alignment = offset & 0xf;
 605         u32 result;
 606
 607         if ((alignment + len) > 4) {
 608                 printk(KERN_ERR "KVM_APIC_READ: alignment error %lx %d",
 609                        (unsigned long)address, len);
 610                 return;
 611         }
 612         result = __apic_read(apic, offset & ~0xf);
 613
 614         switch (len) {
 615         case 1:
 616         case 2:
 617         case 4:
 618                 memcpy(data, (char *)&result + alignment, len);
 619                 break;
 620         default:
 621                 printk(KERN_ERR "Local APIC read with len = %x, "
 622                        "should be 1,2, or 4 instead\n", len);
 623                 break;
 624         }
 625 }
 626
 627 static void update_divide_count(struct kvm_lapic *apic)
 628 {
 629         u32 tmp1, tmp2, tdcr;
 630
 631         tdcr = apic_get_reg(apic, APIC_TDCR);
 632         tmp1 = tdcr & 0xf;
 633         tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
 634         apic->timer.divide_count = 0x1 << (tmp2 & 0x7);
 635
 636         apic_debug("timer divide count is 0x%x\n",
 637                                    apic->timer.divide_count);
 638 }
 639
 640 static void start_apic_timer(struct kvm_lapic *apic)
 641 {
 642         ktime_t now = apic->timer.dev.base->get_time();
 643
 644         apic->timer.last_update = now;
 645
 646         apic->timer.period = apic_get_reg(apic, APIC_TMICT) *
 647                     APIC_BUS_CYCLE_NS * apic->timer.divide_count;
 648         atomic_set(&apic->timer.pending, 0);
 649
 650         if (!apic->timer.period)
 651                 return;
 652
 653         hrtimer_start(&apic->timer.dev,
 654                       ktime_add_ns(now, apic->timer.period),
 655                       HRTIMER_MODE_ABS);
 656
 657         apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
 658                            PRIx64 ", "
 659                            "timer initial count 0x%x, period %lldns, "
 660                            "expire @ 0x%016" PRIx64 ".\n", __func__,
 661                            APIC_BUS_CYCLE_NS, ktime_to_ns(now),
 662                            apic_get_reg(apic, APIC_TMICT),
 663                            apic->timer.period,
 664                            ktime_to_ns(ktime_add_ns(now,
 665                                         apic->timer.period)));
 666 }
 667
 668 static void apic_mmio_write(struct kvm_io_device *this,
 669                             gpa_t address, int len, const void *data)
 670 {
 671         struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
 672         unsigned int offset = address - apic->base_address;
 673         unsigned char alignment = offset & 0xf;
 674         u32 val;
 675
 676         /*
 677          * APIC register must be aligned on 128-bits boundary.
 678          * 32/64/128 bits registers must be accessed thru 32 bits.
 679          * Refer SDM 8.4.1
 680          */
 681         if (len != 4 || alignment) {
 682                 if (printk_ratelimit())
 683                         printk(KERN_ERR "apic write: bad size=%d %lx\n",
 684                                len, (long)address);
 685                 return;
 686         }
 687
 688         val = *(u32 *) data;
 689
 690         /* too common printing */
 691         if (offset != APIC_EOI)
 692                 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
 693                            "0x%x\n", __func__, offset, len, val);
 694
 695         offset &= 0xff0;
 696
 697         KVMTRACE_1D(APIC_ACCESS, apic->vcpu, (u32)offset, handler);
 698
 699         switch (offset) {
 700         case APIC_ID:           /* Local APIC ID */
 701                 apic_set_reg(apic, APIC_ID, val);
 702                 break;
 703
 704         case APIC_TASKPRI:
 705                 report_tpr_access(apic, true);
 706                 apic_set_tpr(apic, val & 0xff);
 707                 break;
 708
 709         case APIC_EOI:
 710                 apic_set_eoi(apic);
 711                 break;
 712
 713         case APIC_LDR:
 714                 apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK);
 715                 break;
 716
 717         case APIC_DFR:
 718                 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
 719                 break;
 720
 721         case APIC_SPIV:
 722                 apic_set_reg(apic, APIC_SPIV, val & 0x3ff);
 723                 if (!(val & APIC_SPIV_APIC_ENABLED)) {
 724                         int i;
 725                         u32 lvt_val;
 726
 727                         for (i = 0; i < APIC_LVT_NUM; i++) {
 728                                 lvt_val = apic_get_reg(apic,
 729                                                        APIC_LVTT + 0x10 * i);
 730                                 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
 731                                              lvt_val | APIC_LVT_MASKED);
 732                         }
 733                         atomic_set(&apic->timer.pending, 0);
 734
 735                 }
 736                 break;
 737
 738         case APIC_ICR:
 739                 /* No delay here, so we always clear the pending bit */
 740                 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
 741                 apic_send_ipi(apic);
 742                 break;
 743
 744         case APIC_ICR2:
 745                 apic_set_reg(apic, APIC_ICR2, val & 0xff000000);
 746                 break;
 747
 748         case APIC_LVTT:
 749         case APIC_LVTTHMR:
 750         case APIC_LVTPC:
 751         case APIC_LVT0:
 752         case APIC_LVT1:
 753         case APIC_LVTERR:
 754                 /* TODO: Check vector */
 755                 if (!apic_sw_enabled(apic))
 756                         val |= APIC_LVT_MASKED;
 757
 758                 val &= apic_lvt_mask[(offset - APIC_LVTT) >> 4];
 759                 apic_set_reg(apic, offset, val);
 760
 761                 break;
 762
 763         case APIC_TMICT:
 764                 hrtimer_cancel(&apic->timer.dev);
 765                 apic_set_reg(apic, APIC_TMICT, val);
 766                 start_apic_timer(apic);
 767                 return;
 768
 769         case APIC_TDCR:
 770                 if (val & 4)
 771                         printk(KERN_ERR "KVM_WRITE:TDCR %x\n", val);
 772                 apic_set_reg(apic, APIC_TDCR, val);
 773                 update_divide_count(apic);
 774                 break;
 775
 776         default:
 777                 apic_debug("Local APIC Write to read-only register %x\n",
 778                            offset);
 779                 break;
 780         }
 781
 782 }
 783
 784 static int apic_mmio_range(struct kvm_io_device *this, gpa_t addr,
 785                            int len, int size)
 786 {
 787         struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
 788         int ret = 0;
 789
 790
 791         if (apic_hw_enabled(apic) &&
 792             (addr >= apic->base_address) &&
 793             (addr < (apic->base_address + LAPIC_MMIO_LENGTH)))
 794                 ret = 1;
 795
 796         return ret;
 797 }
 798
 799 void kvm_free_lapic(struct kvm_vcpu *vcpu)
 800 {
 801         if (!vcpu->arch.apic)
 802                 return;
 803
 804         hrtimer_cancel(&vcpu->arch.apic->timer.dev);
 805
 806         if (vcpu->arch.apic->regs_page)
 807                 __free_page(vcpu->arch.apic->regs_page);
 808
 809         kfree(vcpu->arch.apic);
 810 }
 811
 812 /*
 813  *----------------------------------------------------------------------
 814  * LAPIC interface
 815  *----------------------------------------------------------------------
 816  */
 817
 818 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
 819 {
 820         struct kvm_lapic *apic = vcpu->arch.apic;
 821
 822         if (!apic)
 823                 return;
 824         apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
 825                      | (apic_get_reg(apic, APIC_TASKPRI) & 4));
 826 }
 827 EXPORT_SYMBOL_GPL(kvm_lapic_set_tpr);
 828
 829 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
 830 {
 831         struct kvm_lapic *apic = vcpu->arch.apic;
 832         u64 tpr;
 833
 834         if (!apic)
 835                 return 0;
 836         tpr = (u64) apic_get_reg(apic, APIC_TASKPRI);
 837
 838         return (tpr & 0xf0) >> 4;
 839 }
 840 EXPORT_SYMBOL_GPL(kvm_lapic_get_cr8);
 841
 842 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
 843 {
 844         struct kvm_lapic *apic = vcpu->arch.apic;
 845
 846         if (!apic) {
 847                 value |= MSR_IA32_APICBASE_BSP;
 848                 vcpu->arch.apic_base = value;
 849                 return;
 850         }
 851         if (apic->vcpu->vcpu_id)
 852                 value &= ~MSR_IA32_APICBASE_BSP;
 853
 854         vcpu->arch.apic_base = value;
 855         apic->base_address = apic->vcpu->arch.apic_base &
 856                              MSR_IA32_APICBASE_BASE;
 857
 858         /* with FSB delivery interrupt, we can restart APIC functionality */
 859         apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
 860                    "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
 861
 862 }
 863
 864 u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu)
 865 {
 866         return vcpu->arch.apic_base;
 867 }
 868 EXPORT_SYMBOL_GPL(kvm_lapic_get_base);
 869
 870 void kvm_lapic_reset(struct kvm_vcpu *vcpu)
 871 {
 872         struct kvm_lapic *apic;
 873         int i;
 874
 875         apic_debug("%s\n", __func__);
 876
 877         ASSERT(vcpu);
 878         apic = vcpu->arch.apic;
 879         ASSERT(apic != NULL);
 880
 881         /* Stop the timer in case it's a reset to an active apic */
 882         hrtimer_cancel(&apic->timer.dev);
 883
 884         apic_set_reg(apic, APIC_ID, vcpu->vcpu_id << 24);
 885         apic_set_reg(apic, APIC_LVR, APIC_VERSION);
 886
 887         for (i = 0; i < APIC_LVT_NUM; i++)
 888                 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
 889         apic_set_reg(apic, APIC_LVT0,
 890                      SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
 891
 892         apic_set_reg(apic, APIC_DFR, 0xffffffffU);
 893         apic_set_reg(apic, APIC_SPIV, 0xff);
 894         apic_set_reg(apic, APIC_TASKPRI, 0);
 895         apic_set_reg(apic, APIC_LDR, 0);
 896         apic_set_reg(apic, APIC_ESR, 0);
 897         apic_set_reg(apic, APIC_ICR, 0);
 898         apic_set_reg(apic, APIC_ICR2, 0);
 899         apic_set_reg(apic, APIC_TDCR, 0);
 900         apic_set_reg(apic, APIC_TMICT, 0);
 901         for (i = 0; i < 8; i++) {
 902                 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
 903                 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
 904                 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
 905         }
 906         update_divide_count(apic);
 907         atomic_set(&apic->timer.pending, 0);
 908         if (vcpu->vcpu_id == 0)
 909                 vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP;
 910         apic_update_ppr(apic);
 911
 912         apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr="
 913                    "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
 914                    vcpu, kvm_apic_id(apic),
 915                    vcpu->arch.apic_base, apic->base_address);
 916 }
 917 EXPORT_SYMBOL_GPL(kvm_lapic_reset);
 918
 919 int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
 920 {
 921         struct kvm_lapic *apic = vcpu->arch.apic;
 922         int ret = 0;
 923
 924         if (!apic)
 925                 return 0;
 926         ret = apic_enabled(apic);
 927
 928         return ret;
 929 }
 930 EXPORT_SYMBOL_GPL(kvm_lapic_enabled);
 931
 932 /*
 933  *----------------------------------------------------------------------
 934  * timer interface
 935  *----------------------------------------------------------------------
 936  */
 937
 938 /* TODO: make sure __apic_timer_fn runs in current pCPU */
 939 static int __apic_timer_fn(struct kvm_lapic *apic)
 940 {
 941         int result = 0;
 942         wait_queue_head_t *q = &apic->vcpu->wq;
 943
 944         if(!atomic_inc_and_test(&apic->timer.pending))
 945                 set_bit(KVM_REQ_PENDING_TIMER, &apic->vcpu->requests);
 946         if (waitqueue_active(q))
 947                 wake_up_interruptible(q);
 948
 949         if (apic_lvtt_period(apic)) {
 950                 result = 1;
 951                 apic->timer.dev.expires = ktime_add_ns(
 952                                         apic->timer.dev.expires,
 953                                         apic->timer.period);
 954         }
 955         return result;
 956 }
 957
 958 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
 959 {
 960         struct kvm_lapic *lapic = vcpu->arch.apic;
 961
 962         if (lapic && apic_enabled(lapic) && apic_lvt_enabled(lapic, APIC_LVTT))
 963                 return atomic_read(&lapic->timer.pending);
 964
 965         return 0;
 966 }
 967
 968 static int __inject_apic_timer_irq(struct kvm_lapic *apic)
 969 {
 970         int vector;
 971
 972         vector = apic_lvt_vector(apic, APIC_LVTT);
 973         return __apic_accept_irq(apic, APIC_DM_FIXED, vector, 1, 0);
 974 }
 975
 976 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
 977 {
 978         struct kvm_lapic *apic;
 979         int restart_timer = 0;
 980
 981         apic = container_of(data, struct kvm_lapic, timer.dev);
 982
 983         restart_timer = __apic_timer_fn(apic);
 984
 985         if (restart_timer)
 986                 return HRTIMER_RESTART;
 987         else
 988                 return HRTIMER_NORESTART;
 989 }
 990
 991 int kvm_create_lapic(struct kvm_vcpu *vcpu)
 992 {
 993         struct kvm_lapic *apic;
 994
 995         ASSERT(vcpu != NULL);
 996         apic_debug("apic_init %d\n", vcpu->vcpu_id);
 997
 998         apic = kzalloc(sizeof(*apic), GFP_KERNEL);
 999         if (!apic)
1000                 goto nomem;
1001
1002         vcpu->arch.apic = apic;
1003
1004         apic->regs_page = alloc_page(GFP_KERNEL);
1005         if (apic->regs_page == NULL) {
1006                 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1007                        vcpu->vcpu_id);
1008                 goto nomem_free_apic;
1009         }
1010         apic->regs = page_address(apic->regs_page);
1011         memset(apic->regs, 0, PAGE_SIZE);
1012         apic->vcpu = vcpu;
1013
1014         hrtimer_init(&apic->timer.dev, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
1015         apic->timer.dev.function = apic_timer_fn;
1016         apic->base_address = APIC_DEFAULT_PHYS_BASE;
1017         vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE;
1018
1019         kvm_lapic_reset(vcpu);
1020         apic->dev.read = apic_mmio_read;
1021         apic->dev.write = apic_mmio_write;
1022         apic->dev.in_range = apic_mmio_range;
1023         apic->dev.private = apic;
1024
1025         return 0;
1026 nomem_free_apic:
1027         kfree(apic);
1028 nomem:
1029         return -ENOMEM;
1030 }
1031 EXPORT_SYMBOL_GPL(kvm_create_lapic);
1032
1033 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1034 {
1035         struct kvm_lapic *apic = vcpu->arch.apic;
1036         int highest_irr;
1037
1038         if (!apic || !apic_enabled(apic))
1039                 return -1;
1040
1041         apic_update_ppr(apic);
1042         highest_irr = apic_find_highest_irr(apic);
1043         if ((highest_irr == -1) ||
1044             ((highest_irr & 0xF0) <= apic_get_reg(apic, APIC_PROCPRI)))
1045                 return -1;
1046         return highest_irr;
1047 }
1048
1049 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1050 {
1051         u32 lvt0 = apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1052         int r = 0;
1053
1054         if (vcpu->vcpu_id == 0) {
1055                 if (!apic_hw_enabled(vcpu->arch.apic))
1056                         r = 1;
1057                 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1058                     GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1059                         r = 1;
1060         }
1061         return r;
1062 }
1063
1064 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1065 {
1066         struct kvm_lapic *apic = vcpu->arch.apic;
1067
1068         if (apic && apic_lvt_enabled(apic, APIC_LVTT) &&
1069                 atomic_read(&apic->timer.pending) > 0) {
1070                 if (__inject_apic_timer_irq(apic))
1071                         atomic_dec(&apic->timer.pending);
1072         }
1073 }
1074
1075 void kvm_apic_timer_intr_post(struct kvm_vcpu *vcpu, int vec)
1076 {
1077         struct kvm_lapic *apic = vcpu->arch.apic;
1078
1079         if (apic && apic_lvt_vector(apic, APIC_LVTT) == vec)
1080                 apic->timer.last_update = ktime_add_ns(
1081                                 apic->timer.last_update,
1082                                 apic->timer.period);
1083 }
1084
1085 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1086 {
1087         int vector = kvm_apic_has_interrupt(vcpu);
1088         struct kvm_lapic *apic = vcpu->arch.apic;
1089
1090         if (vector == -1)
1091                 return -1;
1092
1093         apic_set_vector(vector, apic->regs + APIC_ISR);
1094         apic_update_ppr(apic);
1095         apic_clear_irr(vector, apic);
1096         return vector;
1097 }
1098
1099 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu)
1100 {
1101         struct kvm_lapic *apic = vcpu->arch.apic;
1102
1103         apic->base_address = vcpu->arch.apic_base &
1104                              MSR_IA32_APICBASE_BASE;
1105         apic_set_reg(apic, APIC_LVR, APIC_VERSION);
1106         apic_update_ppr(apic);
1107         hrtimer_cancel(&apic->timer.dev);
1108         update_divide_count(apic);
1109         start_apic_timer(apic);
1110 }
1111
1112 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1113 {
1114         struct kvm_lapic *apic = vcpu->arch.apic;
1115         struct hrtimer *timer;
1116
1117         if (!apic)
1118                 return;
1119
1120         timer = &apic->timer.dev;
1121         if (hrtimer_cancel(timer))
1122                 hrtimer_start(timer, timer->expires, HRTIMER_MODE_ABS);
1123 }
1124
1125 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1126 {
1127         u32 data;
1128         void *vapic;
1129
1130         if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1131                 return;
1132
1133         vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1134         data = *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr));
1135         kunmap_atomic(vapic, KM_USER0);
1136
1137         apic_set_tpr(vcpu->arch.apic, data & 0xff);
1138 }
1139
1140 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1141 {
1142         u32 data, tpr;
1143         int max_irr, max_isr;
1144         struct kvm_lapic *apic;
1145         void *vapic;
1146
1147         if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1148                 return;
1149
1150         apic = vcpu->arch.apic;
1151         tpr = apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1152         max_irr = apic_find_highest_irr(apic);
1153         if (max_irr < 0)
1154                 max_irr = 0;
1155         max_isr = apic_find_highest_isr(apic);
1156         if (max_isr < 0)
1157                 max_isr = 0;
1158         data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1159
1160         vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1161         *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)) = data;
1162         kunmap_atomic(vapic, KM_USER0);
1163 }
1164
1165 void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1166 {
1167         if (!irqchip_in_kernel(vcpu->kvm))
1168                 return;
1169
1170         vcpu->arch.apic->vapic_addr = vapic_addr;
1171 }