3 * Local APIC virtualization
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
10 * Dor Laor <dor.laor@qumranet.com>
11 * Gregory Haskins <ghaskins@novell.com>
12 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
14 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
20 #include <linux/kvm_host.h>
21 #include <linux/kvm.h>
23 #include <linux/highmem.h>
24 #include <linux/smp.h>
25 #include <linux/hrtimer.h>
27 #include <linux/module.h>
28 #include <linux/math64.h>
29 #include <asm/processor.h>
32 #include <asm/current.h>
33 #include <asm/apicdef.h>
34 #include <asm/atomic.h>
35 #include "kvm_cache_regs.h"
40 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
42 #define mod_64(x, y) ((x) % (y))
50 #define APIC_BUS_CYCLE_NS 1
52 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
53 #define apic_debug(fmt, arg...)
55 #define APIC_LVT_NUM 6
56 /* 14 is the version for Xeon and Pentium 8.4.8*/
57 #define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
58 #define LAPIC_MMIO_LENGTH (1 << 12)
59 /* followed define is not in apicdef.h */
60 #define APIC_SHORT_MASK 0xc0000
61 #define APIC_DEST_NOSHORT 0x0
62 #define APIC_DEST_MASK 0x800
63 #define MAX_APIC_VECTOR 256
65 #define VEC_POS(v) ((v) & (32 - 1))
66 #define REG_POS(v) (((v) >> 5) << 4)
68 static inline u32 apic_get_reg(struct kvm_lapic *apic, int reg_off)
70 return *((u32 *) (apic->regs + reg_off));
73 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
75 *((u32 *) (apic->regs + reg_off)) = val;
78 static inline int apic_test_and_set_vector(int vec, void *bitmap)
80 return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
83 static inline int apic_test_and_clear_vector(int vec, void *bitmap)
85 return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
88 static inline void apic_set_vector(int vec, void *bitmap)
90 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
93 static inline void apic_clear_vector(int vec, void *bitmap)
95 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
98 static inline int apic_hw_enabled(struct kvm_lapic *apic)
100 return (apic)->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
103 static inline int apic_sw_enabled(struct kvm_lapic *apic)
105 return apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED;
108 static inline int apic_enabled(struct kvm_lapic *apic)
110 return apic_sw_enabled(apic) && apic_hw_enabled(apic);
114 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
117 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
118 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
120 static inline int kvm_apic_id(struct kvm_lapic *apic)
122 return (apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
125 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
127 return !(apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
130 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
132 return apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
135 static inline int apic_lvtt_period(struct kvm_lapic *apic)
137 return apic_get_reg(apic, APIC_LVTT) & APIC_LVT_TIMER_PERIODIC;
140 static inline int apic_lvt_nmi_mode(u32 lvt_val)
142 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
145 static unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
146 LVT_MASK | APIC_LVT_TIMER_PERIODIC, /* LVTT */
147 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
148 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
149 LINT_MASK, LINT_MASK, /* LVT0-1 */
150 LVT_MASK /* LVTERR */
153 static int find_highest_vector(void *bitmap)
156 int word_offset = MAX_APIC_VECTOR >> 5;
158 while ((word_offset != 0) && (word[(--word_offset) << 2] == 0))
161 if (likely(!word_offset && !word[0]))
164 return fls(word[word_offset << 2]) - 1 + (word_offset << 5);
167 static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic)
169 apic->irr_pending = true;
170 return apic_test_and_set_vector(vec, apic->regs + APIC_IRR);
173 static inline int apic_search_irr(struct kvm_lapic *apic)
175 return find_highest_vector(apic->regs + APIC_IRR);
178 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
182 if (!apic->irr_pending)
185 result = apic_search_irr(apic);
186 ASSERT(result == -1 || result >= 16);
191 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
193 apic->irr_pending = false;
194 apic_clear_vector(vec, apic->regs + APIC_IRR);
195 if (apic_search_irr(apic) != -1)
196 apic->irr_pending = true;
199 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
201 struct kvm_lapic *apic = vcpu->arch.apic;
204 /* This may race with setting of irr in __apic_accept_irq() and
205 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
206 * will cause vmexit immediately and the value will be recalculated
207 * on the next vmentry.
211 highest_irr = apic_find_highest_irr(apic);
216 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
217 int vector, int level, int trig_mode);
219 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq)
221 struct kvm_lapic *apic = vcpu->arch.apic;
223 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
224 irq->level, irq->trig_mode);
227 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
231 result = find_highest_vector(apic->regs + APIC_ISR);
232 ASSERT(result == -1 || result >= 16);
237 static void apic_update_ppr(struct kvm_lapic *apic)
242 tpr = apic_get_reg(apic, APIC_TASKPRI);
243 isr = apic_find_highest_isr(apic);
244 isrv = (isr != -1) ? isr : 0;
246 if ((tpr & 0xf0) >= (isrv & 0xf0))
251 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
252 apic, ppr, isr, isrv);
254 apic_set_reg(apic, APIC_PROCPRI, ppr);
257 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
259 apic_set_reg(apic, APIC_TASKPRI, tpr);
260 apic_update_ppr(apic);
263 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest)
265 return dest == 0xff || kvm_apic_id(apic) == dest;
268 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
273 logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR));
275 switch (apic_get_reg(apic, APIC_DFR)) {
277 if (logical_id & mda)
280 case APIC_DFR_CLUSTER:
281 if (((logical_id >> 4) == (mda >> 0x4))
282 && (logical_id & mda & 0xf))
286 printk(KERN_WARNING "Bad DFR vcpu %d: %08x\n",
287 apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR));
294 int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
295 int short_hand, int dest, int dest_mode)
298 struct kvm_lapic *target = vcpu->arch.apic;
300 apic_debug("target %p, source %p, dest 0x%x, "
301 "dest_mode 0x%x, short_hand 0x%x\n",
302 target, source, dest, dest_mode, short_hand);
305 switch (short_hand) {
306 case APIC_DEST_NOSHORT:
309 result = kvm_apic_match_physical_addr(target, dest);
312 result = kvm_apic_match_logical_addr(target, dest);
315 result = (target == source);
317 case APIC_DEST_ALLINC:
320 case APIC_DEST_ALLBUT:
321 result = (target != source);
324 printk(KERN_WARNING "Bad dest shorthand value %x\n",
333 * Add a pending IRQ into lapic.
334 * Return 1 if successfully added and 0 if discarded.
336 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
337 int vector, int level, int trig_mode)
340 struct kvm_vcpu *vcpu = apic->vcpu;
342 switch (delivery_mode) {
344 vcpu->arch.apic_arb_prio++;
346 /* FIXME add logic for vcpu on reset */
347 if (unlikely(!apic_enabled(apic)))
350 result = !apic_test_and_set_irr(vector, apic);
353 apic_debug("level trig mode repeatedly for "
354 "vector %d", vector);
359 apic_debug("level trig mode for vector %d", vector);
360 apic_set_vector(vector, apic->regs + APIC_TMR);
362 apic_clear_vector(vector, apic->regs + APIC_TMR);
367 printk(KERN_DEBUG "Ignoring delivery mode 3\n");
371 printk(KERN_DEBUG "Ignoring guest SMI\n");
376 kvm_inject_nmi(vcpu);
383 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
385 "INIT on a runnable vcpu %d\n",
387 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
390 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
395 case APIC_DM_STARTUP:
396 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
397 vcpu->vcpu_id, vector);
398 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
400 vcpu->arch.sipi_vector = vector;
401 vcpu->arch.mp_state = KVM_MP_STATE_SIPI_RECEIVED;
408 * Should only be called by kvm_apic_local_deliver() with LVT0,
409 * before NMI watchdog was enabled. Already handled by
410 * kvm_apic_accept_pic_intr().
415 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
422 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
424 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
427 static void apic_set_eoi(struct kvm_lapic *apic)
429 int vector = apic_find_highest_isr(apic);
432 * Not every write EOI will has corresponding ISR,
433 * one example is when Kernel check timer on setup_IO_APIC
438 apic_clear_vector(vector, apic->regs + APIC_ISR);
439 apic_update_ppr(apic);
441 if (apic_test_and_clear_vector(vector, apic->regs + APIC_TMR))
442 trigger_mode = IOAPIC_LEVEL_TRIG;
444 trigger_mode = IOAPIC_EDGE_TRIG;
445 mutex_lock(&apic->vcpu->kvm->irq_lock);
446 kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode);
447 mutex_unlock(&apic->vcpu->kvm->irq_lock);
450 static void apic_send_ipi(struct kvm_lapic *apic)
452 u32 icr_low = apic_get_reg(apic, APIC_ICR);
453 u32 icr_high = apic_get_reg(apic, APIC_ICR2);
454 struct kvm_lapic_irq irq;
456 irq.vector = icr_low & APIC_VECTOR_MASK;
457 irq.delivery_mode = icr_low & APIC_MODE_MASK;
458 irq.dest_mode = icr_low & APIC_DEST_MASK;
459 irq.level = icr_low & APIC_INT_ASSERT;
460 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
461 irq.shorthand = icr_low & APIC_SHORT_MASK;
462 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
464 apic_debug("icr_high 0x%x, icr_low 0x%x, "
465 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
466 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
467 icr_high, icr_low, irq.shorthand, irq.dest_id,
468 irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
471 mutex_lock(&apic->vcpu->kvm->irq_lock);
472 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq);
473 mutex_unlock(&apic->vcpu->kvm->irq_lock);
476 static u32 apic_get_tmcct(struct kvm_lapic *apic)
482 ASSERT(apic != NULL);
484 /* if initial count is 0, current count should also be 0 */
485 if (apic_get_reg(apic, APIC_TMICT) == 0)
488 remaining = hrtimer_expires_remaining(&apic->lapic_timer.timer);
489 if (ktime_to_ns(remaining) < 0)
490 remaining = ktime_set(0, 0);
492 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
493 tmcct = div64_u64(ns,
494 (APIC_BUS_CYCLE_NS * apic->divide_count));
499 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
501 struct kvm_vcpu *vcpu = apic->vcpu;
502 struct kvm_run *run = vcpu->run;
504 set_bit(KVM_REQ_REPORT_TPR_ACCESS, &vcpu->requests);
505 run->tpr_access.rip = kvm_rip_read(vcpu);
506 run->tpr_access.is_write = write;
509 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
511 if (apic->vcpu->arch.tpr_access_reporting)
512 __report_tpr_access(apic, write);
515 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
519 if (offset >= LAPIC_MMIO_LENGTH)
524 printk(KERN_WARNING "Access APIC ARBPRI register "
525 "which is for P6\n");
528 case APIC_TMCCT: /* Timer CCR */
529 val = apic_get_tmcct(apic);
533 report_tpr_access(apic, false);
536 apic_update_ppr(apic);
537 val = apic_get_reg(apic, offset);
544 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
546 return container_of(dev, struct kvm_lapic, dev);
549 static void apic_mmio_read(struct kvm_io_device *this,
550 gpa_t address, int len, void *data)
552 struct kvm_lapic *apic = to_lapic(this);
553 unsigned int offset = address - apic->base_address;
554 unsigned char alignment = offset & 0xf;
557 if ((alignment + len) > 4) {
558 printk(KERN_ERR "KVM_APIC_READ: alignment error %lx %d",
559 (unsigned long)address, len);
562 result = __apic_read(apic, offset & ~0xf);
564 trace_kvm_apic_read(offset, result);
570 memcpy(data, (char *)&result + alignment, len);
573 printk(KERN_ERR "Local APIC read with len = %x, "
574 "should be 1,2, or 4 instead\n", len);
579 static void update_divide_count(struct kvm_lapic *apic)
581 u32 tmp1, tmp2, tdcr;
583 tdcr = apic_get_reg(apic, APIC_TDCR);
585 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
586 apic->divide_count = 0x1 << (tmp2 & 0x7);
588 apic_debug("timer divide count is 0x%x\n",
592 static void start_apic_timer(struct kvm_lapic *apic)
594 ktime_t now = apic->lapic_timer.timer.base->get_time();
596 apic->lapic_timer.period = apic_get_reg(apic, APIC_TMICT) *
597 APIC_BUS_CYCLE_NS * apic->divide_count;
598 atomic_set(&apic->lapic_timer.pending, 0);
600 if (!apic->lapic_timer.period)
603 hrtimer_start(&apic->lapic_timer.timer,
604 ktime_add_ns(now, apic->lapic_timer.period),
607 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
609 "timer initial count 0x%x, period %lldns, "
610 "expire @ 0x%016" PRIx64 ".\n", __func__,
611 APIC_BUS_CYCLE_NS, ktime_to_ns(now),
612 apic_get_reg(apic, APIC_TMICT),
613 apic->lapic_timer.period,
614 ktime_to_ns(ktime_add_ns(now,
615 apic->lapic_timer.period)));
618 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
620 int nmi_wd_enabled = apic_lvt_nmi_mode(apic_get_reg(apic, APIC_LVT0));
622 if (apic_lvt_nmi_mode(lvt0_val)) {
623 if (!nmi_wd_enabled) {
624 apic_debug("Receive NMI setting on APIC_LVT0 "
625 "for cpu %d\n", apic->vcpu->vcpu_id);
626 apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
628 } else if (nmi_wd_enabled)
629 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
632 static void apic_mmio_write(struct kvm_io_device *this,
633 gpa_t address, int len, const void *data)
635 struct kvm_lapic *apic = to_lapic(this);
636 unsigned int offset = address - apic->base_address;
637 unsigned char alignment = offset & 0xf;
641 * APIC register must be aligned on 128-bits boundary.
642 * 32/64/128 bits registers must be accessed thru 32 bits.
645 if (len != 4 || alignment) {
646 /* Don't shout loud, $infamous_os would cause only noise. */
647 apic_debug("apic write: bad size=%d %lx\n",
654 /* too common printing */
655 if (offset != APIC_EOI)
656 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
657 "0x%x\n", __func__, offset, len, val);
661 trace_kvm_apic_write(offset, val);
664 case APIC_ID: /* Local APIC ID */
665 apic_set_reg(apic, APIC_ID, val);
669 report_tpr_access(apic, true);
670 apic_set_tpr(apic, val & 0xff);
678 apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK);
682 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
686 apic_set_reg(apic, APIC_SPIV, val & 0x3ff);
687 if (!(val & APIC_SPIV_APIC_ENABLED)) {
691 for (i = 0; i < APIC_LVT_NUM; i++) {
692 lvt_val = apic_get_reg(apic,
693 APIC_LVTT + 0x10 * i);
694 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
695 lvt_val | APIC_LVT_MASKED);
697 atomic_set(&apic->lapic_timer.pending, 0);
703 /* No delay here, so we always clear the pending bit */
704 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
709 apic_set_reg(apic, APIC_ICR2, val & 0xff000000);
713 apic_manage_nmi_watchdog(apic, val);
719 /* TODO: Check vector */
720 if (!apic_sw_enabled(apic))
721 val |= APIC_LVT_MASKED;
723 val &= apic_lvt_mask[(offset - APIC_LVTT) >> 4];
724 apic_set_reg(apic, offset, val);
729 hrtimer_cancel(&apic->lapic_timer.timer);
730 apic_set_reg(apic, APIC_TMICT, val);
731 start_apic_timer(apic);
736 printk(KERN_ERR "KVM_WRITE:TDCR %x\n", val);
737 apic_set_reg(apic, APIC_TDCR, val);
738 update_divide_count(apic);
742 apic_debug("Local APIC Write to read-only register %x\n",
749 static int apic_mmio_range(struct kvm_io_device *this, gpa_t addr,
752 struct kvm_lapic *apic = to_lapic(this);
756 if (apic_hw_enabled(apic) &&
757 (addr >= apic->base_address) &&
758 (addr < (apic->base_address + LAPIC_MMIO_LENGTH)))
764 void kvm_free_lapic(struct kvm_vcpu *vcpu)
766 if (!vcpu->arch.apic)
769 hrtimer_cancel(&vcpu->arch.apic->lapic_timer.timer);
771 if (vcpu->arch.apic->regs_page)
772 __free_page(vcpu->arch.apic->regs_page);
774 kfree(vcpu->arch.apic);
778 *----------------------------------------------------------------------
780 *----------------------------------------------------------------------
783 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
785 struct kvm_lapic *apic = vcpu->arch.apic;
789 apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
790 | (apic_get_reg(apic, APIC_TASKPRI) & 4));
793 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
795 struct kvm_lapic *apic = vcpu->arch.apic;
800 tpr = (u64) apic_get_reg(apic, APIC_TASKPRI);
802 return (tpr & 0xf0) >> 4;
805 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
807 struct kvm_lapic *apic = vcpu->arch.apic;
810 value |= MSR_IA32_APICBASE_BSP;
811 vcpu->arch.apic_base = value;
815 if (!kvm_vcpu_is_bsp(apic->vcpu))
816 value &= ~MSR_IA32_APICBASE_BSP;
818 vcpu->arch.apic_base = value;
819 apic->base_address = apic->vcpu->arch.apic_base &
820 MSR_IA32_APICBASE_BASE;
822 /* with FSB delivery interrupt, we can restart APIC functionality */
823 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
824 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
828 void kvm_lapic_reset(struct kvm_vcpu *vcpu)
830 struct kvm_lapic *apic;
833 apic_debug("%s\n", __func__);
836 apic = vcpu->arch.apic;
837 ASSERT(apic != NULL);
839 /* Stop the timer in case it's a reset to an active apic */
840 hrtimer_cancel(&apic->lapic_timer.timer);
842 apic_set_reg(apic, APIC_ID, vcpu->vcpu_id << 24);
843 apic_set_reg(apic, APIC_LVR, APIC_VERSION);
845 for (i = 0; i < APIC_LVT_NUM; i++)
846 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
847 apic_set_reg(apic, APIC_LVT0,
848 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
850 apic_set_reg(apic, APIC_DFR, 0xffffffffU);
851 apic_set_reg(apic, APIC_SPIV, 0xff);
852 apic_set_reg(apic, APIC_TASKPRI, 0);
853 apic_set_reg(apic, APIC_LDR, 0);
854 apic_set_reg(apic, APIC_ESR, 0);
855 apic_set_reg(apic, APIC_ICR, 0);
856 apic_set_reg(apic, APIC_ICR2, 0);
857 apic_set_reg(apic, APIC_TDCR, 0);
858 apic_set_reg(apic, APIC_TMICT, 0);
859 for (i = 0; i < 8; i++) {
860 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
861 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
862 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
864 apic->irr_pending = false;
865 update_divide_count(apic);
866 atomic_set(&apic->lapic_timer.pending, 0);
867 if (kvm_vcpu_is_bsp(vcpu))
868 vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP;
869 apic_update_ppr(apic);
871 vcpu->arch.apic_arb_prio = 0;
873 apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr="
874 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
875 vcpu, kvm_apic_id(apic),
876 vcpu->arch.apic_base, apic->base_address);
879 bool kvm_apic_present(struct kvm_vcpu *vcpu)
881 return vcpu->arch.apic && apic_hw_enabled(vcpu->arch.apic);
884 int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
886 return kvm_apic_present(vcpu) && apic_sw_enabled(vcpu->arch.apic);
890 *----------------------------------------------------------------------
892 *----------------------------------------------------------------------
895 static bool lapic_is_periodic(struct kvm_timer *ktimer)
897 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic,
899 return apic_lvtt_period(apic);
902 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
904 struct kvm_lapic *lapic = vcpu->arch.apic;
906 if (lapic && apic_enabled(lapic) && apic_lvt_enabled(lapic, APIC_LVTT))
907 return atomic_read(&lapic->lapic_timer.pending);
912 static int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
914 u32 reg = apic_get_reg(apic, lvt_type);
915 int vector, mode, trig_mode;
917 if (apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
918 vector = reg & APIC_VECTOR_MASK;
919 mode = reg & APIC_MODE_MASK;
920 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
921 return __apic_accept_irq(apic, mode, vector, 1, trig_mode);
926 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
928 struct kvm_lapic *apic = vcpu->arch.apic;
931 kvm_apic_local_deliver(apic, APIC_LVT0);
934 static struct kvm_timer_ops lapic_timer_ops = {
935 .is_periodic = lapic_is_periodic,
938 static const struct kvm_io_device_ops apic_mmio_ops = {
939 .read = apic_mmio_read,
940 .write = apic_mmio_write,
941 .in_range = apic_mmio_range,
944 int kvm_create_lapic(struct kvm_vcpu *vcpu)
946 struct kvm_lapic *apic;
948 ASSERT(vcpu != NULL);
949 apic_debug("apic_init %d\n", vcpu->vcpu_id);
951 apic = kzalloc(sizeof(*apic), GFP_KERNEL);
955 vcpu->arch.apic = apic;
957 apic->regs_page = alloc_page(GFP_KERNEL);
958 if (apic->regs_page == NULL) {
959 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
961 goto nomem_free_apic;
963 apic->regs = page_address(apic->regs_page);
964 memset(apic->regs, 0, PAGE_SIZE);
967 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
969 apic->lapic_timer.timer.function = kvm_timer_fn;
970 apic->lapic_timer.t_ops = &lapic_timer_ops;
971 apic->lapic_timer.kvm = vcpu->kvm;
972 apic->lapic_timer.vcpu = vcpu;
974 apic->base_address = APIC_DEFAULT_PHYS_BASE;
975 vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE;
977 kvm_lapic_reset(vcpu);
978 kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
987 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
989 struct kvm_lapic *apic = vcpu->arch.apic;
992 if (!apic || !apic_enabled(apic))
995 apic_update_ppr(apic);
996 highest_irr = apic_find_highest_irr(apic);
997 if ((highest_irr == -1) ||
998 ((highest_irr & 0xF0) <= apic_get_reg(apic, APIC_PROCPRI)))
1003 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1005 u32 lvt0 = apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1008 if (kvm_vcpu_is_bsp(vcpu)) {
1009 if (!apic_hw_enabled(vcpu->arch.apic))
1011 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1012 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1018 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1020 struct kvm_lapic *apic = vcpu->arch.apic;
1022 if (apic && atomic_read(&apic->lapic_timer.pending) > 0) {
1023 if (kvm_apic_local_deliver(apic, APIC_LVTT))
1024 atomic_dec(&apic->lapic_timer.pending);
1028 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1030 int vector = kvm_apic_has_interrupt(vcpu);
1031 struct kvm_lapic *apic = vcpu->arch.apic;
1036 apic_set_vector(vector, apic->regs + APIC_ISR);
1037 apic_update_ppr(apic);
1038 apic_clear_irr(vector, apic);
1042 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu)
1044 struct kvm_lapic *apic = vcpu->arch.apic;
1046 apic->base_address = vcpu->arch.apic_base &
1047 MSR_IA32_APICBASE_BASE;
1048 apic_set_reg(apic, APIC_LVR, APIC_VERSION);
1049 apic_update_ppr(apic);
1050 hrtimer_cancel(&apic->lapic_timer.timer);
1051 update_divide_count(apic);
1052 start_apic_timer(apic);
1055 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1057 struct kvm_lapic *apic = vcpu->arch.apic;
1058 struct hrtimer *timer;
1063 timer = &apic->lapic_timer.timer;
1064 if (hrtimer_cancel(timer))
1065 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
1068 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1073 if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1076 vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1077 data = *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr));
1078 kunmap_atomic(vapic, KM_USER0);
1080 apic_set_tpr(vcpu->arch.apic, data & 0xff);
1083 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1086 int max_irr, max_isr;
1087 struct kvm_lapic *apic;
1090 if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1093 apic = vcpu->arch.apic;
1094 tpr = apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1095 max_irr = apic_find_highest_irr(apic);
1098 max_isr = apic_find_highest_isr(apic);
1101 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1103 vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1104 *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)) = data;
1105 kunmap_atomic(vapic, KM_USER0);
1108 void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1110 if (!irqchip_in_kernel(vcpu->kvm))
1113 vcpu->arch.apic->vapic_addr = vapic_addr;