2 * 8259 interrupt controller emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 * Copyright (c) 2007 Intel Corporation
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 * Yaozu (Eddie) Dong <Eddie.dong@intel.com>
29 #include <linux/bitops.h>
32 #include <linux/kvm_host.h>
34 static void pic_lock(struct kvm_pic *s)
39 static void pic_unlock(struct kvm_pic *s)
41 struct kvm *kvm = s->kvm;
42 unsigned acks = s->pending_acks;
43 bool wakeup = s->wakeup_needed;
44 struct kvm_vcpu *vcpu;
47 s->wakeup_needed = false;
49 spin_unlock(&s->lock);
52 kvm_notify_acked_irq(kvm, SELECT_PIC(__ffs(acks)),
58 vcpu = s->kvm->vcpus[0];
64 static void pic_clear_isr(struct kvm_kpic_state *s, int irq)
66 s->isr &= ~(1 << irq);
67 s->isr_ack |= (1 << irq);
70 void kvm_pic_clear_isr_ack(struct kvm *kvm)
72 struct kvm_pic *s = pic_irqchip(kvm);
73 s->pics[0].isr_ack = 0xff;
74 s->pics[1].isr_ack = 0xff;
78 * set irq level. If an edge is detected, then the IRR is set to 1
80 static inline int pic_set_irq1(struct kvm_kpic_state *s, int irq, int level)
84 if (s->elcr & mask) /* level triggered */
86 ret = !(s->irr & mask);
93 else /* edge triggered */
95 if ((s->last_irr & mask) == 0) {
96 ret = !(s->irr & mask);
101 s->last_irr &= ~mask;
103 return (s->imr & mask) ? -1 : ret;
107 * return the highest priority found in mask (highest = smallest
108 * number). Return 8 if no irq
110 static inline int get_priority(struct kvm_kpic_state *s, int mask)
116 while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
122 * return the pic wanted interrupt. return -1 if none
124 static int pic_get_irq(struct kvm_kpic_state *s)
126 int mask, cur_priority, priority;
128 mask = s->irr & ~s->imr;
129 priority = get_priority(s, mask);
133 * compute current priority. If special fully nested mode on the
134 * master, the IRQ coming from the slave is not taken into account
135 * for the priority computation.
138 if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
140 cur_priority = get_priority(s, mask);
141 if (priority < cur_priority)
143 * higher priority found: an irq should be generated
145 return (priority + s->priority_add) & 7;
151 * raise irq to CPU if necessary. must be called every time the active
154 static void pic_update_irq(struct kvm_pic *s)
158 irq2 = pic_get_irq(&s->pics[1]);
161 * if irq request by slave pic, signal master PIC
163 pic_set_irq1(&s->pics[0], 2, 1);
164 pic_set_irq1(&s->pics[0], 2, 0);
166 irq = pic_get_irq(&s->pics[0]);
168 s->irq_request(s->irq_request_opaque, 1);
170 s->irq_request(s->irq_request_opaque, 0);
173 void kvm_pic_update_irq(struct kvm_pic *s)
180 int kvm_pic_set_irq(void *opaque, int irq, int level)
182 struct kvm_pic *s = opaque;
186 if (irq >= 0 && irq < PIC_NUM_PINS) {
187 ret = pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
196 * acknowledge interrupt 'irq'
198 static inline void pic_intack(struct kvm_kpic_state *s, int irq)
202 if (s->rotate_on_auto_eoi)
203 s->priority_add = (irq + 1) & 7;
204 pic_clear_isr(s, irq);
207 * We don't clear a level sensitive interrupt here
209 if (!(s->elcr & (1 << irq)))
210 s->irr &= ~(1 << irq);
213 int kvm_pic_read_irq(struct kvm *kvm)
215 int irq, irq2, intno;
216 struct kvm_pic *s = pic_irqchip(kvm);
219 irq = pic_get_irq(&s->pics[0]);
221 pic_intack(&s->pics[0], irq);
223 irq2 = pic_get_irq(&s->pics[1]);
225 pic_intack(&s->pics[1], irq2);
228 * spurious IRQ on slave controller
231 intno = s->pics[1].irq_base + irq2;
234 intno = s->pics[0].irq_base + irq;
237 * spurious IRQ on host controller
240 intno = s->pics[0].irq_base + irq;
244 kvm_notify_acked_irq(kvm, SELECT_PIC(irq), irq);
249 void kvm_pic_reset(struct kvm_kpic_state *s)
252 struct kvm *kvm = s->pics_state->irq_request_opaque;
253 struct kvm_vcpu *vcpu0 = kvm->vcpus[0];
255 if (s == &s->pics_state->pics[0])
260 for (irq = 0; irq < PIC_NUM_PINS/2; irq++) {
261 if (vcpu0 && kvm_apic_accept_pic_intr(vcpu0))
262 if (s->irr & (1 << irq) || s->isr & (1 << irq)) {
264 s->pics_state->pending_acks |= 1 << n;
274 s->read_reg_select = 0;
279 s->rotate_on_auto_eoi = 0;
280 s->special_fully_nested_mode = 0;
284 static void pic_ioport_write(void *opaque, u32 addr, u32 val)
286 struct kvm_kpic_state *s = opaque;
287 int priority, cmd, irq;
292 kvm_pic_reset(s); /* init */
294 * deassert a pending interrupt
296 s->pics_state->irq_request(s->pics_state->
297 irq_request_opaque, 0);
301 printk(KERN_ERR "single mode not supported");
304 "level sensitive irq not supported");
305 } else if (val & 0x08) {
309 s->read_reg_select = val & 1;
311 s->special_mask = (val >> 5) & 1;
317 s->rotate_on_auto_eoi = cmd >> 2;
319 case 1: /* end of interrupt */
321 priority = get_priority(s, s->isr);
323 irq = (priority + s->priority_add) & 7;
324 pic_clear_isr(s, irq);
326 s->priority_add = (irq + 1) & 7;
327 pic_update_irq(s->pics_state);
332 pic_clear_isr(s, irq);
333 pic_update_irq(s->pics_state);
336 s->priority_add = (val + 1) & 7;
337 pic_update_irq(s->pics_state);
341 s->priority_add = (irq + 1) & 7;
342 pic_clear_isr(s, irq);
343 pic_update_irq(s->pics_state);
346 break; /* no operation */
350 switch (s->init_state) {
351 case 0: /* normal mode */
353 pic_update_irq(s->pics_state);
356 s->irq_base = val & 0xf8;
366 s->special_fully_nested_mode = (val >> 4) & 1;
367 s->auto_eoi = (val >> 1) & 1;
373 static u32 pic_poll_read(struct kvm_kpic_state *s, u32 addr1)
377 ret = pic_get_irq(s);
380 s->pics_state->pics[0].isr &= ~(1 << 2);
381 s->pics_state->pics[0].irr &= ~(1 << 2);
383 s->irr &= ~(1 << ret);
384 pic_clear_isr(s, ret);
385 if (addr1 >> 7 || ret != 2)
386 pic_update_irq(s->pics_state);
389 pic_update_irq(s->pics_state);
395 static u32 pic_ioport_read(void *opaque, u32 addr1)
397 struct kvm_kpic_state *s = opaque;
404 ret = pic_poll_read(s, addr1);
408 if (s->read_reg_select)
417 static void elcr_ioport_write(void *opaque, u32 addr, u32 val)
419 struct kvm_kpic_state *s = opaque;
420 s->elcr = val & s->elcr_mask;
423 static u32 elcr_ioport_read(void *opaque, u32 addr1)
425 struct kvm_kpic_state *s = opaque;
429 static int picdev_in_range(struct kvm_io_device *this, gpa_t addr,
430 int len, int is_write)
445 static void picdev_write(struct kvm_io_device *this,
446 gpa_t addr, int len, const void *val)
448 struct kvm_pic *s = this->private;
449 unsigned char data = *(unsigned char *)val;
452 if (printk_ratelimit())
453 printk(KERN_ERR "PIC: non byte write\n");
462 pic_ioport_write(&s->pics[addr >> 7], addr, data);
466 elcr_ioport_write(&s->pics[addr & 1], addr, data);
472 static void picdev_read(struct kvm_io_device *this,
473 gpa_t addr, int len, void *val)
475 struct kvm_pic *s = this->private;
476 unsigned char data = 0;
479 if (printk_ratelimit())
480 printk(KERN_ERR "PIC: non byte read\n");
489 data = pic_ioport_read(&s->pics[addr >> 7], addr);
493 data = elcr_ioport_read(&s->pics[addr & 1], addr);
496 *(unsigned char *)val = data;
501 * callback when PIC0 irq status changed
503 static void pic_irq_request(void *opaque, int level)
505 struct kvm *kvm = opaque;
506 struct kvm_vcpu *vcpu = kvm->vcpus[0];
507 struct kvm_pic *s = pic_irqchip(kvm);
508 int irq = pic_get_irq(&s->pics[0]);
511 if (vcpu && level && (s->pics[0].isr_ack & (1 << irq))) {
512 s->pics[0].isr_ack &= ~(1 << irq);
513 s->wakeup_needed = true;
517 struct kvm_pic *kvm_create_pic(struct kvm *kvm)
520 s = kzalloc(sizeof(struct kvm_pic), GFP_KERNEL);
523 spin_lock_init(&s->lock);
525 s->pics[0].elcr_mask = 0xf8;
526 s->pics[1].elcr_mask = 0xde;
527 s->irq_request = pic_irq_request;
528 s->irq_request_opaque = kvm;
529 s->pics[0].pics_state = s;
530 s->pics[1].pics_state = s;
533 * Initialize PIO device
535 s->dev.read = picdev_read;
536 s->dev.write = picdev_write;
537 s->dev.in_range = picdev_in_range;
539 kvm_io_bus_register_dev(&kvm->pio_bus, &s->dev);