1 #include <linux/errno.h>
2 #include <linux/kernel.h>
5 #include <linux/prctl.h>
6 #include <linux/slab.h>
7 #include <linux/sched.h>
8 #include <linux/module.h>
10 #include <linux/clockchips.h>
11 #include <linux/random.h>
12 #include <linux/user-return-notifier.h>
13 #include <trace/events/power.h>
14 #include <asm/system.h>
16 #include <asm/syscalls.h>
18 #include <asm/uaccess.h>
22 unsigned long idle_halt;
23 EXPORT_SYMBOL(idle_halt);
24 unsigned long idle_nomwait;
25 EXPORT_SYMBOL(idle_nomwait);
27 struct kmem_cache *task_xstate_cachep;
29 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
32 if (src->thread.xstate) {
33 dst->thread.xstate = kmem_cache_alloc(task_xstate_cachep,
35 if (!dst->thread.xstate)
37 WARN_ON((unsigned long)dst->thread.xstate & 15);
38 memcpy(dst->thread.xstate, src->thread.xstate, xstate_size);
43 void free_thread_xstate(struct task_struct *tsk)
45 if (tsk->thread.xstate) {
46 kmem_cache_free(task_xstate_cachep, tsk->thread.xstate);
47 tsk->thread.xstate = NULL;
50 WARN(tsk->thread.ds_ctx, "leaking DS context\n");
53 void free_thread_info(struct thread_info *ti)
55 free_thread_xstate(ti->task);
56 free_pages((unsigned long)ti, get_order(THREAD_SIZE));
59 void arch_task_cache_init(void)
62 kmem_cache_create("task_xstate", xstate_size,
63 __alignof__(union thread_xstate),
64 SLAB_PANIC | SLAB_NOTRACK, NULL);
68 * Free current thread data structures etc..
70 void exit_thread(void)
72 struct task_struct *me = current;
73 struct thread_struct *t = &me->thread;
74 unsigned long *bp = t->io_bitmap_ptr;
77 struct tss_struct *tss = &per_cpu(init_tss, get_cpu());
79 t->io_bitmap_ptr = NULL;
80 clear_thread_flag(TIF_IO_BITMAP);
82 * Careful, clear this in the TSS too:
84 memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
91 void flush_thread(void)
93 struct task_struct *tsk = current;
96 if (test_tsk_thread_flag(tsk, TIF_ABI_PENDING)) {
97 clear_tsk_thread_flag(tsk, TIF_ABI_PENDING);
98 if (test_tsk_thread_flag(tsk, TIF_IA32)) {
99 clear_tsk_thread_flag(tsk, TIF_IA32);
101 set_tsk_thread_flag(tsk, TIF_IA32);
102 current_thread_info()->status |= TS_COMPAT;
107 clear_tsk_thread_flag(tsk, TIF_DEBUG);
109 tsk->thread.debugreg0 = 0;
110 tsk->thread.debugreg1 = 0;
111 tsk->thread.debugreg2 = 0;
112 tsk->thread.debugreg3 = 0;
113 tsk->thread.debugreg6 = 0;
114 tsk->thread.debugreg7 = 0;
115 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
117 * Forget coprocessor state..
119 tsk->fpu_counter = 0;
124 static void hard_disable_TSC(void)
126 write_cr4(read_cr4() | X86_CR4_TSD);
129 void disable_TSC(void)
132 if (!test_and_set_thread_flag(TIF_NOTSC))
134 * Must flip the CPU state synchronously with
135 * TIF_NOTSC in the current running context.
141 static void hard_enable_TSC(void)
143 write_cr4(read_cr4() & ~X86_CR4_TSD);
146 static void enable_TSC(void)
149 if (test_and_clear_thread_flag(TIF_NOTSC))
151 * Must flip the CPU state synchronously with
152 * TIF_NOTSC in the current running context.
158 int get_tsc_mode(unsigned long adr)
162 if (test_thread_flag(TIF_NOTSC))
163 val = PR_TSC_SIGSEGV;
167 return put_user(val, (unsigned int __user *)adr);
170 int set_tsc_mode(unsigned int val)
172 if (val == PR_TSC_SIGSEGV)
174 else if (val == PR_TSC_ENABLE)
182 void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
183 struct tss_struct *tss)
185 struct thread_struct *prev, *next;
187 prev = &prev_p->thread;
188 next = &next_p->thread;
190 if (test_tsk_thread_flag(next_p, TIF_DS_AREA_MSR) ||
191 test_tsk_thread_flag(prev_p, TIF_DS_AREA_MSR))
192 ds_switch_to(prev_p, next_p);
193 else if (next->debugctlmsr != prev->debugctlmsr)
194 update_debugctlmsr(next->debugctlmsr);
196 if (test_tsk_thread_flag(next_p, TIF_DEBUG)) {
197 set_debugreg(next->debugreg0, 0);
198 set_debugreg(next->debugreg1, 1);
199 set_debugreg(next->debugreg2, 2);
200 set_debugreg(next->debugreg3, 3);
202 set_debugreg(next->debugreg6, 6);
203 set_debugreg(next->debugreg7, 7);
206 if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
207 test_tsk_thread_flag(next_p, TIF_NOTSC)) {
208 /* prev and next are different */
209 if (test_tsk_thread_flag(next_p, TIF_NOTSC))
215 if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
217 * Copy the relevant range of the IO bitmap.
218 * Normally this is 128 bytes or less:
220 memcpy(tss->io_bitmap, next->io_bitmap_ptr,
221 max(prev->io_bitmap_max, next->io_bitmap_max));
222 } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) {
224 * Clear any possible leftover bits:
226 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
228 propagate_user_return_notify(prev_p, next_p);
231 int sys_fork(struct pt_regs *regs)
233 return do_fork(SIGCHLD, regs->sp, regs, 0, NULL, NULL);
237 * This is trivial, and on the face of it looks like it
238 * could equally well be done in user mode.
240 * Not so, for quite unobvious reasons - register pressure.
241 * In user mode vfork() cannot have a stack frame, and if
242 * done by calling the "clone()" system call directly, you
243 * do not have enough call-clobbered registers to hold all
244 * the information you need.
246 int sys_vfork(struct pt_regs *regs)
248 return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->sp, regs, 0,
254 * Idle related variables and functions
256 unsigned long boot_option_idle_override = 0;
257 EXPORT_SYMBOL(boot_option_idle_override);
260 * Powermanagement idle function, if any..
262 void (*pm_idle)(void);
263 EXPORT_SYMBOL(pm_idle);
267 * This halt magic was a workaround for ancient floppy DMA
268 * wreckage. It should be safe to remove.
270 static int hlt_counter;
271 void disable_hlt(void)
275 EXPORT_SYMBOL(disable_hlt);
277 void enable_hlt(void)
281 EXPORT_SYMBOL(enable_hlt);
283 static inline int hlt_use_halt(void)
285 return (!hlt_counter && boot_cpu_data.hlt_works_ok);
288 static inline int hlt_use_halt(void)
295 * We use this if we don't have any better
298 void default_idle(void)
300 if (hlt_use_halt()) {
301 trace_power_start(POWER_CSTATE, 1);
302 current_thread_info()->status &= ~TS_POLLING;
304 * TS_POLLING-cleared state must be visible before we
310 safe_halt(); /* enables interrupts racelessly */
313 current_thread_info()->status |= TS_POLLING;
316 /* loop is done by the caller */
320 #ifdef CONFIG_APM_MODULE
321 EXPORT_SYMBOL(default_idle);
324 void stop_this_cpu(void *dummy)
330 set_cpu_online(smp_processor_id(), false);
331 disable_local_APIC();
334 if (hlt_works(smp_processor_id()))
339 static void do_nothing(void *unused)
344 * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
345 * pm_idle and update to new pm_idle value. Required while changing pm_idle
346 * handler on SMP systems.
348 * Caller must have changed pm_idle to the new value before the call. Old
349 * pm_idle value will not be used by any CPU after the return of this function.
351 void cpu_idle_wait(void)
354 /* kick all the CPUs so that they exit out of pm_idle */
355 smp_call_function(do_nothing, NULL, 1);
357 EXPORT_SYMBOL_GPL(cpu_idle_wait);
360 * This uses new MONITOR/MWAIT instructions on P4 processors with PNI,
361 * which can obviate IPI to trigger checking of need_resched.
362 * We execute MONITOR against need_resched and enter optimized wait state
363 * through MWAIT. Whenever someone changes need_resched, we would be woken
364 * up from MWAIT (without an IPI).
366 * New with Core Duo processors, MWAIT can take some hints based on CPU
369 void mwait_idle_with_hints(unsigned long ax, unsigned long cx)
371 trace_power_start(POWER_CSTATE, (ax>>4)+1);
372 if (!need_resched()) {
373 if (cpu_has(¤t_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
374 clflush((void *)¤t_thread_info()->flags);
376 __monitor((void *)¤t_thread_info()->flags, 0, 0);
383 /* Default MONITOR/MWAIT with no hints, used for default C1 state */
384 static void mwait_idle(void)
386 if (!need_resched()) {
387 trace_power_start(POWER_CSTATE, 1);
388 if (cpu_has(¤t_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
389 clflush((void *)¤t_thread_info()->flags);
391 __monitor((void *)¤t_thread_info()->flags, 0, 0);
402 * On SMP it's slightly faster (but much more power-consuming!)
403 * to poll the ->work.need_resched flag instead of waiting for the
404 * cross-CPU IPI to arrive. Use this option with caution.
406 static void poll_idle(void)
408 trace_power_start(POWER_CSTATE, 0);
410 while (!need_resched())
416 * mwait selection logic:
418 * It depends on the CPU. For AMD CPUs that support MWAIT this is
419 * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings
420 * then depend on a clock divisor and current Pstate of the core. If
421 * all cores of a processor are in halt state (C1) the processor can
422 * enter the C1E (C1 enhanced) state. If mwait is used this will never
425 * idle=mwait overrides this decision and forces the usage of mwait.
427 static int __cpuinitdata force_mwait;
429 #define MWAIT_INFO 0x05
430 #define MWAIT_ECX_EXTENDED_INFO 0x01
431 #define MWAIT_EDX_C1 0xf0
433 static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c)
435 u32 eax, ebx, ecx, edx;
440 if (c->cpuid_level < MWAIT_INFO)
443 cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx);
444 /* Check, whether EDX has extended info about MWAIT */
445 if (!(ecx & MWAIT_ECX_EXTENDED_INFO))
449 * edx enumeratios MONITOR/MWAIT extensions. Check, whether
452 return (edx & MWAIT_EDX_C1);
456 * Check for AMD CPUs, which have potentially C1E support
458 static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c)
460 if (c->x86_vendor != X86_VENDOR_AMD)
466 /* Family 0x0f models < rev F do not have C1E */
467 if (c->x86 == 0x0f && c->x86_model < 0x40)
473 static cpumask_var_t c1e_mask;
474 static int c1e_detected;
476 void c1e_remove_cpu(int cpu)
478 if (c1e_mask != NULL)
479 cpumask_clear_cpu(cpu, c1e_mask);
483 * C1E aware idle routine. We check for C1E active in the interrupt
484 * pending message MSR. If we detect C1E, then we handle it the same
485 * way as C3 power states (local apic timer and TSC stop)
487 static void c1e_idle(void)
495 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
496 if (lo & K8_INTP_C1E_ACTIVE_MASK) {
498 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
499 mark_tsc_unstable("TSC halt in AMD C1E");
500 printk(KERN_INFO "System has AMD C1E enabled\n");
501 set_cpu_cap(&boot_cpu_data, X86_FEATURE_AMDC1E);
506 int cpu = smp_processor_id();
508 if (!cpumask_test_cpu(cpu, c1e_mask)) {
509 cpumask_set_cpu(cpu, c1e_mask);
511 * Force broadcast so ACPI can not interfere.
513 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
515 printk(KERN_INFO "Switch to broadcast mode on CPU%d\n",
518 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
523 * The switch back from broadcast mode needs to be
524 * called with interrupts disabled.
527 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
533 void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
536 if (pm_idle == poll_idle && smp_num_siblings > 1) {
537 printk(KERN_WARNING "WARNING: polling idle and HT enabled,"
538 " performance may degrade.\n");
544 if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) {
546 * One CPU supports mwait => All CPUs supports mwait
548 printk(KERN_INFO "using mwait in idle threads.\n");
549 pm_idle = mwait_idle;
550 } else if (check_c1e_idle(c)) {
551 printk(KERN_INFO "using C1E aware idle routine\n");
554 pm_idle = default_idle;
557 void __init init_c1e_mask(void)
559 /* If we're using c1e_idle, we need to allocate c1e_mask. */
560 if (pm_idle == c1e_idle)
561 zalloc_cpumask_var(&c1e_mask, GFP_KERNEL);
564 static int __init idle_setup(char *str)
569 if (!strcmp(str, "poll")) {
570 printk("using polling idle threads.\n");
572 } else if (!strcmp(str, "mwait"))
574 else if (!strcmp(str, "halt")) {
576 * When the boot option of idle=halt is added, halt is
577 * forced to be used for CPU idle. In such case CPU C2/C3
578 * won't be used again.
579 * To continue to load the CPU idle driver, don't touch
580 * the boot_option_idle_override.
582 pm_idle = default_idle;
585 } else if (!strcmp(str, "nomwait")) {
587 * If the boot option of "idle=nomwait" is added,
588 * it means that mwait will be disabled for CPU C2/C3
589 * states. In such case it won't touch the variable
590 * of boot_option_idle_override.
597 boot_option_idle_override = 1;
600 early_param("idle", idle_setup);
602 unsigned long arch_align_stack(unsigned long sp)
604 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
605 sp -= get_random_int() % 8192;
609 unsigned long arch_randomize_brk(struct mm_struct *mm)
611 unsigned long range_end = mm->brk + 0x02000000;
612 return randomize_range(mm->brk, range_end, 0) ? : mm->brk;