2 * Dynamic DMA mapping support for AMD Hammer.
4 * Use the integrated AGP GART in the Hammer northbridge as an IOMMU for PCI.
5 * This allows to use PCI devices that only support 32bit addresses on systems
8 * See Documentation/DMA-mapping.txt for the interface specification.
10 * Copyright 2002 Andi Kleen, SuSE Labs.
11 * Subject to the GNU General Public License v2 only.
14 #include <linux/types.h>
15 #include <linux/ctype.h>
16 #include <linux/agp_backend.h>
17 #include <linux/init.h>
19 #include <linux/string.h>
20 #include <linux/spinlock.h>
21 #include <linux/pci.h>
22 #include <linux/module.h>
23 #include <linux/topology.h>
24 #include <linux/interrupt.h>
25 #include <linux/bitops.h>
26 #include <linux/kdebug.h>
27 #include <linux/scatterlist.h>
28 #include <linux/iommu-helper.h>
29 #include <linux/sysdev.h>
30 #include <asm/atomic.h>
33 #include <asm/pgtable.h>
34 #include <asm/proto.h>
35 #include <asm/iommu.h>
37 #include <asm/cacheflush.h>
38 #include <asm/swiotlb.h>
42 static unsigned long iommu_bus_base; /* GART remapping area (physical) */
43 static unsigned long iommu_size; /* size of remapping area bytes */
44 static unsigned long iommu_pages; /* .. and in pages */
46 static u32 *iommu_gatt_base; /* Remapping table */
48 /* Allocation bitmap for the remapping area: */
49 static DEFINE_SPINLOCK(iommu_bitmap_lock);
50 /* Guarded by iommu_bitmap_lock: */
51 static unsigned long *iommu_gart_bitmap;
53 static u32 gart_unmapped_entry;
56 #define GPTE_COHERENT 2
57 #define GPTE_ENCODE(x) \
58 (((x) & 0xfffff000) | (((x) >> 32) << 4) | GPTE_VALID | GPTE_COHERENT)
59 #define GPTE_DECODE(x) (((x) & 0xfffff000) | (((u64)(x) & 0xff0) << 28))
61 #define EMERGENCY_PAGES 32 /* = 128KB */
64 #define AGPEXTERN extern
69 /* backdoor interface to AGP driver */
70 AGPEXTERN int agp_memory_reserved;
71 AGPEXTERN __u32 *agp_gatt_table;
73 static unsigned long next_bit; /* protected by iommu_bitmap_lock */
74 static int need_flush; /* global flush state. set for each gart wrap */
76 static unsigned long alloc_iommu(struct device *dev, int size,
77 unsigned long align_mask, u64 dma_mask)
79 unsigned long offset, flags;
80 unsigned long boundary_size;
81 unsigned long base_index;
84 base_index = ALIGN(iommu_bus_base & dma_get_seg_boundary(dev),
85 PAGE_SIZE) >> PAGE_SHIFT;
86 boundary_size = ALIGN((unsigned long long)dma_get_seg_boundary(dev) + 1,
87 PAGE_SIZE) >> PAGE_SHIFT;
89 limit = iommu_device_max_index(iommu_pages,
90 DIV_ROUND_UP(iommu_bus_base, PAGE_SIZE),
91 dma_mask >> PAGE_SHIFT);
93 spin_lock_irqsave(&iommu_bitmap_lock, flags);
95 if (limit <= next_bit) {
100 offset = iommu_area_alloc(iommu_gart_bitmap, limit, next_bit,
101 size, base_index, boundary_size, align_mask);
102 if (offset == -1 && next_bit) {
104 offset = iommu_area_alloc(iommu_gart_bitmap, limit, 0,
105 size, base_index, boundary_size,
109 next_bit = offset+size;
110 if (next_bit >= iommu_pages) {
117 spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
122 static void free_iommu(unsigned long offset, int size)
126 spin_lock_irqsave(&iommu_bitmap_lock, flags);
127 iommu_area_free(iommu_gart_bitmap, offset, size);
128 spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
132 * Use global flush state to avoid races with multiple flushers.
134 static void flush_gart(void)
138 spin_lock_irqsave(&iommu_bitmap_lock, flags);
143 spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
146 #ifdef CONFIG_IOMMU_LEAK
148 #define SET_LEAK(x) \
150 if (iommu_leak_tab) \
151 iommu_leak_tab[x] = __builtin_return_address(0);\
154 #define CLEAR_LEAK(x) \
156 if (iommu_leak_tab) \
157 iommu_leak_tab[x] = NULL; \
160 /* Debugging aid for drivers that don't free their IOMMU tables */
161 static void **iommu_leak_tab;
162 static int leak_trace;
163 static int iommu_leak_pages = 20;
165 static void dump_leak(void)
170 if (dump || !iommu_leak_tab)
173 show_stack(NULL, NULL);
175 /* Very crude. dump some from the end of the table too */
176 printk(KERN_DEBUG "Dumping %d pages from end of IOMMU:\n",
178 for (i = 0; i < iommu_leak_pages; i += 2) {
179 printk(KERN_DEBUG "%lu: ", iommu_pages-i);
180 printk_address((unsigned long) iommu_leak_tab[iommu_pages-i], 0);
181 printk(KERN_CONT "%c", (i+1)%2 == 0 ? '\n' : ' ');
183 printk(KERN_DEBUG "\n");
187 # define CLEAR_LEAK(x)
190 static void iommu_full(struct device *dev, size_t size, int dir)
193 * Ran out of IOMMU space for this operation. This is very bad.
194 * Unfortunately the drivers cannot handle this operation properly.
195 * Return some non mapped prereserved space in the aperture and
196 * let the Northbridge deal with it. This will result in garbage
197 * in the IO operation. When the size exceeds the prereserved space
198 * memory corruption will occur or random memory will be DMAed
199 * out. Hopefully no network devices use single mappings that big.
202 dev_err(dev, "PCI-DMA: Out of IOMMU space for %lu bytes\n", size);
204 if (size > PAGE_SIZE*EMERGENCY_PAGES) {
205 if (dir == PCI_DMA_FROMDEVICE || dir == PCI_DMA_BIDIRECTIONAL)
206 panic("PCI-DMA: Memory would be corrupted\n");
207 if (dir == PCI_DMA_TODEVICE || dir == PCI_DMA_BIDIRECTIONAL)
209 "PCI-DMA: Random memory would be DMAed\n");
211 #ifdef CONFIG_IOMMU_LEAK
217 need_iommu(struct device *dev, unsigned long addr, size_t size)
219 return force_iommu ||
220 !is_buffer_dma_capable(*dev->dma_mask, addr, size);
224 nonforced_iommu(struct device *dev, unsigned long addr, size_t size)
226 return !is_buffer_dma_capable(*dev->dma_mask, addr, size);
229 /* Map a single continuous physical area into the IOMMU.
230 * Caller needs to check if the iommu is needed and flush.
232 static dma_addr_t dma_map_area(struct device *dev, dma_addr_t phys_mem,
233 size_t size, int dir, unsigned long align_mask,
236 unsigned long npages = iommu_num_pages(phys_mem, size);
237 unsigned long iommu_page;
240 iommu_page = alloc_iommu(dev, npages, align_mask, dma_mask);
241 if (iommu_page == -1) {
242 if (!nonforced_iommu(dev, phys_mem, size))
244 if (panic_on_overflow)
245 panic("dma_map_area overflow %lu bytes\n", size);
246 iommu_full(dev, size, dir);
247 return bad_dma_address;
250 for (i = 0; i < npages; i++) {
251 iommu_gatt_base[iommu_page + i] = GPTE_ENCODE(phys_mem);
252 SET_LEAK(iommu_page + i);
253 phys_mem += PAGE_SIZE;
255 return iommu_bus_base + iommu_page*PAGE_SIZE + (phys_mem & ~PAGE_MASK);
258 /* Map a single area into the IOMMU */
260 gart_map_single(struct device *dev, phys_addr_t paddr, size_t size, int dir)
265 dev = &x86_dma_fallback_dev;
267 if (!need_iommu(dev, paddr, size))
270 bus = dma_map_area(dev, paddr, size, dir, 0, dma_get_mask(dev));
277 * Free a DMA mapping.
279 static void gart_unmap_single(struct device *dev, dma_addr_t dma_addr,
280 size_t size, int direction)
282 unsigned long iommu_page;
286 if (dma_addr < iommu_bus_base + EMERGENCY_PAGES*PAGE_SIZE ||
287 dma_addr >= iommu_bus_base + iommu_size)
290 iommu_page = (dma_addr - iommu_bus_base)>>PAGE_SHIFT;
291 npages = iommu_num_pages(dma_addr, size);
292 for (i = 0; i < npages; i++) {
293 iommu_gatt_base[iommu_page + i] = gart_unmapped_entry;
294 CLEAR_LEAK(iommu_page + i);
296 free_iommu(iommu_page, npages);
300 * Wrapper for pci_unmap_single working with scatterlists.
303 gart_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, int dir)
305 struct scatterlist *s;
308 for_each_sg(sg, s, nents, i) {
309 if (!s->dma_length || !s->length)
311 gart_unmap_single(dev, s->dma_address, s->dma_length, dir);
315 /* Fallback for dma_map_sg in case of overflow */
316 static int dma_map_sg_nonforce(struct device *dev, struct scatterlist *sg,
319 struct scatterlist *s;
321 u64 dma_mask = dma_get_mask(dev);
323 #ifdef CONFIG_IOMMU_DEBUG
324 printk(KERN_DEBUG "dma_map_sg overflow\n");
327 for_each_sg(sg, s, nents, i) {
328 unsigned long addr = sg_phys(s);
330 if (nonforced_iommu(dev, addr, s->length)) {
331 addr = dma_map_area(dev, addr, s->length, dir, 0,
333 if (addr == bad_dma_address) {
335 gart_unmap_sg(dev, sg, i, dir);
337 sg[0].dma_length = 0;
341 s->dma_address = addr;
342 s->dma_length = s->length;
349 /* Map multiple scatterlist entries continuous into the first. */
350 static int __dma_map_cont(struct device *dev, struct scatterlist *start,
351 int nelems, struct scatterlist *sout,
354 unsigned long iommu_start;
355 unsigned long iommu_page;
356 struct scatterlist *s;
359 iommu_start = alloc_iommu(dev, pages, 0, dma_get_mask(dev));
360 if (iommu_start == -1)
363 iommu_page = iommu_start;
364 for_each_sg(start, s, nelems, i) {
365 unsigned long pages, addr;
366 unsigned long phys_addr = s->dma_address;
368 BUG_ON(s != start && s->offset);
370 sout->dma_address = iommu_bus_base;
371 sout->dma_address += iommu_page*PAGE_SIZE + s->offset;
372 sout->dma_length = s->length;
374 sout->dma_length += s->length;
378 pages = iommu_num_pages(s->offset, s->length);
380 iommu_gatt_base[iommu_page] = GPTE_ENCODE(addr);
381 SET_LEAK(iommu_page);
386 BUG_ON(iommu_page - iommu_start != pages);
392 dma_map_cont(struct device *dev, struct scatterlist *start, int nelems,
393 struct scatterlist *sout, unsigned long pages, int need)
397 sout->dma_address = start->dma_address;
398 sout->dma_length = start->length;
401 return __dma_map_cont(dev, start, nelems, sout, pages);
405 * DMA map all entries in a scatterlist.
406 * Merge chunks that have page aligned sizes into a continuous mapping.
409 gart_map_sg(struct device *dev, struct scatterlist *sg, int nents, int dir)
411 struct scatterlist *s, *ps, *start_sg, *sgmap;
412 int need = 0, nextneed, i, out, start;
413 unsigned long pages = 0;
414 unsigned int seg_size;
415 unsigned int max_seg_size;
421 dev = &x86_dma_fallback_dev;
425 start_sg = sgmap = sg;
427 max_seg_size = dma_get_max_seg_size(dev);
428 ps = NULL; /* shut up gcc */
429 for_each_sg(sg, s, nents, i) {
430 dma_addr_t addr = sg_phys(s);
432 s->dma_address = addr;
433 BUG_ON(s->length == 0);
435 nextneed = need_iommu(dev, addr, s->length);
437 /* Handle the previous not yet processed entries */
440 * Can only merge when the last chunk ends on a
441 * page boundary and the new one doesn't have an
444 if (!iommu_merge || !nextneed || !need || s->offset ||
445 (s->length + seg_size > max_seg_size) ||
446 (ps->offset + ps->length) % PAGE_SIZE) {
447 if (dma_map_cont(dev, start_sg, i - start,
448 sgmap, pages, need) < 0)
452 sgmap = sg_next(sgmap);
459 seg_size += s->length;
461 pages += iommu_num_pages(s->offset, s->length);
464 if (dma_map_cont(dev, start_sg, i - start, sgmap, pages, need) < 0)
469 sgmap = sg_next(sgmap);
470 sgmap->dma_length = 0;
476 gart_unmap_sg(dev, sg, out, dir);
478 /* When it was forced or merged try again in a dumb way */
479 if (force_iommu || iommu_merge) {
480 out = dma_map_sg_nonforce(dev, sg, nents, dir);
484 if (panic_on_overflow)
485 panic("dma_map_sg: overflow on %lu pages\n", pages);
487 iommu_full(dev, pages << PAGE_SHIFT, dir);
488 for_each_sg(sg, s, nents, i)
489 s->dma_address = bad_dma_address;
493 /* allocate and map a coherent mapping */
495 gart_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_addr,
500 unsigned long align_mask;
501 u64 dma_mask = dma_alloc_coherent_mask(dev, flag);
503 vaddr = (void *)__get_free_pages(flag | __GFP_ZERO, get_order(size));
507 paddr = virt_to_phys(vaddr);
508 if (is_buffer_dma_capable(dma_mask, paddr, size)) {
513 align_mask = (1UL << get_order(size)) - 1;
515 *dma_addr = dma_map_area(dev, paddr, size, DMA_BIDIRECTIONAL,
516 align_mask, dma_mask);
519 if (*dma_addr != bad_dma_address)
522 free_pages((unsigned long)vaddr, get_order(size));
527 /* free a coherent mapping */
529 gart_free_coherent(struct device *dev, size_t size, void *vaddr,
532 gart_unmap_single(dev, dma_addr, size, DMA_BIDIRECTIONAL);
533 free_pages((unsigned long)vaddr, get_order(size));
538 static __init unsigned long check_iommu_size(unsigned long aper, u64 aper_size)
543 iommu_size = aper_size;
548 a = aper + iommu_size;
549 iommu_size -= round_up(a, PMD_PAGE_SIZE) - a;
551 if (iommu_size < 64*1024*1024) {
553 "PCI-DMA: Warning: Small IOMMU %luMB."
554 " Consider increasing the AGP aperture in BIOS\n",
561 static __init unsigned read_aperture(struct pci_dev *dev, u32 *size)
563 unsigned aper_size = 0, aper_base_32, aper_order;
566 pci_read_config_dword(dev, AMD64_GARTAPERTUREBASE, &aper_base_32);
567 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &aper_order);
568 aper_order = (aper_order >> 1) & 7;
570 aper_base = aper_base_32 & 0x7fff;
573 aper_size = (32 * 1024 * 1024) << aper_order;
574 if (aper_base + aper_size > 0x100000000UL || !aper_size)
581 static void enable_gart_translations(void)
585 for (i = 0; i < num_k8_northbridges; i++) {
586 struct pci_dev *dev = k8_northbridges[i];
588 enable_gart_translation(dev, __pa(agp_gatt_table));
593 * If fix_up_north_bridges is set, the north bridges have to be fixed up on
594 * resume in the same way as they are handled in gart_iommu_hole_init().
596 static bool fix_up_north_bridges;
597 static u32 aperture_order;
598 static u32 aperture_alloc;
600 void set_up_gart_resume(u32 aper_order, u32 aper_alloc)
602 fix_up_north_bridges = true;
603 aperture_order = aper_order;
604 aperture_alloc = aper_alloc;
607 static int gart_resume(struct sys_device *dev)
609 printk(KERN_INFO "PCI-DMA: Resuming GART IOMMU\n");
611 if (fix_up_north_bridges) {
614 printk(KERN_INFO "PCI-DMA: Restoring GART aperture settings\n");
616 for (i = 0; i < num_k8_northbridges; i++) {
617 struct pci_dev *dev = k8_northbridges[i];
620 * Don't enable translations just yet. That is the next
621 * step. Restore the pre-suspend aperture settings.
623 pci_write_config_dword(dev, AMD64_GARTAPERTURECTL,
624 aperture_order << 1);
625 pci_write_config_dword(dev, AMD64_GARTAPERTUREBASE,
626 aperture_alloc >> 25);
630 enable_gart_translations();
635 static int gart_suspend(struct sys_device *dev, pm_message_t state)
640 static struct sysdev_class gart_sysdev_class = {
642 .suspend = gart_suspend,
643 .resume = gart_resume,
647 static struct sys_device device_gart = {
649 .cls = &gart_sysdev_class,
653 * Private Northbridge GATT initialization in case we cannot use the
654 * AGP driver for some reason.
656 static __init int init_k8_gatt(struct agp_kern_info *info)
658 unsigned aper_size, gatt_size, new_aper_size;
659 unsigned aper_base, new_aper_base;
663 unsigned long start_pfn, end_pfn;
665 printk(KERN_INFO "PCI-DMA: Disabling AGP.\n");
666 aper_size = aper_base = info->aper_size = 0;
668 for (i = 0; i < num_k8_northbridges; i++) {
669 dev = k8_northbridges[i];
670 new_aper_base = read_aperture(dev, &new_aper_size);
675 aper_size = new_aper_size;
676 aper_base = new_aper_base;
678 if (aper_size != new_aper_size || aper_base != new_aper_base)
683 info->aper_base = aper_base;
684 info->aper_size = aper_size >> 20;
686 gatt_size = (aper_size >> PAGE_SHIFT) * sizeof(u32);
687 gatt = (void *)__get_free_pages(GFP_KERNEL, get_order(gatt_size));
689 panic("Cannot allocate GATT table");
690 if (set_memory_uc((unsigned long)gatt, gatt_size >> PAGE_SHIFT))
691 panic("Could not set GART PTEs to uncacheable pages");
693 memset(gatt, 0, gatt_size);
694 agp_gatt_table = gatt;
696 enable_gart_translations();
698 error = sysdev_class_register(&gart_sysdev_class);
700 error = sysdev_register(&device_gart);
702 panic("Could not register gart_sysdev -- would corrupt data on next suspend");
706 printk(KERN_INFO "PCI-DMA: aperture base @ %x size %u KB\n",
707 aper_base, aper_size>>10);
709 /* need to map that range */
710 end_pfn = (aper_base>>PAGE_SHIFT) + (aper_size>>PAGE_SHIFT);
711 if (end_pfn > max_low_pfn_mapped) {
712 start_pfn = (aper_base>>PAGE_SHIFT);
713 init_memory_mapping(start_pfn<<PAGE_SHIFT, end_pfn<<PAGE_SHIFT);
718 /* Should not happen anymore */
719 printk(KERN_WARNING "PCI-DMA: More than 4GB of RAM and no IOMMU\n"
720 KERN_WARNING "falling back to iommu=soft.\n");
724 extern int agp_amd64_init(void);
726 static struct dma_mapping_ops gart_dma_ops = {
727 .map_single = gart_map_single,
728 .unmap_single = gart_unmap_single,
729 .sync_single_for_cpu = NULL,
730 .sync_single_for_device = NULL,
731 .sync_single_range_for_cpu = NULL,
732 .sync_single_range_for_device = NULL,
733 .sync_sg_for_cpu = NULL,
734 .sync_sg_for_device = NULL,
735 .map_sg = gart_map_sg,
736 .unmap_sg = gart_unmap_sg,
737 .alloc_coherent = gart_alloc_coherent,
738 .free_coherent = gart_free_coherent,
741 void gart_iommu_shutdown(void)
746 if (no_agp && (dma_ops != &gart_dma_ops))
749 for (i = 0; i < num_k8_northbridges; i++) {
752 dev = k8_northbridges[i];
753 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl);
757 pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);
761 void __init gart_iommu_init(void)
763 struct agp_kern_info info;
764 unsigned long iommu_start;
765 unsigned long aper_size;
766 unsigned long scratch;
769 if (cache_k8_northbridges() < 0 || num_k8_northbridges == 0) {
770 printk(KERN_INFO "PCI-GART: No AMD northbridge found.\n");
774 #ifndef CONFIG_AGP_AMD64
777 /* Makefile puts PCI initialization via subsys_initcall first. */
778 /* Add other K8 AGP bridge drivers here */
780 (agp_amd64_init() < 0) ||
781 (agp_copy_info(agp_bridge, &info) < 0);
787 /* Did we detect a different HW IOMMU? */
788 if (iommu_detected && !gart_iommu_aperture)
792 (!force_iommu && max_pfn <= MAX_DMA32_PFN) ||
793 !gart_iommu_aperture ||
794 (no_agp && init_k8_gatt(&info) < 0)) {
795 if (max_pfn > MAX_DMA32_PFN) {
796 printk(KERN_WARNING "More than 4GB of memory "
797 "but GART IOMMU not available.\n"
798 KERN_WARNING "falling back to iommu=soft.\n");
803 printk(KERN_INFO "PCI-DMA: using GART IOMMU.\n");
804 aper_size = info.aper_size * 1024 * 1024;
805 iommu_size = check_iommu_size(info.aper_base, aper_size);
806 iommu_pages = iommu_size >> PAGE_SHIFT;
808 iommu_gart_bitmap = (void *) __get_free_pages(GFP_KERNEL,
809 get_order(iommu_pages/8));
810 if (!iommu_gart_bitmap)
811 panic("Cannot allocate iommu bitmap\n");
812 memset(iommu_gart_bitmap, 0, iommu_pages/8);
814 #ifdef CONFIG_IOMMU_LEAK
816 iommu_leak_tab = (void *)__get_free_pages(GFP_KERNEL,
817 get_order(iommu_pages*sizeof(void *)));
819 memset(iommu_leak_tab, 0, iommu_pages * 8);
822 "PCI-DMA: Cannot allocate leak trace area\n");
827 * Out of IOMMU space handling.
828 * Reserve some invalid pages at the beginning of the GART.
830 iommu_area_reserve(iommu_gart_bitmap, 0, EMERGENCY_PAGES);
832 agp_memory_reserved = iommu_size;
834 "PCI-DMA: Reserving %luMB of IOMMU area in the AGP aperture\n",
837 iommu_start = aper_size - iommu_size;
838 iommu_bus_base = info.aper_base + iommu_start;
839 bad_dma_address = iommu_bus_base;
840 iommu_gatt_base = agp_gatt_table + (iommu_start>>PAGE_SHIFT);
843 * Unmap the IOMMU part of the GART. The alias of the page is
844 * always mapped with cache enabled and there is no full cache
845 * coherency across the GART remapping. The unmapping avoids
846 * automatic prefetches from the CPU allocating cache lines in
847 * there. All CPU accesses are done via the direct mapping to
848 * the backing memory. The GART address is only used by PCI
851 set_memory_np((unsigned long)__va(iommu_bus_base),
852 iommu_size >> PAGE_SHIFT);
854 * Tricky. The GART table remaps the physical memory range,
855 * so the CPU wont notice potential aliases and if the memory
856 * is remapped to UC later on, we might surprise the PCI devices
857 * with a stray writeout of a cacheline. So play it sure and
858 * do an explicit, full-scale wbinvd() _after_ having marked all
859 * the pages as Not-Present:
864 * Try to workaround a bug (thanks to BenH):
865 * Set unmapped entries to a scratch page instead of 0.
866 * Any prefetches that hit unmapped entries won't get an bus abort
867 * then. (P2P bridge may be prefetching on DMA reads).
869 scratch = get_zeroed_page(GFP_KERNEL);
871 panic("Cannot allocate iommu scratch page");
872 gart_unmapped_entry = GPTE_ENCODE(__pa(scratch));
873 for (i = EMERGENCY_PAGES; i < iommu_pages; i++)
874 iommu_gatt_base[i] = gart_unmapped_entry;
877 dma_ops = &gart_dma_ops;
880 void __init gart_parse_options(char *p)
884 #ifdef CONFIG_IOMMU_LEAK
885 if (!strncmp(p, "leak", 4)) {
889 if (isdigit(*p) && get_option(&p, &arg))
890 iommu_leak_pages = arg;
893 if (isdigit(*p) && get_option(&p, &arg))
895 if (!strncmp(p, "noagp", 5))
897 if (!strncmp(p, "noaperture", 10))
899 /* duplicated from pci-dma.c */
900 if (!strncmp(p, "force", 5))
901 gart_iommu_aperture_allowed = 1;
902 if (!strncmp(p, "allowed", 7))
903 gart_iommu_aperture_allowed = 1;
904 if (!strncmp(p, "memaper", 7)) {
905 fallback_aper_force = 1;
909 if (get_option(&p, &arg))
910 fallback_aper_order = arg;