1 #include <linux/linkage.h>
2 #include <linux/errno.h>
3 #include <linux/signal.h>
4 #include <linux/sched.h>
5 #include <linux/ioport.h>
6 #include <linux/interrupt.h>
7 #include <linux/timex.h>
8 #include <linux/slab.h>
9 #include <linux/random.h>
10 #include <linux/init.h>
11 #include <linux/kernel_stat.h>
12 #include <linux/sysdev.h>
13 #include <linux/bitops.h>
16 #include <asm/atomic.h>
17 #include <asm/system.h>
19 #include <asm/timer.h>
20 #include <asm/hw_irq.h>
21 #include <asm/pgtable.h>
22 #include <asm/delay.h>
25 #include <asm/arch_hooks.h>
26 #include <asm/i8259.h>
29 * This is the 'legacy' 8259A Programmable Interrupt Controller,
30 * present in the majority of PC/AT boxes.
31 * plus some generic x86 specific things if generic specifics makes
35 static int i8259A_auto_eoi;
36 DEFINE_SPINLOCK(i8259A_lock);
37 static void mask_and_ack_8259A(unsigned int);
39 struct irq_chip i8259A_chip = {
41 .mask = disable_8259A_irq,
42 .disable = disable_8259A_irq,
43 .unmask = enable_8259A_irq,
44 .mask_ack = mask_and_ack_8259A,
48 * 8259A PIC functions to handle ISA devices:
52 * This contains the irq mask for both 8259A irq controllers,
54 unsigned int cached_irq_mask = 0xffff;
57 * Not all IRQs can be routed through the IO-APIC, eg. on certain (older)
58 * boards the timer interrupt is not really connected to any IO-APIC pin,
59 * it's fed to the master 8259A's IR0 line only.
61 * Any '1' bit in this mask means the IRQ is routed through the IO-APIC.
62 * this 'mixed mode' IRQ handling costs nothing because it's only used
65 unsigned long io_apic_irqs;
67 void disable_8259A_irq(unsigned int irq)
69 unsigned int mask = 1 << irq;
72 spin_lock_irqsave(&i8259A_lock, flags);
73 cached_irq_mask |= mask;
75 outb(cached_slave_mask, PIC_SLAVE_IMR);
77 outb(cached_master_mask, PIC_MASTER_IMR);
78 spin_unlock_irqrestore(&i8259A_lock, flags);
81 void enable_8259A_irq(unsigned int irq)
83 unsigned int mask = ~(1 << irq);
86 spin_lock_irqsave(&i8259A_lock, flags);
87 cached_irq_mask &= mask;
89 outb(cached_slave_mask, PIC_SLAVE_IMR);
91 outb(cached_master_mask, PIC_MASTER_IMR);
92 spin_unlock_irqrestore(&i8259A_lock, flags);
95 int i8259A_irq_pending(unsigned int irq)
97 unsigned int mask = 1<<irq;
101 spin_lock_irqsave(&i8259A_lock, flags);
103 ret = inb(PIC_MASTER_CMD) & mask;
105 ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
106 spin_unlock_irqrestore(&i8259A_lock, flags);
111 void make_8259A_irq(unsigned int irq)
113 disable_irq_nosync(irq);
114 io_apic_irqs &= ~(1<<irq);
115 set_irq_chip_and_handler_name(irq, &i8259A_chip, handle_level_irq,
121 * This function assumes to be called rarely. Switching between
122 * 8259A registers is slow.
123 * This has to be protected by the irq controller spinlock
124 * before being called.
126 static inline int i8259A_irq_real(unsigned int irq)
129 int irqmask = 1<<irq;
132 outb(0x0B,PIC_MASTER_CMD); /* ISR register */
133 value = inb(PIC_MASTER_CMD) & irqmask;
134 outb(0x0A,PIC_MASTER_CMD); /* back to the IRR register */
137 outb(0x0B,PIC_SLAVE_CMD); /* ISR register */
138 value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
139 outb(0x0A,PIC_SLAVE_CMD); /* back to the IRR register */
144 * Careful! The 8259A is a fragile beast, it pretty
145 * much _has_ to be done exactly like this (mask it
146 * first, _then_ send the EOI, and the order of EOI
147 * to the two 8259s is important!
149 static void mask_and_ack_8259A(unsigned int irq)
151 unsigned int irqmask = 1 << irq;
154 spin_lock_irqsave(&i8259A_lock, flags);
156 * Lightweight spurious IRQ detection. We do not want
157 * to overdo spurious IRQ handling - it's usually a sign
158 * of hardware problems, so we only do the checks we can
159 * do without slowing down good hardware unnecessarily.
161 * Note that IRQ7 and IRQ15 (the two spurious IRQs
162 * usually resulting from the 8259A-1|2 PICs) occur
163 * even if the IRQ is masked in the 8259A. Thus we
164 * can check spurious 8259A IRQs without doing the
165 * quite slow i8259A_irq_real() call for every IRQ.
166 * This does not cover 100% of spurious interrupts,
167 * but should be enough to warn the user that there
168 * is something bad going on ...
170 if (cached_irq_mask & irqmask)
171 goto spurious_8259A_irq;
172 cached_irq_mask |= irqmask;
176 inb(PIC_SLAVE_IMR); /* DUMMY - (do we need this?) */
177 outb(cached_slave_mask, PIC_SLAVE_IMR);
178 #ifndef CONFIG_X86_64
179 outb(0x60+(irq&7),PIC_SLAVE_CMD);/* 'Specific EOI' to slave */
180 outb(0x60+PIC_CASCADE_IR,PIC_MASTER_CMD); /* 'Specific EOI' to master-IRQ2 */
181 #else /* CONFIG_X86_64 */
182 /* 'Specific EOI' to slave */
183 outb(0x60+(irq&7),PIC_SLAVE_CMD);
184 /* 'Specific EOI' to master-IRQ2 */
185 outb(0x60+PIC_CASCADE_IR,PIC_MASTER_CMD);
186 #endif /* CONFIG_X86_64 */
188 inb(PIC_MASTER_IMR); /* DUMMY - (do we need this?) */
189 outb(cached_master_mask, PIC_MASTER_IMR);
190 #ifndef CONFIG_X86_64
191 outb(0x60+irq,PIC_MASTER_CMD); /* 'Specific EOI to master */
192 #else /* CONFIG_X86_64 */
193 /* 'Specific EOI' to master */
194 outb(0x60+irq,PIC_MASTER_CMD);
195 #endif /* CONFIG_X86_64 */
197 spin_unlock_irqrestore(&i8259A_lock, flags);
202 * this is the slow path - should happen rarely.
204 if (i8259A_irq_real(irq))
206 * oops, the IRQ _is_ in service according to the
207 * 8259A - not spurious, go handle it.
209 goto handle_real_irq;
212 static int spurious_irq_mask;
214 * At this point we can be sure the IRQ is spurious,
215 * lets ACK and report it. [once per IRQ]
217 if (!(spurious_irq_mask & irqmask)) {
218 #ifndef CONFIG_X86_64
219 printk(KERN_DEBUG "spurious 8259A interrupt: IRQ%d.\n", irq);
220 #else /* CONFIG_X86_64 */
222 "spurious 8259A interrupt: IRQ%d.\n", irq);
223 #endif /* CONFIG_X86_64 */
224 spurious_irq_mask |= irqmask;
226 atomic_inc(&irq_err_count);
228 * Theoretically we do not have to handle this IRQ,
229 * but in Linux this does not cause problems and is
232 goto handle_real_irq;
236 static char irq_trigger[2];
238 * ELCR registers (0x4d0, 0x4d1) control edge/level of IRQ
240 static void restore_ELCR(char *trigger)
242 outb(trigger[0], 0x4d0);
243 outb(trigger[1], 0x4d1);
246 static void save_ELCR(char *trigger)
248 /* IRQ 0,1,2,8,13 are marked as reserved */
249 trigger[0] = inb(0x4d0) & 0xF8;
250 trigger[1] = inb(0x4d1) & 0xDE;
253 static int i8259A_resume(struct sys_device *dev)
255 init_8259A(i8259A_auto_eoi);
256 restore_ELCR(irq_trigger);
260 static int i8259A_suspend(struct sys_device *dev, pm_message_t state)
262 save_ELCR(irq_trigger);
266 static int i8259A_shutdown(struct sys_device *dev)
268 /* Put the i8259A into a quiescent state that
269 * the kernel initialization code can get it
272 outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
273 outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-1 */
277 static struct sysdev_class i8259_sysdev_class = {
279 .suspend = i8259A_suspend,
280 .resume = i8259A_resume,
281 .shutdown = i8259A_shutdown,
284 static struct sys_device device_i8259A = {
286 .cls = &i8259_sysdev_class,
289 static int __init i8259A_init_sysfs(void)
291 int error = sysdev_class_register(&i8259_sysdev_class);
293 error = sysdev_register(&device_i8259A);
297 device_initcall(i8259A_init_sysfs);
299 void init_8259A(int auto_eoi)
303 i8259A_auto_eoi = auto_eoi;
305 spin_lock_irqsave(&i8259A_lock, flags);
307 outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
308 outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
311 * outb_pic - this has to work on a wide range of PC hardware.
313 outb_pic(0x11, PIC_MASTER_CMD); /* ICW1: select 8259A-1 init */
314 #ifndef CONFIG_X86_64
315 outb_pic(0x20 + 0, PIC_MASTER_IMR); /* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */
316 outb_pic(1U << PIC_CASCADE_IR, PIC_MASTER_IMR); /* 8259A-1 (the master) has a slave on IR2 */
317 #else /* CONFIG_X86_64 */
318 /* ICW2: 8259A-1 IR0-7 mapped to 0x30-0x37 */
319 outb_pic(IRQ0_VECTOR, PIC_MASTER_IMR);
320 /* 8259A-1 (the master) has a slave on IR2 */
321 outb_pic(0x04, PIC_MASTER_IMR);
322 #endif /* CONFIG_X86_64 */
323 if (auto_eoi) /* master does Auto EOI */
324 outb_pic(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR);
325 else /* master expects normal EOI */
326 outb_pic(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);
328 outb_pic(0x11, PIC_SLAVE_CMD); /* ICW1: select 8259A-2 init */
329 #ifndef CONFIG_X86_64
330 outb_pic(0x20 + 8, PIC_SLAVE_IMR); /* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */
331 outb_pic(PIC_CASCADE_IR, PIC_SLAVE_IMR); /* 8259A-2 is a slave on master's IR2 */
332 outb_pic(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR); /* (slave's support for AEOI in flat mode is to be investigated) */
333 #else /* CONFIG_X86_64 */
334 /* ICW2: 8259A-2 IR0-7 mapped to 0x38-0x3f */
335 outb_pic(IRQ8_VECTOR, PIC_SLAVE_IMR);
336 /* 8259A-2 is a slave on master's IR2 */
337 outb_pic(PIC_CASCADE_IR, PIC_SLAVE_IMR);
338 /* (slave's support for AEOI in flat mode is to be investigated) */
339 outb_pic(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR);
341 #endif /* CONFIG_X86_64 */
344 * In AEOI mode we just have to mask the interrupt
347 i8259A_chip.mask_ack = disable_8259A_irq;
349 i8259A_chip.mask_ack = mask_and_ack_8259A;
351 udelay(100); /* wait for 8259A to initialize */
353 outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
354 outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */
356 spin_unlock_irqrestore(&i8259A_lock, flags);