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   1 /*
   2  * Performance events x86 architecture code
   3  *
   4  *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
   5  *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
   6  *  Copyright (C) 2009 Jaswinder Singh Rajput
   7  *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
   8  *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
   9  *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
  10  *  Copyright (C) 2009 Google, Inc., Stephane Eranian
  11  *
  12  *  For licencing details see kernel-base/COPYING
  13  */
  14
  15 #include <linux/perf_event.h>
  16 #include <linux/capability.h>
  17 #include <linux/notifier.h>
  18 #include <linux/hardirq.h>
  19 #include <linux/kprobes.h>
  20 #include <linux/module.h>
  21 #include <linux/kdebug.h>
  22 #include <linux/sched.h>
  23 #include <linux/uaccess.h>
  24 #include <linux/highmem.h>
  25 #include <linux/cpu.h>
  26 #include <linux/bitops.h>
  27
  28 #include <asm/apic.h>
  29 #include <asm/stacktrace.h>
  30 #include <asm/nmi.h>
  31
  32 static u64 perf_event_mask __read_mostly;
  33
  34 /* The maximal number of PEBS events: */
  35 #define MAX_PEBS_EVENTS 4
  36
  37 /* The size of a BTS record in bytes: */
  38 #define BTS_RECORD_SIZE         24
  39
  40 /* The size of a per-cpu BTS buffer in bytes: */
  41 #define BTS_BUFFER_SIZE         (BTS_RECORD_SIZE * 2048)
  42
  43 /* The BTS overflow threshold in bytes from the end of the buffer: */
  44 #define BTS_OVFL_TH             (BTS_RECORD_SIZE * 128)
  45
  46
  47 /*
  48  * Bits in the debugctlmsr controlling branch tracing.
  49  */
  50 #define X86_DEBUGCTL_TR                 (1 << 6)
  51 #define X86_DEBUGCTL_BTS                (1 << 7)
  52 #define X86_DEBUGCTL_BTINT              (1 << 8)
  53 #define X86_DEBUGCTL_BTS_OFF_OS         (1 << 9)
  54 #define X86_DEBUGCTL_BTS_OFF_USR        (1 << 10)
  55
  56 /*
  57  * A debug store configuration.
  58  *
  59  * We only support architectures that use 64bit fields.
  60  */
  61 struct debug_store {
  62         u64     bts_buffer_base;
  63         u64     bts_index;
  64         u64     bts_absolute_maximum;
  65         u64     bts_interrupt_threshold;
  66         u64     pebs_buffer_base;
  67         u64     pebs_index;
  68         u64     pebs_absolute_maximum;
  69         u64     pebs_interrupt_threshold;
  70         u64     pebs_event_reset[MAX_PEBS_EVENTS];
  71 };
  72
  73 struct event_constraint {
  74         union {
  75                 unsigned long   idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
  76                 u64             idxmsk64;
  77         };
  78         u64     code;
  79         u64     cmask;
  80         int     weight;
  81 };
  82
  83 struct amd_nb {
  84         int nb_id;  /* NorthBridge id */
  85         int refcnt; /* reference count */
  86         struct perf_event *owners[X86_PMC_IDX_MAX];
  87         struct event_constraint event_constraints[X86_PMC_IDX_MAX];
  88 };
  89
  90 struct cpu_hw_events {
  91         struct perf_event       *events[X86_PMC_IDX_MAX]; /* in counter order */
  92         unsigned long           active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
  93         unsigned long           interrupts;
  94         int                     enabled;
  95         struct debug_store      *ds;
  96
  97         int                     n_events;
  98         int                     n_added;
  99         int                     assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
 100         u64                     tags[X86_PMC_IDX_MAX];
 101         struct perf_event       *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
 102         struct amd_nb           *amd_nb;
 103 };
 104
 105 #define __EVENT_CONSTRAINT(c, n, m, w) {\
 106         { .idxmsk64 = (n) },            \
 107         .code = (c),                    \
 108         .cmask = (m),                   \
 109         .weight = (w),                  \
 110 }
 111
 112 #define EVENT_CONSTRAINT(c, n, m)       \
 113         __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n))
 114
 115 #define INTEL_EVENT_CONSTRAINT(c, n)    \
 116         EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVTSEL_MASK)
 117
 118 #define FIXED_EVENT_CONSTRAINT(c, n)    \
 119         EVENT_CONSTRAINT(c, (1ULL << (32+n)), INTEL_ARCH_FIXED_MASK)
 120
 121 #define EVENT_CONSTRAINT_END            \
 122         EVENT_CONSTRAINT(0, 0, 0)
 123
 124 #define for_each_event_constraint(e, c) \
 125         for ((e) = (c); (e)->cmask; (e)++)
 126
 127 /*
 128  * struct x86_pmu - generic x86 pmu
 129  */
 130 struct x86_pmu {
 131         const char      *name;
 132         int             version;
 133         int             (*handle_irq)(struct pt_regs *);
 134         void            (*disable_all)(void);
 135         void            (*enable_all)(void);
 136         void            (*enable)(struct hw_perf_event *, int);
 137         void            (*disable)(struct hw_perf_event *, int);
 138         unsigned        eventsel;
 139         unsigned        perfctr;
 140         u64             (*event_map)(int);
 141         u64             (*raw_event)(u64);
 142         int             max_events;
 143         int             num_events;
 144         int             num_events_fixed;
 145         int             event_bits;
 146         u64             event_mask;
 147         int             apic;
 148         u64             max_period;
 149         u64             intel_ctrl;
 150         void            (*enable_bts)(u64 config);
 151         void            (*disable_bts)(void);
 152
 153         struct event_constraint *
 154                         (*get_event_constraints)(struct cpu_hw_events *cpuc,
 155                                                  struct perf_event *event);
 156
 157         void            (*put_event_constraints)(struct cpu_hw_events *cpuc,
 158                                                  struct perf_event *event);
 159         struct event_constraint *event_constraints;
 160 };
 161
 162 static struct x86_pmu x86_pmu __read_mostly;
 163
 164 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
 165         .enabled = 1,
 166 };
 167
 168 static int x86_perf_event_set_period(struct perf_event *event,
 169                              struct hw_perf_event *hwc, int idx);
 170
 171 /*
 172  * Generalized hw caching related hw_event table, filled
 173  * in on a per model basis. A value of 0 means
 174  * 'not supported', -1 means 'hw_event makes no sense on
 175  * this CPU', any other value means the raw hw_event
 176  * ID.
 177  */
 178
 179 #define C(x) PERF_COUNT_HW_CACHE_##x
 180
 181 static u64 __read_mostly hw_cache_event_ids
 182                                 [PERF_COUNT_HW_CACHE_MAX]
 183                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 184                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
 185
 186 /*
 187  * Propagate event elapsed time into the generic event.
 188  * Can only be executed on the CPU where the event is active.
 189  * Returns the delta events processed.
 190  */
 191 static u64
 192 x86_perf_event_update(struct perf_event *event,
 193                         struct hw_perf_event *hwc, int idx)
 194 {
 195         int shift = 64 - x86_pmu.event_bits;
 196         u64 prev_raw_count, new_raw_count;
 197         s64 delta;
 198
 199         if (idx == X86_PMC_IDX_FIXED_BTS)
 200                 return 0;
 201
 202         /*
 203          * Careful: an NMI might modify the previous event value.
 204          *
 205          * Our tactic to handle this is to first atomically read and
 206          * exchange a new raw count - then add that new-prev delta
 207          * count to the generic event atomically:
 208          */
 209 again:
 210         prev_raw_count = atomic64_read(&hwc->prev_count);
 211         rdmsrl(hwc->event_base + idx, new_raw_count);
 212
 213         if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
 214                                         new_raw_count) != prev_raw_count)
 215                 goto again;
 216
 217         /*
 218          * Now we have the new raw value and have updated the prev
 219          * timestamp already. We can now calculate the elapsed delta
 220          * (event-)time and add that to the generic event.
 221          *
 222          * Careful, not all hw sign-extends above the physical width
 223          * of the count.
 224          */
 225         delta = (new_raw_count << shift) - (prev_raw_count << shift);
 226         delta >>= shift;
 227
 228         atomic64_add(delta, &event->count);
 229         atomic64_sub(delta, &hwc->period_left);
 230
 231         return new_raw_count;
 232 }
 233
 234 static atomic_t active_events;
 235 static DEFINE_MUTEX(pmc_reserve_mutex);
 236
 237 static bool reserve_pmc_hardware(void)
 238 {
 239 #ifdef CONFIG_X86_LOCAL_APIC
 240         int i;
 241
 242         if (nmi_watchdog == NMI_LOCAL_APIC)
 243                 disable_lapic_nmi_watchdog();
 244
 245         for (i = 0; i < x86_pmu.num_events; i++) {
 246                 if (!reserve_perfctr_nmi(x86_pmu.perfctr + i))
 247                         goto perfctr_fail;
 248         }
 249
 250         for (i = 0; i < x86_pmu.num_events; i++) {
 251                 if (!reserve_evntsel_nmi(x86_pmu.eventsel + i))
 252                         goto eventsel_fail;
 253         }
 254 #endif
 255
 256         return true;
 257
 258 #ifdef CONFIG_X86_LOCAL_APIC
 259 eventsel_fail:
 260         for (i--; i >= 0; i--)
 261                 release_evntsel_nmi(x86_pmu.eventsel + i);
 262
 263         i = x86_pmu.num_events;
 264
 265 perfctr_fail:
 266         for (i--; i >= 0; i--)
 267                 release_perfctr_nmi(x86_pmu.perfctr + i);
 268
 269         if (nmi_watchdog == NMI_LOCAL_APIC)
 270                 enable_lapic_nmi_watchdog();
 271
 272         return false;
 273 #endif
 274 }
 275
 276 static void release_pmc_hardware(void)
 277 {
 278 #ifdef CONFIG_X86_LOCAL_APIC
 279         int i;
 280
 281         for (i = 0; i < x86_pmu.num_events; i++) {
 282                 release_perfctr_nmi(x86_pmu.perfctr + i);
 283                 release_evntsel_nmi(x86_pmu.eventsel + i);
 284         }
 285
 286         if (nmi_watchdog == NMI_LOCAL_APIC)
 287                 enable_lapic_nmi_watchdog();
 288 #endif
 289 }
 290
 291 static inline bool bts_available(void)
 292 {
 293         return x86_pmu.enable_bts != NULL;
 294 }
 295
 296 static inline void init_debug_store_on_cpu(int cpu)
 297 {
 298         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 299
 300         if (!ds)
 301                 return;
 302
 303         wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
 304                      (u32)((u64)(unsigned long)ds),
 305                      (u32)((u64)(unsigned long)ds >> 32));
 306 }
 307
 308 static inline void fini_debug_store_on_cpu(int cpu)
 309 {
 310         if (!per_cpu(cpu_hw_events, cpu).ds)
 311                 return;
 312
 313         wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
 314 }
 315
 316 static void release_bts_hardware(void)
 317 {
 318         int cpu;
 319
 320         if (!bts_available())
 321                 return;
 322
 323         get_online_cpus();
 324
 325         for_each_online_cpu(cpu)
 326                 fini_debug_store_on_cpu(cpu);
 327
 328         for_each_possible_cpu(cpu) {
 329                 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 330
 331                 if (!ds)
 332                         continue;
 333
 334                 per_cpu(cpu_hw_events, cpu).ds = NULL;
 335
 336                 kfree((void *)(unsigned long)ds->bts_buffer_base);
 337                 kfree(ds);
 338         }
 339
 340         put_online_cpus();
 341 }
 342
 343 static int reserve_bts_hardware(void)
 344 {
 345         int cpu, err = 0;
 346
 347         if (!bts_available())
 348                 return 0;
 349
 350         get_online_cpus();
 351
 352         for_each_possible_cpu(cpu) {
 353                 struct debug_store *ds;
 354                 void *buffer;
 355
 356                 err = -ENOMEM;
 357                 buffer = kzalloc(BTS_BUFFER_SIZE, GFP_KERNEL);
 358                 if (unlikely(!buffer))
 359                         break;
 360
 361                 ds = kzalloc(sizeof(*ds), GFP_KERNEL);
 362                 if (unlikely(!ds)) {
 363                         kfree(buffer);
 364                         break;
 365                 }
 366
 367                 ds->bts_buffer_base = (u64)(unsigned long)buffer;
 368                 ds->bts_index = ds->bts_buffer_base;
 369                 ds->bts_absolute_maximum =
 370                         ds->bts_buffer_base + BTS_BUFFER_SIZE;
 371                 ds->bts_interrupt_threshold =
 372                         ds->bts_absolute_maximum - BTS_OVFL_TH;
 373
 374                 per_cpu(cpu_hw_events, cpu).ds = ds;
 375                 err = 0;
 376         }
 377
 378         if (err)
 379                 release_bts_hardware();
 380         else {
 381                 for_each_online_cpu(cpu)
 382                         init_debug_store_on_cpu(cpu);
 383         }
 384
 385         put_online_cpus();
 386
 387         return err;
 388 }
 389
 390 static void hw_perf_event_destroy(struct perf_event *event)
 391 {
 392         if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
 393                 release_pmc_hardware();
 394                 release_bts_hardware();
 395                 mutex_unlock(&pmc_reserve_mutex);
 396         }
 397 }
 398
 399 static inline int x86_pmu_initialized(void)
 400 {
 401         return x86_pmu.handle_irq != NULL;
 402 }
 403
 404 static inline int
 405 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event_attr *attr)
 406 {
 407         unsigned int cache_type, cache_op, cache_result;
 408         u64 config, val;
 409
 410         config = attr->config;
 411
 412         cache_type = (config >>  0) & 0xff;
 413         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
 414                 return -EINVAL;
 415
 416         cache_op = (config >>  8) & 0xff;
 417         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
 418                 return -EINVAL;
 419
 420         cache_result = (config >> 16) & 0xff;
 421         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
 422                 return -EINVAL;
 423
 424         val = hw_cache_event_ids[cache_type][cache_op][cache_result];
 425
 426         if (val == 0)
 427                 return -ENOENT;
 428
 429         if (val == -1)
 430                 return -EINVAL;
 431
 432         hwc->config |= val;
 433
 434         return 0;
 435 }
 436
 437 /*
 438  * Setup the hardware configuration for a given attr_type
 439  */
 440 static int __hw_perf_event_init(struct perf_event *event)
 441 {
 442         struct perf_event_attr *attr = &event->attr;
 443         struct hw_perf_event *hwc = &event->hw;
 444         u64 config;
 445         int err;
 446
 447         if (!x86_pmu_initialized())
 448                 return -ENODEV;
 449
 450         err = 0;
 451         if (!atomic_inc_not_zero(&active_events)) {
 452                 mutex_lock(&pmc_reserve_mutex);
 453                 if (atomic_read(&active_events) == 0) {
 454                         if (!reserve_pmc_hardware())
 455                                 err = -EBUSY;
 456                         else
 457                                 err = reserve_bts_hardware();
 458                 }
 459                 if (!err)
 460                         atomic_inc(&active_events);
 461                 mutex_unlock(&pmc_reserve_mutex);
 462         }
 463         if (err)
 464                 return err;
 465
 466         event->destroy = hw_perf_event_destroy;
 467
 468         /*
 469          * Generate PMC IRQs:
 470          * (keep 'enabled' bit clear for now)
 471          */
 472         hwc->config = ARCH_PERFMON_EVENTSEL_INT;
 473
 474         hwc->idx = -1;
 475         hwc->last_cpu = -1;
 476         hwc->last_tag = ~0ULL;
 477
 478         /*
 479          * Count user and OS events unless requested not to.
 480          */
 481         if (!attr->exclude_user)
 482                 hwc->config |= ARCH_PERFMON_EVENTSEL_USR;
 483         if (!attr->exclude_kernel)
 484                 hwc->config |= ARCH_PERFMON_EVENTSEL_OS;
 485
 486         if (!hwc->sample_period) {
 487                 hwc->sample_period = x86_pmu.max_period;
 488                 hwc->last_period = hwc->sample_period;
 489                 atomic64_set(&hwc->period_left, hwc->sample_period);
 490         } else {
 491                 /*
 492                  * If we have a PMU initialized but no APIC
 493                  * interrupts, we cannot sample hardware
 494                  * events (user-space has to fall back and
 495                  * sample via a hrtimer based software event):
 496                  */
 497                 if (!x86_pmu.apic)
 498                         return -EOPNOTSUPP;
 499         }
 500
 501         /*
 502          * Raw hw_event type provide the config in the hw_event structure
 503          */
 504         if (attr->type == PERF_TYPE_RAW) {
 505                 hwc->config |= x86_pmu.raw_event(attr->config);
 506                 if ((hwc->config & ARCH_PERFMON_EVENTSEL_ANY) &&
 507                     perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN))
 508                         return -EACCES;
 509                 return 0;
 510         }
 511
 512         if (attr->type == PERF_TYPE_HW_CACHE)
 513                 return set_ext_hw_attr(hwc, attr);
 514
 515         if (attr->config >= x86_pmu.max_events)
 516                 return -EINVAL;
 517
 518         /*
 519          * The generic map:
 520          */
 521         config = x86_pmu.event_map(attr->config);
 522
 523         if (config == 0)
 524                 return -ENOENT;
 525
 526         if (config == -1LL)
 527                 return -EINVAL;
 528
 529         /*
 530          * Branch tracing:
 531          */
 532         if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) &&
 533             (hwc->sample_period == 1)) {
 534                 /* BTS is not supported by this architecture. */
 535                 if (!bts_available())
 536                         return -EOPNOTSUPP;
 537
 538                 /* BTS is currently only allowed for user-mode. */
 539                 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
 540                         return -EOPNOTSUPP;
 541         }
 542
 543         hwc->config |= config;
 544
 545         return 0;
 546 }
 547
 548 static void x86_pmu_disable_all(void)
 549 {
 550         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 551         int idx;
 552
 553         for (idx = 0; idx < x86_pmu.num_events; idx++) {
 554                 u64 val;
 555
 556                 if (!test_bit(idx, cpuc->active_mask))
 557                         continue;
 558                 rdmsrl(x86_pmu.eventsel + idx, val);
 559                 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
 560                         continue;
 561                 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
 562                 wrmsrl(x86_pmu.eventsel + idx, val);
 563         }
 564 }
 565
 566 void hw_perf_disable(void)
 567 {
 568         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 569
 570         if (!x86_pmu_initialized())
 571                 return;
 572
 573         if (!cpuc->enabled)
 574                 return;
 575
 576         cpuc->n_added = 0;
 577         cpuc->enabled = 0;
 578         barrier();
 579
 580         x86_pmu.disable_all();
 581 }
 582
 583 static void x86_pmu_enable_all(void)
 584 {
 585         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 586         int idx;
 587
 588         for (idx = 0; idx < x86_pmu.num_events; idx++) {
 589                 struct perf_event *event = cpuc->events[idx];
 590                 u64 val;
 591
 592                 if (!test_bit(idx, cpuc->active_mask))
 593                         continue;
 594
 595                 val = event->hw.config;
 596                 val |= ARCH_PERFMON_EVENTSEL_ENABLE;
 597                 wrmsrl(x86_pmu.eventsel + idx, val);
 598         }
 599 }
 600
 601 static const struct pmu pmu;
 602
 603 static inline int is_x86_event(struct perf_event *event)
 604 {
 605         return event->pmu == &pmu;
 606 }
 607
 608 static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
 609 {
 610         struct event_constraint *c, *constraints[X86_PMC_IDX_MAX];
 611         unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 612         int i, j, w, wmax, num = 0;
 613         struct hw_perf_event *hwc;
 614
 615         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 616
 617         for (i = 0; i < n; i++) {
 618                 c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
 619                 constraints[i] = c;
 620         }
 621
 622         /*
 623          * fastpath, try to reuse previous register
 624          */
 625         for (i = 0; i < n; i++) {
 626                 hwc = &cpuc->event_list[i]->hw;
 627                 c = constraints[i];
 628
 629                 /* never assigned */
 630                 if (hwc->idx == -1)
 631                         break;
 632
 633                 /* constraint still honored */
 634                 if (!test_bit(hwc->idx, c->idxmsk))
 635                         break;
 636
 637                 /* not already used */
 638                 if (test_bit(hwc->idx, used_mask))
 639                         break;
 640
 641                 set_bit(hwc->idx, used_mask);
 642                 if (assign)
 643                         assign[i] = hwc->idx;
 644         }
 645         if (i == n)
 646                 goto done;
 647
 648         /*
 649          * begin slow path
 650          */
 651
 652         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 653
 654         /*
 655          * weight = number of possible counters
 656          *
 657          * 1    = most constrained, only works on one counter
 658          * wmax = least constrained, works on any counter
 659          *
 660          * assign events to counters starting with most
 661          * constrained events.
 662          */
 663         wmax = x86_pmu.num_events;
 664
 665         /*
 666          * when fixed event counters are present,
 667          * wmax is incremented by 1 to account
 668          * for one more choice
 669          */
 670         if (x86_pmu.num_events_fixed)
 671                 wmax++;
 672
 673         for (w = 1, num = n; num && w <= wmax; w++) {
 674                 /* for each event */
 675                 for (i = 0; num && i < n; i++) {
 676                         c = constraints[i];
 677                         hwc = &cpuc->event_list[i]->hw;
 678
 679                         if (c->weight != w)
 680                                 continue;
 681
 682                         for_each_set_bit(j, c->idxmsk, X86_PMC_IDX_MAX) {
 683                                 if (!test_bit(j, used_mask))
 684                                         break;
 685                         }
 686
 687                         if (j == X86_PMC_IDX_MAX)
 688                                 break;
 689
 690                         set_bit(j, used_mask);
 691
 692                         if (assign)
 693                                 assign[i] = j;
 694                         num--;
 695                 }
 696         }
 697 done:
 698         /*
 699          * scheduling failed or is just a simulation,
 700          * free resources if necessary
 701          */
 702         if (!assign || num) {
 703                 for (i = 0; i < n; i++) {
 704                         if (x86_pmu.put_event_constraints)
 705                                 x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]);
 706                 }
 707         }
 708         return num ? -ENOSPC : 0;
 709 }
 710
 711 /*
 712  * dogrp: true if must collect siblings events (group)
 713  * returns total number of events and error code
 714  */
 715 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
 716 {
 717         struct perf_event *event;
 718         int n, max_count;
 719
 720         max_count = x86_pmu.num_events + x86_pmu.num_events_fixed;
 721
 722         /* current number of events already accepted */
 723         n = cpuc->n_events;
 724
 725         if (is_x86_event(leader)) {
 726                 if (n >= max_count)
 727                         return -ENOSPC;
 728                 cpuc->event_list[n] = leader;
 729                 n++;
 730         }
 731         if (!dogrp)
 732                 return n;
 733
 734         list_for_each_entry(event, &leader->sibling_list, group_entry) {
 735                 if (!is_x86_event(event) ||
 736                     event->state <= PERF_EVENT_STATE_OFF)
 737                         continue;
 738
 739                 if (n >= max_count)
 740                         return -ENOSPC;
 741
 742                 cpuc->event_list[n] = event;
 743                 n++;
 744         }
 745         return n;
 746 }
 747
 748 static inline void x86_assign_hw_event(struct perf_event *event,
 749                                 struct cpu_hw_events *cpuc, int i)
 750 {
 751         struct hw_perf_event *hwc = &event->hw;
 752
 753         hwc->idx = cpuc->assign[i];
 754         hwc->last_cpu = smp_processor_id();
 755         hwc->last_tag = ++cpuc->tags[i];
 756
 757         if (hwc->idx == X86_PMC_IDX_FIXED_BTS) {
 758                 hwc->config_base = 0;
 759                 hwc->event_base = 0;
 760         } else if (hwc->idx >= X86_PMC_IDX_FIXED) {
 761                 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 762                 /*
 763                  * We set it so that event_base + idx in wrmsr/rdmsr maps to
 764                  * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
 765                  */
 766                 hwc->event_base =
 767                         MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED;
 768         } else {
 769                 hwc->config_base = x86_pmu.eventsel;
 770                 hwc->event_base  = x86_pmu.perfctr;
 771         }
 772 }
 773
 774 static inline int match_prev_assignment(struct hw_perf_event *hwc,
 775                                         struct cpu_hw_events *cpuc,
 776                                         int i)
 777 {
 778         return hwc->idx == cpuc->assign[i] &&
 779                 hwc->last_cpu == smp_processor_id() &&
 780                 hwc->last_tag == cpuc->tags[i];
 781 }
 782
 783 static void x86_pmu_stop(struct perf_event *event);
 784
 785 void hw_perf_enable(void)
 786 {
 787         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 788         struct perf_event *event;
 789         struct hw_perf_event *hwc;
 790         int i;
 791
 792         if (!x86_pmu_initialized())
 793                 return;
 794
 795         if (cpuc->enabled)
 796                 return;
 797
 798         if (cpuc->n_added) {
 799                 /*
 800                  * apply assignment obtained either from
 801                  * hw_perf_group_sched_in() or x86_pmu_enable()
 802                  *
 803                  * step1: save events moving to new counters
 804                  * step2: reprogram moved events into new counters
 805                  */
 806                 for (i = 0; i < cpuc->n_events; i++) {
 807
 808                         event = cpuc->event_list[i];
 809                         hwc = &event->hw;
 810
 811                         /*
 812                          * we can avoid reprogramming counter if:
 813                          * - assigned same counter as last time
 814                          * - running on same CPU as last time
 815                          * - no other event has used the counter since
 816                          */
 817                         if (hwc->idx == -1 ||
 818                             match_prev_assignment(hwc, cpuc, i))
 819                                 continue;
 820
 821                         x86_pmu_stop(event);
 822
 823                         hwc->idx = -1;
 824                 }
 825
 826                 for (i = 0; i < cpuc->n_events; i++) {
 827
 828                         event = cpuc->event_list[i];
 829                         hwc = &event->hw;
 830
 831                         if (hwc->idx == -1) {
 832                                 x86_assign_hw_event(event, cpuc, i);
 833                                 x86_perf_event_set_period(event, hwc, hwc->idx);
 834                         }
 835                         /*
 836                          * need to mark as active because x86_pmu_disable()
 837                          * clear active_mask and events[] yet it preserves
 838                          * idx
 839                          */
 840                         set_bit(hwc->idx, cpuc->active_mask);
 841                         cpuc->events[hwc->idx] = event;
 842
 843                         x86_pmu.enable(hwc, hwc->idx);
 844                         perf_event_update_userpage(event);
 845                 }
 846                 cpuc->n_added = 0;
 847                 perf_events_lapic_init();
 848         }
 849
 850         cpuc->enabled = 1;
 851         barrier();
 852
 853         x86_pmu.enable_all();
 854 }
 855
 856 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc, int idx)
 857 {
 858         (void)checking_wrmsrl(hwc->config_base + idx,
 859                               hwc->config | ARCH_PERFMON_EVENTSEL_ENABLE);
 860 }
 861
 862 static inline void x86_pmu_disable_event(struct hw_perf_event *hwc, int idx)
 863 {
 864         (void)checking_wrmsrl(hwc->config_base + idx, hwc->config);
 865 }
 866
 867 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
 868
 869 /*
 870  * Set the next IRQ period, based on the hwc->period_left value.
 871  * To be called with the event disabled in hw:
 872  */
 873 static int
 874 x86_perf_event_set_period(struct perf_event *event,
 875                              struct hw_perf_event *hwc, int idx)
 876 {
 877         s64 left = atomic64_read(&hwc->period_left);
 878         s64 period = hwc->sample_period;
 879         int err, ret = 0;
 880
 881         if (idx == X86_PMC_IDX_FIXED_BTS)
 882                 return 0;
 883
 884         /*
 885          * If we are way outside a reasonable range then just skip forward:
 886          */
 887         if (unlikely(left <= -period)) {
 888                 left = period;
 889                 atomic64_set(&hwc->period_left, left);
 890                 hwc->last_period = period;
 891                 ret = 1;
 892         }
 893
 894         if (unlikely(left <= 0)) {
 895                 left += period;
 896                 atomic64_set(&hwc->period_left, left);
 897                 hwc->last_period = period;
 898                 ret = 1;
 899         }
 900         /*
 901          * Quirk: certain CPUs dont like it if just 1 hw_event is left:
 902          */
 903         if (unlikely(left < 2))
 904                 left = 2;
 905
 906         if (left > x86_pmu.max_period)
 907                 left = x86_pmu.max_period;
 908
 909         per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
 910
 911         /*
 912          * The hw event starts counting from this event offset,
 913          * mark it to be able to extra future deltas:
 914          */
 915         atomic64_set(&hwc->prev_count, (u64)-left);
 916
 917         err = checking_wrmsrl(hwc->event_base + idx,
 918                              (u64)(-left) & x86_pmu.event_mask);
 919
 920         perf_event_update_userpage(event);
 921
 922         return ret;
 923 }
 924
 925 static void x86_pmu_enable_event(struct hw_perf_event *hwc, int idx)
 926 {
 927         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 928         if (cpuc->enabled)
 929                 __x86_pmu_enable_event(hwc, idx);
 930 }
 931
 932 /*
 933  * activate a single event
 934  *
 935  * The event is added to the group of enabled events
 936  * but only if it can be scehduled with existing events.
 937  *
 938  * Called with PMU disabled. If successful and return value 1,
 939  * then guaranteed to call perf_enable() and hw_perf_enable()
 940  */
 941 static int x86_pmu_enable(struct perf_event *event)
 942 {
 943         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 944         struct hw_perf_event *hwc;
 945         int assign[X86_PMC_IDX_MAX];
 946         int n, n0, ret;
 947
 948         hwc = &event->hw;
 949
 950         n0 = cpuc->n_events;
 951         n = collect_events(cpuc, event, false);
 952         if (n < 0)
 953                 return n;
 954
 955         ret = x86_schedule_events(cpuc, n, assign);
 956         if (ret)
 957                 return ret;
 958         /*
 959          * copy new assignment, now we know it is possible
 960          * will be used by hw_perf_enable()
 961          */
 962         memcpy(cpuc->assign, assign, n*sizeof(int));
 963
 964         cpuc->n_events = n;
 965         cpuc->n_added  = n - n0;
 966
 967         return 0;
 968 }
 969
 970 static int x86_pmu_start(struct perf_event *event)
 971 {
 972         struct hw_perf_event *hwc = &event->hw;
 973
 974         if (hwc->idx == -1)
 975                 return -EAGAIN;
 976
 977         x86_perf_event_set_period(event, hwc, hwc->idx);
 978         x86_pmu.enable(hwc, hwc->idx);
 979
 980         return 0;
 981 }
 982
 983 static void x86_pmu_unthrottle(struct perf_event *event)
 984 {
 985         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 986         struct hw_perf_event *hwc = &event->hw;
 987
 988         if (WARN_ON_ONCE(hwc->idx >= X86_PMC_IDX_MAX ||
 989                                 cpuc->events[hwc->idx] != event))
 990                 return;
 991
 992         x86_pmu.enable(hwc, hwc->idx);
 993 }
 994
 995 void perf_event_print_debug(void)
 996 {
 997         u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
 998         struct cpu_hw_events *cpuc;
 999         unsigned long flags;
1000         int cpu, idx;
1001
1002         if (!x86_pmu.num_events)
1003                 return;
1004
1005         local_irq_save(flags);
1006
1007         cpu = smp_processor_id();
1008         cpuc = &per_cpu(cpu_hw_events, cpu);
1009
1010         if (x86_pmu.version >= 2) {
1011                 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1012                 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1013                 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1014                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1015
1016                 pr_info("\n");
1017                 pr_info("CPU#%d: ctrl:       %016llx\n", cpu, ctrl);
1018                 pr_info("CPU#%d: status:     %016llx\n", cpu, status);
1019                 pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);
1020                 pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);
1021         }
1022         pr_info("CPU#%d: active:       %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1023
1024         for (idx = 0; idx < x86_pmu.num_events; idx++) {
1025                 rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl);
1026                 rdmsrl(x86_pmu.perfctr  + idx, pmc_count);
1027
1028                 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1029
1030                 pr_info("CPU#%d:   gen-PMC%d ctrl:  %016llx\n",
1031                         cpu, idx, pmc_ctrl);
1032                 pr_info("CPU#%d:   gen-PMC%d count: %016llx\n",
1033                         cpu, idx, pmc_count);
1034                 pr_info("CPU#%d:   gen-PMC%d left:  %016llx\n",
1035                         cpu, idx, prev_left);
1036         }
1037         for (idx = 0; idx < x86_pmu.num_events_fixed; idx++) {
1038                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1039
1040                 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1041                         cpu, idx, pmc_count);
1042         }
1043         local_irq_restore(flags);
1044 }
1045
1046 static void x86_pmu_stop(struct perf_event *event)
1047 {
1048         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1049         struct hw_perf_event *hwc = &event->hw;
1050         int idx = hwc->idx;
1051
1052         /*
1053          * Must be done before we disable, otherwise the nmi handler
1054          * could reenable again:
1055          */
1056         clear_bit(idx, cpuc->active_mask);
1057         x86_pmu.disable(hwc, idx);
1058
1059         /*
1060          * Drain the remaining delta count out of a event
1061          * that we are disabling:
1062          */
1063         x86_perf_event_update(event, hwc, idx);
1064
1065         cpuc->events[idx] = NULL;
1066 }
1067
1068 static void x86_pmu_disable(struct perf_event *event)
1069 {
1070         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1071         int i;
1072
1073         x86_pmu_stop(event);
1074
1075         for (i = 0; i < cpuc->n_events; i++) {
1076                 if (event == cpuc->event_list[i]) {
1077
1078                         if (x86_pmu.put_event_constraints)
1079                                 x86_pmu.put_event_constraints(cpuc, event);
1080
1081                         while (++i < cpuc->n_events)
1082                                 cpuc->event_list[i-1] = cpuc->event_list[i];
1083
1084                         --cpuc->n_events;
1085                         break;
1086                 }
1087         }
1088         perf_event_update_userpage(event);
1089 }
1090
1091 static int x86_pmu_handle_irq(struct pt_regs *regs)
1092 {
1093         struct perf_sample_data data;
1094         struct cpu_hw_events *cpuc;
1095         struct perf_event *event;
1096         struct hw_perf_event *hwc;
1097         int idx, handled = 0;
1098         u64 val;
1099
1100         data.addr = 0;
1101         data.raw = NULL;
1102
1103         cpuc = &__get_cpu_var(cpu_hw_events);
1104
1105         for (idx = 0; idx < x86_pmu.num_events; idx++) {
1106                 if (!test_bit(idx, cpuc->active_mask))
1107                         continue;
1108
1109                 event = cpuc->events[idx];
1110                 hwc = &event->hw;
1111
1112                 val = x86_perf_event_update(event, hwc, idx);
1113                 if (val & (1ULL << (x86_pmu.event_bits - 1)))
1114                         continue;
1115
1116                 /*
1117                  * event overflow
1118                  */
1119                 handled         = 1;
1120                 data.period     = event->hw.last_period;
1121
1122                 if (!x86_perf_event_set_period(event, hwc, idx))
1123                         continue;
1124
1125                 if (perf_event_overflow(event, 1, &data, regs))
1126                         x86_pmu.disable(hwc, idx);
1127         }
1128
1129         if (handled)
1130                 inc_irq_stat(apic_perf_irqs);
1131
1132         return handled;
1133 }
1134
1135 void smp_perf_pending_interrupt(struct pt_regs *regs)
1136 {
1137         irq_enter();
1138         ack_APIC_irq();
1139         inc_irq_stat(apic_pending_irqs);
1140         perf_event_do_pending();
1141         irq_exit();
1142 }
1143
1144 void set_perf_event_pending(void)
1145 {
1146 #ifdef CONFIG_X86_LOCAL_APIC
1147         if (!x86_pmu.apic || !x86_pmu_initialized())
1148                 return;
1149
1150         apic->send_IPI_self(LOCAL_PENDING_VECTOR);
1151 #endif
1152 }
1153
1154 void perf_events_lapic_init(void)
1155 {
1156 #ifdef CONFIG_X86_LOCAL_APIC
1157         if (!x86_pmu.apic || !x86_pmu_initialized())
1158                 return;
1159
1160         /*
1161          * Always use NMI for PMU
1162          */
1163         apic_write(APIC_LVTPC, APIC_DM_NMI);
1164 #endif
1165 }
1166
1167 static int __kprobes
1168 perf_event_nmi_handler(struct notifier_block *self,
1169                          unsigned long cmd, void *__args)
1170 {
1171         struct die_args *args = __args;
1172         struct pt_regs *regs;
1173
1174         if (!atomic_read(&active_events))
1175                 return NOTIFY_DONE;
1176
1177         switch (cmd) {
1178         case DIE_NMI:
1179         case DIE_NMI_IPI:
1180                 break;
1181
1182         default:
1183                 return NOTIFY_DONE;
1184         }
1185
1186         regs = args->regs;
1187
1188 #ifdef CONFIG_X86_LOCAL_APIC
1189         apic_write(APIC_LVTPC, APIC_DM_NMI);
1190 #endif
1191         /*
1192          * Can't rely on the handled return value to say it was our NMI, two
1193          * events could trigger 'simultaneously' raising two back-to-back NMIs.
1194          *
1195          * If the first NMI handles both, the latter will be empty and daze
1196          * the CPU.
1197          */
1198         x86_pmu.handle_irq(regs);
1199
1200         return NOTIFY_STOP;
1201 }
1202
1203 static __read_mostly struct notifier_block perf_event_nmi_notifier = {
1204         .notifier_call          = perf_event_nmi_handler,
1205         .next                   = NULL,
1206         .priority               = 1
1207 };
1208
1209 static struct event_constraint unconstrained;
1210 static struct event_constraint emptyconstraint;
1211
1212 static struct event_constraint *
1213 x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1214 {
1215         struct event_constraint *c;
1216
1217         if (x86_pmu.event_constraints) {
1218                 for_each_event_constraint(c, x86_pmu.event_constraints) {
1219                         if ((event->hw.config & c->cmask) == c->code)
1220                                 return c;
1221                 }
1222         }
1223
1224         return &unconstrained;
1225 }
1226
1227 static int x86_event_sched_in(struct perf_event *event,
1228                           struct perf_cpu_context *cpuctx)
1229 {
1230         int ret = 0;
1231
1232         event->state = PERF_EVENT_STATE_ACTIVE;
1233         event->oncpu = smp_processor_id();
1234         event->tstamp_running += event->ctx->time - event->tstamp_stopped;
1235
1236         if (!is_x86_event(event))
1237                 ret = event->pmu->enable(event);
1238
1239         if (!ret && !is_software_event(event))
1240                 cpuctx->active_oncpu++;
1241
1242         if (!ret && event->attr.exclusive)
1243                 cpuctx->exclusive = 1;
1244
1245         return ret;
1246 }
1247
1248 static void x86_event_sched_out(struct perf_event *event,
1249                             struct perf_cpu_context *cpuctx)
1250 {
1251         event->state = PERF_EVENT_STATE_INACTIVE;
1252         event->oncpu = -1;
1253
1254         if (!is_x86_event(event))
1255                 event->pmu->disable(event);
1256
1257         event->tstamp_running -= event->ctx->time - event->tstamp_stopped;
1258
1259         if (!is_software_event(event))
1260                 cpuctx->active_oncpu--;
1261
1262         if (event->attr.exclusive || !cpuctx->active_oncpu)
1263                 cpuctx->exclusive = 0;
1264 }
1265
1266 /*
1267  * Called to enable a whole group of events.
1268  * Returns 1 if the group was enabled, or -EAGAIN if it could not be.
1269  * Assumes the caller has disabled interrupts and has
1270  * frozen the PMU with hw_perf_save_disable.
1271  *
1272  * called with PMU disabled. If successful and return value 1,
1273  * then guaranteed to call perf_enable() and hw_perf_enable()
1274  */
1275 int hw_perf_group_sched_in(struct perf_event *leader,
1276                struct perf_cpu_context *cpuctx,
1277                struct perf_event_context *ctx)
1278 {
1279         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1280         struct perf_event *sub;
1281         int assign[X86_PMC_IDX_MAX];
1282         int n0, n1, ret;
1283
1284         /* n0 = total number of events */
1285         n0 = collect_events(cpuc, leader, true);
1286         if (n0 < 0)
1287                 return n0;
1288
1289         ret = x86_schedule_events(cpuc, n0, assign);
1290         if (ret)
1291                 return ret;
1292
1293         ret = x86_event_sched_in(leader, cpuctx);
1294         if (ret)
1295                 return ret;
1296
1297         n1 = 1;
1298         list_for_each_entry(sub, &leader->sibling_list, group_entry) {
1299                 if (sub->state > PERF_EVENT_STATE_OFF) {
1300                         ret = x86_event_sched_in(sub, cpuctx);
1301                         if (ret)
1302                                 goto undo;
1303                         ++n1;
1304                 }
1305         }
1306         /*
1307          * copy new assignment, now we know it is possible
1308          * will be used by hw_perf_enable()
1309          */
1310         memcpy(cpuc->assign, assign, n0*sizeof(int));
1311
1312         cpuc->n_events  = n0;
1313         cpuc->n_added   = n1;
1314         ctx->nr_active += n1;
1315
1316         /*
1317          * 1 means successful and events are active
1318          * This is not quite true because we defer
1319          * actual activation until hw_perf_enable() but
1320          * this way we* ensure caller won't try to enable
1321          * individual events
1322          */
1323         return 1;
1324 undo:
1325         x86_event_sched_out(leader, cpuctx);
1326         n0  = 1;
1327         list_for_each_entry(sub, &leader->sibling_list, group_entry) {
1328                 if (sub->state == PERF_EVENT_STATE_ACTIVE) {
1329                         x86_event_sched_out(sub, cpuctx);
1330                         if (++n0 == n1)
1331                                 break;
1332                 }
1333         }
1334         return ret;
1335 }
1336
1337 #include "perf_event_amd.c"
1338 #include "perf_event_p6.c"
1339 #include "perf_event_intel.c"
1340
1341 static void __init pmu_check_apic(void)
1342 {
1343         if (cpu_has_apic)
1344                 return;
1345
1346         x86_pmu.apic = 0;
1347         pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1348         pr_info("no hardware sampling interrupt available.\n");
1349 }
1350
1351 void __init init_hw_perf_events(void)
1352 {
1353         struct event_constraint *c;
1354         int err;
1355
1356         pr_info("Performance Events: ");
1357
1358         switch (boot_cpu_data.x86_vendor) {
1359         case X86_VENDOR_INTEL:
1360                 err = intel_pmu_init();
1361                 break;
1362         case X86_VENDOR_AMD:
1363                 err = amd_pmu_init();
1364                 break;
1365         default:
1366                 return;
1367         }
1368         if (err != 0) {
1369                 pr_cont("no PMU driver, software events only.\n");
1370                 return;
1371         }
1372
1373         pmu_check_apic();
1374
1375         pr_cont("%s PMU driver.\n", x86_pmu.name);
1376
1377         if (x86_pmu.num_events > X86_PMC_MAX_GENERIC) {
1378                 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
1379                      x86_pmu.num_events, X86_PMC_MAX_GENERIC);
1380                 x86_pmu.num_events = X86_PMC_MAX_GENERIC;
1381         }
1382         perf_event_mask = (1 << x86_pmu.num_events) - 1;
1383         perf_max_events = x86_pmu.num_events;
1384
1385         if (x86_pmu.num_events_fixed > X86_PMC_MAX_FIXED) {
1386                 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
1387                      x86_pmu.num_events_fixed, X86_PMC_MAX_FIXED);
1388                 x86_pmu.num_events_fixed = X86_PMC_MAX_FIXED;
1389         }
1390
1391         perf_event_mask |=
1392                 ((1LL << x86_pmu.num_events_fixed)-1) << X86_PMC_IDX_FIXED;
1393         x86_pmu.intel_ctrl = perf_event_mask;
1394
1395         perf_events_lapic_init();
1396         register_die_notifier(&perf_event_nmi_notifier);
1397
1398         unconstrained = (struct event_constraint)
1399                 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_events) - 1,
1400                                    0, x86_pmu.num_events);
1401
1402         if (x86_pmu.event_constraints) {
1403                 for_each_event_constraint(c, x86_pmu.event_constraints) {
1404                         if (c->cmask != INTEL_ARCH_FIXED_MASK)
1405                                 continue;
1406
1407                         c->idxmsk64 |= (1ULL << x86_pmu.num_events) - 1;
1408                         c->weight += x86_pmu.num_events;
1409                 }
1410         }
1411
1412         pr_info("... version:                %d\n",     x86_pmu.version);
1413         pr_info("... bit width:              %d\n",     x86_pmu.event_bits);
1414         pr_info("... generic registers:      %d\n",     x86_pmu.num_events);
1415         pr_info("... value mask:             %016Lx\n", x86_pmu.event_mask);
1416         pr_info("... max period:             %016Lx\n", x86_pmu.max_period);
1417         pr_info("... fixed-purpose events:   %d\n",     x86_pmu.num_events_fixed);
1418         pr_info("... event mask:             %016Lx\n", perf_event_mask);
1419 }
1420
1421 static inline void x86_pmu_read(struct perf_event *event)
1422 {
1423         x86_perf_event_update(event, &event->hw, event->hw.idx);
1424 }
1425
1426 static const struct pmu pmu = {
1427         .enable         = x86_pmu_enable,
1428         .disable        = x86_pmu_disable,
1429         .start          = x86_pmu_start,
1430         .stop           = x86_pmu_stop,
1431         .read           = x86_pmu_read,
1432         .unthrottle     = x86_pmu_unthrottle,
1433 };
1434
1435 /*
1436  * validate a single event group
1437  *
1438  * validation include:
1439  *      - check events are compatible which each other
1440  *      - events do not compete for the same counter
1441  *      - number of events <= number of counters
1442  *
1443  * validation ensures the group can be loaded onto the
1444  * PMU if it was the only group available.
1445  */
1446 static int validate_group(struct perf_event *event)
1447 {
1448         struct perf_event *leader = event->group_leader;
1449         struct cpu_hw_events *fake_cpuc;
1450         int ret, n;
1451
1452         ret = -ENOMEM;
1453         fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1454         if (!fake_cpuc)
1455                 goto out;
1456
1457         /*
1458          * the event is not yet connected with its
1459          * siblings therefore we must first collect
1460          * existing siblings, then add the new event
1461          * before we can simulate the scheduling
1462          */
1463         ret = -ENOSPC;
1464         n = collect_events(fake_cpuc, leader, true);
1465         if (n < 0)
1466                 goto out_free;
1467
1468         fake_cpuc->n_events = n;
1469         n = collect_events(fake_cpuc, event, false);
1470         if (n < 0)
1471                 goto out_free;
1472
1473         fake_cpuc->n_events = n;
1474
1475         ret = x86_schedule_events(fake_cpuc, n, NULL);
1476
1477 out_free:
1478         kfree(fake_cpuc);
1479 out:
1480         return ret;
1481 }
1482
1483 const struct pmu *hw_perf_event_init(struct perf_event *event)
1484 {
1485         const struct pmu *tmp;
1486         int err;
1487
1488         err = __hw_perf_event_init(event);
1489         if (!err) {
1490                 /*
1491                  * we temporarily connect event to its pmu
1492                  * such that validate_group() can classify
1493                  * it as an x86 event using is_x86_event()
1494                  */
1495                 tmp = event->pmu;
1496                 event->pmu = &pmu;
1497
1498                 if (event->group_leader != event)
1499                         err = validate_group(event);
1500
1501                 event->pmu = tmp;
1502         }
1503         if (err) {
1504                 if (event->destroy)
1505                         event->destroy(event);
1506                 return ERR_PTR(err);
1507         }
1508
1509         return &pmu;
1510 }
1511
1512 /*
1513  * callchain support
1514  */
1515
1516 static inline
1517 void callchain_store(struct perf_callchain_entry *entry, u64 ip)
1518 {
1519         if (entry->nr < PERF_MAX_STACK_DEPTH)
1520                 entry->ip[entry->nr++] = ip;
1521 }
1522
1523 static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_irq_entry);
1524 static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_nmi_entry);
1525
1526
1527 static void
1528 backtrace_warning_symbol(void *data, char *msg, unsigned long symbol)
1529 {
1530         /* Ignore warnings */
1531 }
1532
1533 static void backtrace_warning(void *data, char *msg)
1534 {
1535         /* Ignore warnings */
1536 }
1537
1538 static int backtrace_stack(void *data, char *name)
1539 {
1540         return 0;
1541 }
1542
1543 static void backtrace_address(void *data, unsigned long addr, int reliable)
1544 {
1545         struct perf_callchain_entry *entry = data;
1546
1547         if (reliable)
1548                 callchain_store(entry, addr);
1549 }
1550
1551 static const struct stacktrace_ops backtrace_ops = {
1552         .warning                = backtrace_warning,
1553         .warning_symbol         = backtrace_warning_symbol,
1554         .stack                  = backtrace_stack,
1555         .address                = backtrace_address,
1556         .walk_stack             = print_context_stack_bp,
1557 };
1558
1559 #include "../dumpstack.h"
1560
1561 static void
1562 perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry)
1563 {
1564         callchain_store(entry, PERF_CONTEXT_KERNEL);
1565         callchain_store(entry, regs->ip);
1566
1567         dump_trace(NULL, regs, NULL, regs->bp, &backtrace_ops, entry);
1568 }
1569
1570 /*
1571  * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
1572  */
1573 static unsigned long
1574 copy_from_user_nmi(void *to, const void __user *from, unsigned long n)
1575 {
1576         unsigned long offset, addr = (unsigned long)from;
1577         int type = in_nmi() ? KM_NMI : KM_IRQ0;
1578         unsigned long size, len = 0;
1579         struct page *page;
1580         void *map;
1581         int ret;
1582
1583         do {
1584                 ret = __get_user_pages_fast(addr, 1, 0, &page);
1585                 if (!ret)
1586                         break;
1587
1588                 offset = addr & (PAGE_SIZE - 1);
1589                 size = min(PAGE_SIZE - offset, n - len);
1590
1591                 map = kmap_atomic(page, type);
1592                 memcpy(to, map+offset, size);
1593                 kunmap_atomic(map, type);
1594                 put_page(page);
1595
1596                 len  += size;
1597                 to   += size;
1598                 addr += size;
1599
1600         } while (len < n);
1601
1602         return len;
1603 }
1604
1605 static int copy_stack_frame(const void __user *fp, struct stack_frame *frame)
1606 {
1607         unsigned long bytes;
1608
1609         bytes = copy_from_user_nmi(frame, fp, sizeof(*frame));
1610
1611         return bytes == sizeof(*frame);
1612 }
1613
1614 static void
1615 perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry)
1616 {
1617         struct stack_frame frame;
1618         const void __user *fp;
1619
1620         if (!user_mode(regs))
1621                 regs = task_pt_regs(current);
1622
1623         fp = (void __user *)regs->bp;
1624
1625         callchain_store(entry, PERF_CONTEXT_USER);
1626         callchain_store(entry, regs->ip);
1627
1628         while (entry->nr < PERF_MAX_STACK_DEPTH) {
1629                 frame.next_frame             = NULL;
1630                 frame.return_address = 0;
1631
1632                 if (!copy_stack_frame(fp, &frame))
1633                         break;
1634
1635                 if ((unsigned long)fp < regs->sp)
1636                         break;
1637
1638                 callchain_store(entry, frame.return_address);
1639                 fp = frame.next_frame;
1640         }
1641 }
1642
1643 static void
1644 perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry)
1645 {
1646         int is_user;
1647
1648         if (!regs)
1649                 return;
1650
1651         is_user = user_mode(regs);
1652
1653         if (is_user && current->state != TASK_RUNNING)
1654                 return;
1655
1656         if (!is_user)
1657                 perf_callchain_kernel(regs, entry);
1658
1659         if (current->mm)
1660                 perf_callchain_user(regs, entry);
1661 }
1662
1663 struct perf_callchain_entry *perf_callchain(struct pt_regs *regs)
1664 {
1665         struct perf_callchain_entry *entry;
1666
1667         if (in_nmi())
1668                 entry = &__get_cpu_var(pmc_nmi_entry);
1669         else
1670                 entry = &__get_cpu_var(pmc_irq_entry);
1671
1672         entry->nr = 0;
1673
1674         perf_do_callchain(regs, entry);
1675
1676         return entry;
1677 }
1678
1679 void hw_perf_event_setup_online(int cpu)
1680 {
1681         init_debug_store_on_cpu(cpu);
1682
1683         switch (boot_cpu_data.x86_vendor) {
1684         case X86_VENDOR_AMD:
1685                 amd_pmu_cpu_online(cpu);
1686                 break;
1687         default:
1688                 return;
1689         }
1690 }
1691
1692 void hw_perf_event_setup_offline(int cpu)
1693 {
1694         init_debug_store_on_cpu(cpu);
1695
1696         switch (boot_cpu_data.x86_vendor) {
1697         case X86_VENDOR_AMD:
1698                 amd_pmu_cpu_offline(cpu);
1699                 break;
1700         default:
1701                 return;
1702         }
1703 }