2 * Performance events x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/module.h>
21 #include <linux/kdebug.h>
22 #include <linux/sched.h>
23 #include <linux/uaccess.h>
24 #include <linux/slab.h>
25 #include <linux/highmem.h>
26 #include <linux/cpu.h>
27 #include <linux/bitops.h>
30 #include <asm/stacktrace.h>
32 #include <asm/compat.h>
36 #define wrmsrl(msr, val) \
38 trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\
39 (unsigned long)(val)); \
40 native_write_msr((msr), (u32)((u64)(val)), \
41 (u32)((u64)(val) >> 32)); \
46 * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
49 copy_from_user_nmi(void *to, const void __user *from, unsigned long n)
51 unsigned long offset, addr = (unsigned long)from;
52 int type = in_nmi() ? KM_NMI : KM_IRQ0;
53 unsigned long size, len = 0;
59 ret = __get_user_pages_fast(addr, 1, 0, &page);
63 offset = addr & (PAGE_SIZE - 1);
64 size = min(PAGE_SIZE - offset, n - len);
66 map = kmap_atomic(page, type);
67 memcpy(to, map+offset, size);
68 kunmap_atomic(map, type);
80 struct event_constraint {
82 unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
91 int nb_id; /* NorthBridge id */
92 int refcnt; /* reference count */
93 struct perf_event *owners[X86_PMC_IDX_MAX];
94 struct event_constraint event_constraints[X86_PMC_IDX_MAX];
97 #define MAX_LBR_ENTRIES 16
99 struct cpu_hw_events {
101 * Generic x86 PMC bits
103 struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */
104 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
109 int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
110 u64 tags[X86_PMC_IDX_MAX];
111 struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
114 * Intel DebugStore bits
116 struct debug_store *ds;
124 struct perf_branch_stack lbr_stack;
125 struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES];
130 struct amd_nb *amd_nb;
133 #define __EVENT_CONSTRAINT(c, n, m, w) {\
134 { .idxmsk64 = (n) }, \
140 #define EVENT_CONSTRAINT(c, n, m) \
141 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n))
144 * Constraint on the Event code.
146 #define INTEL_EVENT_CONSTRAINT(c, n) \
147 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
150 * Constraint on the Event code + UMask + fixed-mask
152 * filter mask to validate fixed counter events.
153 * the following filters disqualify for fixed counters:
157 * The other filters are supported by fixed counters.
158 * The any-thread option is supported starting with v3.
160 #define FIXED_EVENT_CONSTRAINT(c, n) \
161 EVENT_CONSTRAINT(c, (1ULL << (32+n)), X86_RAW_EVENT_MASK)
164 * Constraint on the Event code + UMask
166 #define PEBS_EVENT_CONSTRAINT(c, n) \
167 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
169 #define EVENT_CONSTRAINT_END \
170 EVENT_CONSTRAINT(0, 0, 0)
172 #define for_each_event_constraint(e, c) \
173 for ((e) = (c); (e)->weight; (e)++)
175 union perf_capabilities {
179 u64 pebs_arch_reg : 1;
187 * struct x86_pmu - generic x86 pmu
191 * Generic x86 PMC bits
195 int (*handle_irq)(struct pt_regs *);
196 void (*disable_all)(void);
197 void (*enable_all)(int added);
198 void (*enable)(struct perf_event *);
199 void (*disable)(struct perf_event *);
200 int (*hw_config)(struct perf_event *event);
201 int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
204 u64 (*event_map)(int);
207 int num_counters_fixed;
212 struct event_constraint *
213 (*get_event_constraints)(struct cpu_hw_events *cpuc,
214 struct perf_event *event);
216 void (*put_event_constraints)(struct cpu_hw_events *cpuc,
217 struct perf_event *event);
218 struct event_constraint *event_constraints;
219 void (*quirks)(void);
221 int (*cpu_prepare)(int cpu);
222 void (*cpu_starting)(int cpu);
223 void (*cpu_dying)(int cpu);
224 void (*cpu_dead)(int cpu);
227 * Intel Arch Perfmon v2+
230 union perf_capabilities intel_cap;
233 * Intel DebugStore bits
236 int pebs_record_size;
237 void (*drain_pebs)(struct pt_regs *regs);
238 struct event_constraint *pebs_constraints;
243 unsigned long lbr_tos, lbr_from, lbr_to; /* MSR base regs */
244 int lbr_nr; /* hardware stack size */
247 static struct x86_pmu x86_pmu __read_mostly;
249 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
253 static int x86_perf_event_set_period(struct perf_event *event);
256 * Generalized hw caching related hw_event table, filled
257 * in on a per model basis. A value of 0 means
258 * 'not supported', -1 means 'hw_event makes no sense on
259 * this CPU', any other value means the raw hw_event
263 #define C(x) PERF_COUNT_HW_CACHE_##x
265 static u64 __read_mostly hw_cache_event_ids
266 [PERF_COUNT_HW_CACHE_MAX]
267 [PERF_COUNT_HW_CACHE_OP_MAX]
268 [PERF_COUNT_HW_CACHE_RESULT_MAX];
271 * Propagate event elapsed time into the generic event.
272 * Can only be executed on the CPU where the event is active.
273 * Returns the delta events processed.
276 x86_perf_event_update(struct perf_event *event)
278 struct hw_perf_event *hwc = &event->hw;
279 int shift = 64 - x86_pmu.cntval_bits;
280 u64 prev_raw_count, new_raw_count;
284 if (idx == X86_PMC_IDX_FIXED_BTS)
288 * Careful: an NMI might modify the previous event value.
290 * Our tactic to handle this is to first atomically read and
291 * exchange a new raw count - then add that new-prev delta
292 * count to the generic event atomically:
295 prev_raw_count = atomic64_read(&hwc->prev_count);
296 rdmsrl(hwc->event_base + idx, new_raw_count);
298 if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
299 new_raw_count) != prev_raw_count)
303 * Now we have the new raw value and have updated the prev
304 * timestamp already. We can now calculate the elapsed delta
305 * (event-)time and add that to the generic event.
307 * Careful, not all hw sign-extends above the physical width
310 delta = (new_raw_count << shift) - (prev_raw_count << shift);
313 atomic64_add(delta, &event->count);
314 atomic64_sub(delta, &hwc->period_left);
316 return new_raw_count;
319 static atomic_t active_events;
320 static DEFINE_MUTEX(pmc_reserve_mutex);
322 #ifdef CONFIG_X86_LOCAL_APIC
324 static bool reserve_pmc_hardware(void)
328 if (nmi_watchdog == NMI_LOCAL_APIC)
329 disable_lapic_nmi_watchdog();
331 for (i = 0; i < x86_pmu.num_counters; i++) {
332 if (!reserve_perfctr_nmi(x86_pmu.perfctr + i))
336 for (i = 0; i < x86_pmu.num_counters; i++) {
337 if (!reserve_evntsel_nmi(x86_pmu.eventsel + i))
344 for (i--; i >= 0; i--)
345 release_evntsel_nmi(x86_pmu.eventsel + i);
347 i = x86_pmu.num_counters;
350 for (i--; i >= 0; i--)
351 release_perfctr_nmi(x86_pmu.perfctr + i);
353 if (nmi_watchdog == NMI_LOCAL_APIC)
354 enable_lapic_nmi_watchdog();
359 static void release_pmc_hardware(void)
363 for (i = 0; i < x86_pmu.num_counters; i++) {
364 release_perfctr_nmi(x86_pmu.perfctr + i);
365 release_evntsel_nmi(x86_pmu.eventsel + i);
368 if (nmi_watchdog == NMI_LOCAL_APIC)
369 enable_lapic_nmi_watchdog();
374 static bool reserve_pmc_hardware(void) { return true; }
375 static void release_pmc_hardware(void) {}
379 static int reserve_ds_buffers(void);
380 static void release_ds_buffers(void);
382 static void hw_perf_event_destroy(struct perf_event *event)
384 if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
385 release_pmc_hardware();
386 release_ds_buffers();
387 mutex_unlock(&pmc_reserve_mutex);
391 static inline int x86_pmu_initialized(void)
393 return x86_pmu.handle_irq != NULL;
397 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event_attr *attr)
399 unsigned int cache_type, cache_op, cache_result;
402 config = attr->config;
404 cache_type = (config >> 0) & 0xff;
405 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
408 cache_op = (config >> 8) & 0xff;
409 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
412 cache_result = (config >> 16) & 0xff;
413 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
416 val = hw_cache_event_ids[cache_type][cache_op][cache_result];
429 static int x86_setup_perfctr(struct perf_event *event)
431 struct perf_event_attr *attr = &event->attr;
432 struct hw_perf_event *hwc = &event->hw;
435 if (!hwc->sample_period) {
436 hwc->sample_period = x86_pmu.max_period;
437 hwc->last_period = hwc->sample_period;
438 atomic64_set(&hwc->period_left, hwc->sample_period);
441 * If we have a PMU initialized but no APIC
442 * interrupts, we cannot sample hardware
443 * events (user-space has to fall back and
444 * sample via a hrtimer based software event):
450 if (attr->type == PERF_TYPE_RAW)
453 if (attr->type == PERF_TYPE_HW_CACHE)
454 return set_ext_hw_attr(hwc, attr);
456 if (attr->config >= x86_pmu.max_events)
462 config = x86_pmu.event_map(attr->config);
473 if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) &&
474 (hwc->sample_period == 1)) {
475 /* BTS is not supported by this architecture. */
479 /* BTS is currently only allowed for user-mode. */
480 if (!attr->exclude_kernel)
484 hwc->config |= config;
489 static int x86_pmu_hw_config(struct perf_event *event)
493 * (keep 'enabled' bit clear for now)
495 event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
498 * Count user and OS events unless requested not to
500 if (!event->attr.exclude_user)
501 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
502 if (!event->attr.exclude_kernel)
503 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
505 if (event->attr.type == PERF_TYPE_RAW)
506 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
508 return x86_setup_perfctr(event);
512 * Setup the hardware configuration for a given attr_type
514 static int __hw_perf_event_init(struct perf_event *event)
518 if (!x86_pmu_initialized())
522 if (!atomic_inc_not_zero(&active_events)) {
523 mutex_lock(&pmc_reserve_mutex);
524 if (atomic_read(&active_events) == 0) {
525 if (!reserve_pmc_hardware())
528 err = reserve_ds_buffers();
530 release_pmc_hardware();
534 atomic_inc(&active_events);
535 mutex_unlock(&pmc_reserve_mutex);
540 event->destroy = hw_perf_event_destroy;
543 event->hw.last_cpu = -1;
544 event->hw.last_tag = ~0ULL;
546 return x86_pmu.hw_config(event);
549 static void x86_pmu_disable_all(void)
551 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
554 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
557 if (!test_bit(idx, cpuc->active_mask))
559 rdmsrl(x86_pmu.eventsel + idx, val);
560 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
562 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
563 wrmsrl(x86_pmu.eventsel + idx, val);
567 void hw_perf_disable(void)
569 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
571 if (!x86_pmu_initialized())
581 x86_pmu.disable_all();
584 static void x86_pmu_enable_all(int added)
586 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
589 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
590 struct perf_event *event = cpuc->events[idx];
593 if (!test_bit(idx, cpuc->active_mask))
596 val = event->hw.config;
597 val |= ARCH_PERFMON_EVENTSEL_ENABLE;
598 wrmsrl(x86_pmu.eventsel + idx, val);
602 static const struct pmu pmu;
604 static inline int is_x86_event(struct perf_event *event)
606 return event->pmu == &pmu;
609 static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
611 struct event_constraint *c, *constraints[X86_PMC_IDX_MAX];
612 unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
613 int i, j, w, wmax, num = 0;
614 struct hw_perf_event *hwc;
616 bitmap_zero(used_mask, X86_PMC_IDX_MAX);
618 for (i = 0; i < n; i++) {
619 c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
624 * fastpath, try to reuse previous register
626 for (i = 0; i < n; i++) {
627 hwc = &cpuc->event_list[i]->hw;
634 /* constraint still honored */
635 if (!test_bit(hwc->idx, c->idxmsk))
638 /* not already used */
639 if (test_bit(hwc->idx, used_mask))
642 __set_bit(hwc->idx, used_mask);
644 assign[i] = hwc->idx;
653 bitmap_zero(used_mask, X86_PMC_IDX_MAX);
656 * weight = number of possible counters
658 * 1 = most constrained, only works on one counter
659 * wmax = least constrained, works on any counter
661 * assign events to counters starting with most
662 * constrained events.
664 wmax = x86_pmu.num_counters;
667 * when fixed event counters are present,
668 * wmax is incremented by 1 to account
669 * for one more choice
671 if (x86_pmu.num_counters_fixed)
674 for (w = 1, num = n; num && w <= wmax; w++) {
676 for (i = 0; num && i < n; i++) {
678 hwc = &cpuc->event_list[i]->hw;
683 for_each_set_bit(j, c->idxmsk, X86_PMC_IDX_MAX) {
684 if (!test_bit(j, used_mask))
688 if (j == X86_PMC_IDX_MAX)
691 __set_bit(j, used_mask);
700 * scheduling failed or is just a simulation,
701 * free resources if necessary
703 if (!assign || num) {
704 for (i = 0; i < n; i++) {
705 if (x86_pmu.put_event_constraints)
706 x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]);
709 return num ? -ENOSPC : 0;
713 * dogrp: true if must collect siblings events (group)
714 * returns total number of events and error code
716 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
718 struct perf_event *event;
721 max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
723 /* current number of events already accepted */
726 if (is_x86_event(leader)) {
729 cpuc->event_list[n] = leader;
735 list_for_each_entry(event, &leader->sibling_list, group_entry) {
736 if (!is_x86_event(event) ||
737 event->state <= PERF_EVENT_STATE_OFF)
743 cpuc->event_list[n] = event;
749 static inline void x86_assign_hw_event(struct perf_event *event,
750 struct cpu_hw_events *cpuc, int i)
752 struct hw_perf_event *hwc = &event->hw;
754 hwc->idx = cpuc->assign[i];
755 hwc->last_cpu = smp_processor_id();
756 hwc->last_tag = ++cpuc->tags[i];
758 if (hwc->idx == X86_PMC_IDX_FIXED_BTS) {
759 hwc->config_base = 0;
761 } else if (hwc->idx >= X86_PMC_IDX_FIXED) {
762 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
764 * We set it so that event_base + idx in wrmsr/rdmsr maps to
765 * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
768 MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED;
770 hwc->config_base = x86_pmu.eventsel;
771 hwc->event_base = x86_pmu.perfctr;
775 static inline int match_prev_assignment(struct hw_perf_event *hwc,
776 struct cpu_hw_events *cpuc,
779 return hwc->idx == cpuc->assign[i] &&
780 hwc->last_cpu == smp_processor_id() &&
781 hwc->last_tag == cpuc->tags[i];
784 static int x86_pmu_start(struct perf_event *event);
785 static void x86_pmu_stop(struct perf_event *event);
787 void hw_perf_enable(void)
789 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
790 struct perf_event *event;
791 struct hw_perf_event *hwc;
792 int i, added = cpuc->n_added;
794 if (!x86_pmu_initialized())
801 int n_running = cpuc->n_events - cpuc->n_added;
803 * apply assignment obtained either from
804 * hw_perf_group_sched_in() or x86_pmu_enable()
806 * step1: save events moving to new counters
807 * step2: reprogram moved events into new counters
809 for (i = 0; i < n_running; i++) {
810 event = cpuc->event_list[i];
814 * we can avoid reprogramming counter if:
815 * - assigned same counter as last time
816 * - running on same CPU as last time
817 * - no other event has used the counter since
819 if (hwc->idx == -1 ||
820 match_prev_assignment(hwc, cpuc, i))
826 for (i = 0; i < cpuc->n_events; i++) {
827 event = cpuc->event_list[i];
830 if (!match_prev_assignment(hwc, cpuc, i))
831 x86_assign_hw_event(event, cpuc, i);
832 else if (i < n_running)
835 x86_pmu_start(event);
838 perf_events_lapic_init();
844 x86_pmu.enable_all(added);
847 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
850 wrmsrl(hwc->config_base + hwc->idx, hwc->config | enable_mask);
853 static inline void x86_pmu_disable_event(struct perf_event *event)
855 struct hw_perf_event *hwc = &event->hw;
857 wrmsrl(hwc->config_base + hwc->idx, hwc->config);
860 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
863 * Set the next IRQ period, based on the hwc->period_left value.
864 * To be called with the event disabled in hw:
867 x86_perf_event_set_period(struct perf_event *event)
869 struct hw_perf_event *hwc = &event->hw;
870 s64 left = atomic64_read(&hwc->period_left);
871 s64 period = hwc->sample_period;
872 int ret = 0, idx = hwc->idx;
874 if (idx == X86_PMC_IDX_FIXED_BTS)
878 * If we are way outside a reasonable range then just skip forward:
880 if (unlikely(left <= -period)) {
882 atomic64_set(&hwc->period_left, left);
883 hwc->last_period = period;
887 if (unlikely(left <= 0)) {
889 atomic64_set(&hwc->period_left, left);
890 hwc->last_period = period;
894 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
896 if (unlikely(left < 2))
899 if (left > x86_pmu.max_period)
900 left = x86_pmu.max_period;
902 per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
905 * The hw event starts counting from this event offset,
906 * mark it to be able to extra future deltas:
908 atomic64_set(&hwc->prev_count, (u64)-left);
910 wrmsrl(hwc->event_base + idx,
911 (u64)(-left) & x86_pmu.cntval_mask);
913 perf_event_update_userpage(event);
918 static void x86_pmu_enable_event(struct perf_event *event)
920 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
922 __x86_pmu_enable_event(&event->hw,
923 ARCH_PERFMON_EVENTSEL_ENABLE);
927 * activate a single event
929 * The event is added to the group of enabled events
930 * but only if it can be scehduled with existing events.
932 * Called with PMU disabled. If successful and return value 1,
933 * then guaranteed to call perf_enable() and hw_perf_enable()
935 static int x86_pmu_enable(struct perf_event *event)
937 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
938 struct hw_perf_event *hwc;
939 int assign[X86_PMC_IDX_MAX];
945 n = collect_events(cpuc, event, false);
949 ret = x86_pmu.schedule_events(cpuc, n, assign);
953 * copy new assignment, now we know it is possible
954 * will be used by hw_perf_enable()
956 memcpy(cpuc->assign, assign, n*sizeof(int));
959 cpuc->n_added += n - n0;
964 static int x86_pmu_start(struct perf_event *event)
966 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
967 int idx = event->hw.idx;
972 x86_perf_event_set_period(event);
973 cpuc->events[idx] = event;
974 __set_bit(idx, cpuc->active_mask);
975 x86_pmu.enable(event);
976 perf_event_update_userpage(event);
981 static void x86_pmu_unthrottle(struct perf_event *event)
983 int ret = x86_pmu_start(event);
987 void perf_event_print_debug(void)
989 u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
991 struct cpu_hw_events *cpuc;
995 if (!x86_pmu.num_counters)
998 local_irq_save(flags);
1000 cpu = smp_processor_id();
1001 cpuc = &per_cpu(cpu_hw_events, cpu);
1003 if (x86_pmu.version >= 2) {
1004 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1005 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1006 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1007 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1008 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1011 pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl);
1012 pr_info("CPU#%d: status: %016llx\n", cpu, status);
1013 pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow);
1014 pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed);
1015 pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs);
1017 pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1019 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1020 rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl);
1021 rdmsrl(x86_pmu.perfctr + idx, pmc_count);
1023 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1025 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1026 cpu, idx, pmc_ctrl);
1027 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1028 cpu, idx, pmc_count);
1029 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1030 cpu, idx, prev_left);
1032 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1033 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1035 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1036 cpu, idx, pmc_count);
1038 local_irq_restore(flags);
1041 static void x86_pmu_stop(struct perf_event *event)
1043 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1044 struct hw_perf_event *hwc = &event->hw;
1047 if (!__test_and_clear_bit(idx, cpuc->active_mask))
1050 x86_pmu.disable(event);
1053 * Drain the remaining delta count out of a event
1054 * that we are disabling:
1056 x86_perf_event_update(event);
1058 cpuc->events[idx] = NULL;
1061 static void x86_pmu_disable(struct perf_event *event)
1063 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1066 x86_pmu_stop(event);
1068 for (i = 0; i < cpuc->n_events; i++) {
1069 if (event == cpuc->event_list[i]) {
1071 if (x86_pmu.put_event_constraints)
1072 x86_pmu.put_event_constraints(cpuc, event);
1074 while (++i < cpuc->n_events)
1075 cpuc->event_list[i-1] = cpuc->event_list[i];
1081 perf_event_update_userpage(event);
1084 static int x86_pmu_handle_irq(struct pt_regs *regs)
1086 struct perf_sample_data data;
1087 struct cpu_hw_events *cpuc;
1088 struct perf_event *event;
1089 struct hw_perf_event *hwc;
1090 int idx, handled = 0;
1093 perf_sample_data_init(&data, 0);
1095 cpuc = &__get_cpu_var(cpu_hw_events);
1097 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1098 if (!test_bit(idx, cpuc->active_mask))
1101 event = cpuc->events[idx];
1104 val = x86_perf_event_update(event);
1105 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1112 data.period = event->hw.last_period;
1114 if (!x86_perf_event_set_period(event))
1117 if (perf_event_overflow(event, 1, &data, regs))
1118 x86_pmu_stop(event);
1122 inc_irq_stat(apic_perf_irqs);
1127 void smp_perf_pending_interrupt(struct pt_regs *regs)
1131 inc_irq_stat(apic_pending_irqs);
1132 perf_event_do_pending();
1136 void set_perf_event_pending(void)
1138 #ifdef CONFIG_X86_LOCAL_APIC
1139 if (!x86_pmu.apic || !x86_pmu_initialized())
1142 apic->send_IPI_self(LOCAL_PENDING_VECTOR);
1146 void perf_events_lapic_init(void)
1148 if (!x86_pmu.apic || !x86_pmu_initialized())
1152 * Always use NMI for PMU
1154 apic_write(APIC_LVTPC, APIC_DM_NMI);
1157 static int __kprobes
1158 perf_event_nmi_handler(struct notifier_block *self,
1159 unsigned long cmd, void *__args)
1161 struct die_args *args = __args;
1162 struct pt_regs *regs;
1164 if (!atomic_read(&active_events))
1178 apic_write(APIC_LVTPC, APIC_DM_NMI);
1180 * Can't rely on the handled return value to say it was our NMI, two
1181 * events could trigger 'simultaneously' raising two back-to-back NMIs.
1183 * If the first NMI handles both, the latter will be empty and daze
1186 x86_pmu.handle_irq(regs);
1191 static __read_mostly struct notifier_block perf_event_nmi_notifier = {
1192 .notifier_call = perf_event_nmi_handler,
1197 static struct event_constraint unconstrained;
1198 static struct event_constraint emptyconstraint;
1200 static struct event_constraint *
1201 x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1203 struct event_constraint *c;
1205 if (x86_pmu.event_constraints) {
1206 for_each_event_constraint(c, x86_pmu.event_constraints) {
1207 if ((event->hw.config & c->cmask) == c->code)
1212 return &unconstrained;
1215 static int x86_event_sched_in(struct perf_event *event,
1216 struct perf_cpu_context *cpuctx)
1220 event->state = PERF_EVENT_STATE_ACTIVE;
1221 event->oncpu = smp_processor_id();
1222 event->tstamp_running += event->ctx->time - event->tstamp_stopped;
1224 if (!is_x86_event(event))
1225 ret = event->pmu->enable(event);
1227 if (!ret && !is_software_event(event))
1228 cpuctx->active_oncpu++;
1230 if (!ret && event->attr.exclusive)
1231 cpuctx->exclusive = 1;
1236 static void x86_event_sched_out(struct perf_event *event,
1237 struct perf_cpu_context *cpuctx)
1239 event->state = PERF_EVENT_STATE_INACTIVE;
1242 if (!is_x86_event(event))
1243 event->pmu->disable(event);
1245 event->tstamp_running -= event->ctx->time - event->tstamp_stopped;
1247 if (!is_software_event(event))
1248 cpuctx->active_oncpu--;
1250 if (event->attr.exclusive || !cpuctx->active_oncpu)
1251 cpuctx->exclusive = 0;
1255 * Called to enable a whole group of events.
1256 * Returns 1 if the group was enabled, or -EAGAIN if it could not be.
1257 * Assumes the caller has disabled interrupts and has
1258 * frozen the PMU with hw_perf_save_disable.
1260 * called with PMU disabled. If successful and return value 1,
1261 * then guaranteed to call perf_enable() and hw_perf_enable()
1263 int hw_perf_group_sched_in(struct perf_event *leader,
1264 struct perf_cpu_context *cpuctx,
1265 struct perf_event_context *ctx)
1267 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1268 struct perf_event *sub;
1269 int assign[X86_PMC_IDX_MAX];
1272 if (!x86_pmu_initialized())
1275 /* n0 = total number of events */
1276 n0 = collect_events(cpuc, leader, true);
1280 ret = x86_pmu.schedule_events(cpuc, n0, assign);
1284 ret = x86_event_sched_in(leader, cpuctx);
1289 list_for_each_entry(sub, &leader->sibling_list, group_entry) {
1290 if (sub->state > PERF_EVENT_STATE_OFF) {
1291 ret = x86_event_sched_in(sub, cpuctx);
1298 * copy new assignment, now we know it is possible
1299 * will be used by hw_perf_enable()
1301 memcpy(cpuc->assign, assign, n0*sizeof(int));
1303 cpuc->n_events = n0;
1304 cpuc->n_added += n1;
1305 ctx->nr_active += n1;
1308 * 1 means successful and events are active
1309 * This is not quite true because we defer
1310 * actual activation until hw_perf_enable() but
1311 * this way we* ensure caller won't try to enable
1316 x86_event_sched_out(leader, cpuctx);
1318 list_for_each_entry(sub, &leader->sibling_list, group_entry) {
1319 if (sub->state == PERF_EVENT_STATE_ACTIVE) {
1320 x86_event_sched_out(sub, cpuctx);
1328 #include "perf_event_amd.c"
1329 #include "perf_event_p6.c"
1330 #include "perf_event_p4.c"
1331 #include "perf_event_intel_lbr.c"
1332 #include "perf_event_intel_ds.c"
1333 #include "perf_event_intel.c"
1335 static int __cpuinit
1336 x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1338 unsigned int cpu = (long)hcpu;
1339 int ret = NOTIFY_OK;
1341 switch (action & ~CPU_TASKS_FROZEN) {
1342 case CPU_UP_PREPARE:
1343 if (x86_pmu.cpu_prepare)
1344 ret = x86_pmu.cpu_prepare(cpu);
1348 if (x86_pmu.cpu_starting)
1349 x86_pmu.cpu_starting(cpu);
1353 if (x86_pmu.cpu_dying)
1354 x86_pmu.cpu_dying(cpu);
1357 case CPU_UP_CANCELED:
1359 if (x86_pmu.cpu_dead)
1360 x86_pmu.cpu_dead(cpu);
1370 static void __init pmu_check_apic(void)
1376 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1377 pr_info("no hardware sampling interrupt available.\n");
1380 void __init init_hw_perf_events(void)
1382 struct event_constraint *c;
1385 pr_info("Performance Events: ");
1387 switch (boot_cpu_data.x86_vendor) {
1388 case X86_VENDOR_INTEL:
1389 err = intel_pmu_init();
1391 case X86_VENDOR_AMD:
1392 err = amd_pmu_init();
1398 pr_cont("no PMU driver, software events only.\n");
1404 pr_cont("%s PMU driver.\n", x86_pmu.name);
1409 if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) {
1410 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
1411 x86_pmu.num_counters, X86_PMC_MAX_GENERIC);
1412 x86_pmu.num_counters = X86_PMC_MAX_GENERIC;
1414 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1415 perf_max_events = x86_pmu.num_counters;
1417 if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) {
1418 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
1419 x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED);
1420 x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED;
1423 x86_pmu.intel_ctrl |=
1424 ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED;
1426 perf_events_lapic_init();
1427 register_die_notifier(&perf_event_nmi_notifier);
1429 unconstrained = (struct event_constraint)
1430 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1431 0, x86_pmu.num_counters);
1433 if (x86_pmu.event_constraints) {
1434 for_each_event_constraint(c, x86_pmu.event_constraints) {
1435 if (c->cmask != X86_RAW_EVENT_MASK)
1438 c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
1439 c->weight += x86_pmu.num_counters;
1443 pr_info("... version: %d\n", x86_pmu.version);
1444 pr_info("... bit width: %d\n", x86_pmu.cntval_bits);
1445 pr_info("... generic registers: %d\n", x86_pmu.num_counters);
1446 pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask);
1447 pr_info("... max period: %016Lx\n", x86_pmu.max_period);
1448 pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed);
1449 pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl);
1451 perf_cpu_notifier(x86_pmu_notifier);
1454 static inline void x86_pmu_read(struct perf_event *event)
1456 x86_perf_event_update(event);
1459 static const struct pmu pmu = {
1460 .enable = x86_pmu_enable,
1461 .disable = x86_pmu_disable,
1462 .start = x86_pmu_start,
1463 .stop = x86_pmu_stop,
1464 .read = x86_pmu_read,
1465 .unthrottle = x86_pmu_unthrottle,
1469 * validate that we can schedule this event
1471 static int validate_event(struct perf_event *event)
1473 struct cpu_hw_events *fake_cpuc;
1474 struct event_constraint *c;
1477 fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1481 c = x86_pmu.get_event_constraints(fake_cpuc, event);
1483 if (!c || !c->weight)
1486 if (x86_pmu.put_event_constraints)
1487 x86_pmu.put_event_constraints(fake_cpuc, event);
1495 * validate a single event group
1497 * validation include:
1498 * - check events are compatible which each other
1499 * - events do not compete for the same counter
1500 * - number of events <= number of counters
1502 * validation ensures the group can be loaded onto the
1503 * PMU if it was the only group available.
1505 static int validate_group(struct perf_event *event)
1507 struct perf_event *leader = event->group_leader;
1508 struct cpu_hw_events *fake_cpuc;
1512 fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1517 * the event is not yet connected with its
1518 * siblings therefore we must first collect
1519 * existing siblings, then add the new event
1520 * before we can simulate the scheduling
1523 n = collect_events(fake_cpuc, leader, true);
1527 fake_cpuc->n_events = n;
1528 n = collect_events(fake_cpuc, event, false);
1532 fake_cpuc->n_events = n;
1534 ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
1542 const struct pmu *hw_perf_event_init(struct perf_event *event)
1544 const struct pmu *tmp;
1547 err = __hw_perf_event_init(event);
1550 * we temporarily connect event to its pmu
1551 * such that validate_group() can classify
1552 * it as an x86 event using is_x86_event()
1557 if (event->group_leader != event)
1558 err = validate_group(event);
1560 err = validate_event(event);
1566 event->destroy(event);
1567 return ERR_PTR(err);
1578 void callchain_store(struct perf_callchain_entry *entry, u64 ip)
1580 if (entry->nr < PERF_MAX_STACK_DEPTH)
1581 entry->ip[entry->nr++] = ip;
1584 static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_irq_entry);
1585 static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_nmi_entry);
1589 backtrace_warning_symbol(void *data, char *msg, unsigned long symbol)
1591 /* Ignore warnings */
1594 static void backtrace_warning(void *data, char *msg)
1596 /* Ignore warnings */
1599 static int backtrace_stack(void *data, char *name)
1604 static void backtrace_address(void *data, unsigned long addr, int reliable)
1606 struct perf_callchain_entry *entry = data;
1608 callchain_store(entry, addr);
1611 static const struct stacktrace_ops backtrace_ops = {
1612 .warning = backtrace_warning,
1613 .warning_symbol = backtrace_warning_symbol,
1614 .stack = backtrace_stack,
1615 .address = backtrace_address,
1616 .walk_stack = print_context_stack_bp,
1619 #include "../dumpstack.h"
1622 perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry)
1624 callchain_store(entry, PERF_CONTEXT_KERNEL);
1625 callchain_store(entry, regs->ip);
1627 dump_trace(NULL, regs, NULL, regs->bp, &backtrace_ops, entry);
1630 #ifdef CONFIG_COMPAT
1632 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1634 /* 32-bit process in 64-bit kernel. */
1635 struct stack_frame_ia32 frame;
1636 const void __user *fp;
1638 if (!test_thread_flag(TIF_IA32))
1641 fp = compat_ptr(regs->bp);
1642 while (entry->nr < PERF_MAX_STACK_DEPTH) {
1643 unsigned long bytes;
1644 frame.next_frame = 0;
1645 frame.return_address = 0;
1647 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1648 if (bytes != sizeof(frame))
1651 if (fp < compat_ptr(regs->sp))
1654 callchain_store(entry, frame.return_address);
1655 fp = compat_ptr(frame.next_frame);
1661 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1668 perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry)
1670 struct stack_frame frame;
1671 const void __user *fp;
1673 if (!user_mode(regs))
1674 regs = task_pt_regs(current);
1676 fp = (void __user *)regs->bp;
1678 callchain_store(entry, PERF_CONTEXT_USER);
1679 callchain_store(entry, regs->ip);
1681 if (perf_callchain_user32(regs, entry))
1684 while (entry->nr < PERF_MAX_STACK_DEPTH) {
1685 unsigned long bytes;
1686 frame.next_frame = NULL;
1687 frame.return_address = 0;
1689 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1690 if (bytes != sizeof(frame))
1693 if ((unsigned long)fp < regs->sp)
1696 callchain_store(entry, frame.return_address);
1697 fp = frame.next_frame;
1702 perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry)
1709 is_user = user_mode(regs);
1711 if (is_user && current->state != TASK_RUNNING)
1715 perf_callchain_kernel(regs, entry);
1718 perf_callchain_user(regs, entry);
1721 struct perf_callchain_entry *perf_callchain(struct pt_regs *regs)
1723 struct perf_callchain_entry *entry;
1725 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1726 /* TODO: We don't support guest os callchain now */
1731 entry = &__get_cpu_var(pmc_nmi_entry);
1733 entry = &__get_cpu_var(pmc_irq_entry);
1737 perf_do_callchain(regs, entry);
1742 void perf_arch_fetch_caller_regs(struct pt_regs *regs, unsigned long ip, int skip)
1746 * perf_arch_fetch_caller_regs adds another call, we need to increment
1749 regs->bp = rewind_frame_pointer(skip + 1);
1750 regs->cs = __KERNEL_CS;
1751 local_save_flags(regs->flags);
1754 unsigned long perf_instruction_pointer(struct pt_regs *regs)
1758 if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
1759 ip = perf_guest_cbs->get_guest_ip();
1761 ip = instruction_pointer(regs);
1766 unsigned long perf_misc_flags(struct pt_regs *regs)
1770 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1771 if (perf_guest_cbs->is_user_mode())
1772 misc |= PERF_RECORD_MISC_GUEST_USER;
1774 misc |= PERF_RECORD_MISC_GUEST_KERNEL;
1776 if (user_mode(regs))
1777 misc |= PERF_RECORD_MISC_USER;
1779 misc |= PERF_RECORD_MISC_KERNEL;
1782 if (regs->flags & PERF_EFLAGS_EXACT)
1783 misc |= PERF_RECORD_MISC_EXACT;