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   1 /*
   2  * Performance events x86 architecture code
   3  *
   4  *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
   5  *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
   6  *  Copyright (C) 2009 Jaswinder Singh Rajput
   7  *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
   8  *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
   9  *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
  10  *  Copyright (C) 2009 Google, Inc., Stephane Eranian
  11  *
  12  *  For licencing details see kernel-base/COPYING
  13  */
  14
  15 #include <linux/perf_event.h>
  16 #include <linux/capability.h>
  17 #include <linux/notifier.h>
  18 #include <linux/hardirq.h>
  19 #include <linux/kprobes.h>
  20 #include <linux/module.h>
  21 #include <linux/kdebug.h>
  22 #include <linux/sched.h>
  23 #include <linux/uaccess.h>
  24 #include <linux/slab.h>
  25 #include <linux/highmem.h>
  26 #include <linux/cpu.h>
  27 #include <linux/bitops.h>
  28
  29 #include <asm/apic.h>
  30 #include <asm/stacktrace.h>
  31 #include <asm/nmi.h>
  32 #include <asm/compat.h>
  33
  34 #if 0
  35 #undef wrmsrl
  36 #define wrmsrl(msr, val)                                        \
  37 do {                                                            \
  38         trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\
  39                         (unsigned long)(val));                  \
  40         native_write_msr((msr), (u32)((u64)(val)),              \
  41                         (u32)((u64)(val) >> 32));               \
  42 } while (0)
  43 #endif
  44
  45 /*
  46  * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
  47  */
  48 static unsigned long
  49 copy_from_user_nmi(void *to, const void __user *from, unsigned long n)
  50 {
  51         unsigned long offset, addr = (unsigned long)from;
  52         int type = in_nmi() ? KM_NMI : KM_IRQ0;
  53         unsigned long size, len = 0;
  54         struct page *page;
  55         void *map;
  56         int ret;
  57
  58         do {
  59                 ret = __get_user_pages_fast(addr, 1, 0, &page);
  60                 if (!ret)
  61                         break;
  62
  63                 offset = addr & (PAGE_SIZE - 1);
  64                 size = min(PAGE_SIZE - offset, n - len);
  65
  66                 map = kmap_atomic(page, type);
  67                 memcpy(to, map+offset, size);
  68                 kunmap_atomic(map, type);
  69                 put_page(page);
  70
  71                 len  += size;
  72                 to   += size;
  73                 addr += size;
  74
  75         } while (len < n);
  76
  77         return len;
  78 }
  79
  80 struct event_constraint {
  81         union {
  82                 unsigned long   idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
  83                 u64             idxmsk64;
  84         };
  85         u64     code;
  86         u64     cmask;
  87         int     weight;
  88 };
  89
  90 struct amd_nb {
  91         int nb_id;  /* NorthBridge id */
  92         int refcnt; /* reference count */
  93         struct perf_event *owners[X86_PMC_IDX_MAX];
  94         struct event_constraint event_constraints[X86_PMC_IDX_MAX];
  95 };
  96
  97 #define MAX_LBR_ENTRIES         16
  98
  99 struct cpu_hw_events {
 100         /*
 101          * Generic x86 PMC bits
 102          */
 103         struct perf_event       *events[X86_PMC_IDX_MAX]; /* in counter order */
 104         unsigned long           active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 105         int                     enabled;
 106
 107         int                     n_events;
 108         int                     n_added;
 109         int                     assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
 110         u64                     tags[X86_PMC_IDX_MAX];
 111         struct perf_event       *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
 112
 113         /*
 114          * Intel DebugStore bits
 115          */
 116         struct debug_store      *ds;
 117         u64                     pebs_enabled;
 118
 119         /*
 120          * Intel LBR bits
 121          */
 122         int                             lbr_users;
 123         void                            *lbr_context;
 124         struct perf_branch_stack        lbr_stack;
 125         struct perf_branch_entry        lbr_entries[MAX_LBR_ENTRIES];
 126
 127         /*
 128          * AMD specific bits
 129          */
 130         struct amd_nb           *amd_nb;
 131 };
 132
 133 #define __EVENT_CONSTRAINT(c, n, m, w) {\
 134         { .idxmsk64 = (n) },            \
 135         .code = (c),                    \
 136         .cmask = (m),                   \
 137         .weight = (w),                  \
 138 }
 139
 140 #define EVENT_CONSTRAINT(c, n, m)       \
 141         __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n))
 142
 143 /*
 144  * Constraint on the Event code.
 145  */
 146 #define INTEL_EVENT_CONSTRAINT(c, n)    \
 147         EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
 148
 149 /*
 150  * Constraint on the Event code + UMask + fixed-mask
 151  *
 152  * filter mask to validate fixed counter events.
 153  * the following filters disqualify for fixed counters:
 154  *  - inv
 155  *  - edge
 156  *  - cnt-mask
 157  *  The other filters are supported by fixed counters.
 158  *  The any-thread option is supported starting with v3.
 159  */
 160 #define FIXED_EVENT_CONSTRAINT(c, n)    \
 161         EVENT_CONSTRAINT(c, (1ULL << (32+n)), X86_RAW_EVENT_MASK)
 162
 163 /*
 164  * Constraint on the Event code + UMask
 165  */
 166 #define PEBS_EVENT_CONSTRAINT(c, n)     \
 167         EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
 168
 169 #define EVENT_CONSTRAINT_END            \
 170         EVENT_CONSTRAINT(0, 0, 0)
 171
 172 #define for_each_event_constraint(e, c) \
 173         for ((e) = (c); (e)->weight; (e)++)
 174
 175 union perf_capabilities {
 176         struct {
 177                 u64     lbr_format    : 6;
 178                 u64     pebs_trap     : 1;
 179                 u64     pebs_arch_reg : 1;
 180                 u64     pebs_format   : 4;
 181                 u64     smm_freeze    : 1;
 182         };
 183         u64     capabilities;
 184 };
 185
 186 /*
 187  * struct x86_pmu - generic x86 pmu
 188  */
 189 struct x86_pmu {
 190         /*
 191          * Generic x86 PMC bits
 192          */
 193         const char      *name;
 194         int             version;
 195         int             (*handle_irq)(struct pt_regs *);
 196         void            (*disable_all)(void);
 197         void            (*enable_all)(int added);
 198         void            (*enable)(struct perf_event *);
 199         void            (*disable)(struct perf_event *);
 200         int             (*hw_config)(struct perf_event *event);
 201         int             (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
 202         unsigned        eventsel;
 203         unsigned        perfctr;
 204         u64             (*event_map)(int);
 205         int             max_events;
 206         int             num_counters;
 207         int             num_counters_fixed;
 208         int             cntval_bits;
 209         u64             cntval_mask;
 210         int             apic;
 211         u64             max_period;
 212         struct event_constraint *
 213                         (*get_event_constraints)(struct cpu_hw_events *cpuc,
 214                                                  struct perf_event *event);
 215
 216         void            (*put_event_constraints)(struct cpu_hw_events *cpuc,
 217                                                  struct perf_event *event);
 218         struct event_constraint *event_constraints;
 219         void            (*quirks)(void);
 220
 221         int             (*cpu_prepare)(int cpu);
 222         void            (*cpu_starting)(int cpu);
 223         void            (*cpu_dying)(int cpu);
 224         void            (*cpu_dead)(int cpu);
 225
 226         /*
 227          * Intel Arch Perfmon v2+
 228          */
 229         u64                     intel_ctrl;
 230         union perf_capabilities intel_cap;
 231
 232         /*
 233          * Intel DebugStore bits
 234          */
 235         int             bts, pebs;
 236         int             pebs_record_size;
 237         void            (*drain_pebs)(struct pt_regs *regs);
 238         struct event_constraint *pebs_constraints;
 239
 240         /*
 241          * Intel LBR
 242          */
 243         unsigned long   lbr_tos, lbr_from, lbr_to; /* MSR base regs       */
 244         int             lbr_nr;                    /* hardware stack size */
 245 };
 246
 247 static struct x86_pmu x86_pmu __read_mostly;
 248
 249 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
 250         .enabled = 1,
 251 };
 252
 253 static int x86_perf_event_set_period(struct perf_event *event);
 254
 255 /*
 256  * Generalized hw caching related hw_event table, filled
 257  * in on a per model basis. A value of 0 means
 258  * 'not supported', -1 means 'hw_event makes no sense on
 259  * this CPU', any other value means the raw hw_event
 260  * ID.
 261  */
 262
 263 #define C(x) PERF_COUNT_HW_CACHE_##x
 264
 265 static u64 __read_mostly hw_cache_event_ids
 266                                 [PERF_COUNT_HW_CACHE_MAX]
 267                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 268                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
 269
 270 /*
 271  * Propagate event elapsed time into the generic event.
 272  * Can only be executed on the CPU where the event is active.
 273  * Returns the delta events processed.
 274  */
 275 static u64
 276 x86_perf_event_update(struct perf_event *event)
 277 {
 278         struct hw_perf_event *hwc = &event->hw;
 279         int shift = 64 - x86_pmu.cntval_bits;
 280         u64 prev_raw_count, new_raw_count;
 281         int idx = hwc->idx;
 282         s64 delta;
 283
 284         if (idx == X86_PMC_IDX_FIXED_BTS)
 285                 return 0;
 286
 287         /*
 288          * Careful: an NMI might modify the previous event value.
 289          *
 290          * Our tactic to handle this is to first atomically read and
 291          * exchange a new raw count - then add that new-prev delta
 292          * count to the generic event atomically:
 293          */
 294 again:
 295         prev_raw_count = atomic64_read(&hwc->prev_count);
 296         rdmsrl(hwc->event_base + idx, new_raw_count);
 297
 298         if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
 299                                         new_raw_count) != prev_raw_count)
 300                 goto again;
 301
 302         /*
 303          * Now we have the new raw value and have updated the prev
 304          * timestamp already. We can now calculate the elapsed delta
 305          * (event-)time and add that to the generic event.
 306          *
 307          * Careful, not all hw sign-extends above the physical width
 308          * of the count.
 309          */
 310         delta = (new_raw_count << shift) - (prev_raw_count << shift);
 311         delta >>= shift;
 312
 313         atomic64_add(delta, &event->count);
 314         atomic64_sub(delta, &hwc->period_left);
 315
 316         return new_raw_count;
 317 }
 318
 319 static atomic_t active_events;
 320 static DEFINE_MUTEX(pmc_reserve_mutex);
 321
 322 #ifdef CONFIG_X86_LOCAL_APIC
 323
 324 static bool reserve_pmc_hardware(void)
 325 {
 326         int i;
 327
 328         if (nmi_watchdog == NMI_LOCAL_APIC)
 329                 disable_lapic_nmi_watchdog();
 330
 331         for (i = 0; i < x86_pmu.num_counters; i++) {
 332                 if (!reserve_perfctr_nmi(x86_pmu.perfctr + i))
 333                         goto perfctr_fail;
 334         }
 335
 336         for (i = 0; i < x86_pmu.num_counters; i++) {
 337                 if (!reserve_evntsel_nmi(x86_pmu.eventsel + i))
 338                         goto eventsel_fail;
 339         }
 340
 341         return true;
 342
 343 eventsel_fail:
 344         for (i--; i >= 0; i--)
 345                 release_evntsel_nmi(x86_pmu.eventsel + i);
 346
 347         i = x86_pmu.num_counters;
 348
 349 perfctr_fail:
 350         for (i--; i >= 0; i--)
 351                 release_perfctr_nmi(x86_pmu.perfctr + i);
 352
 353         if (nmi_watchdog == NMI_LOCAL_APIC)
 354                 enable_lapic_nmi_watchdog();
 355
 356         return false;
 357 }
 358
 359 static void release_pmc_hardware(void)
 360 {
 361         int i;
 362
 363         for (i = 0; i < x86_pmu.num_counters; i++) {
 364                 release_perfctr_nmi(x86_pmu.perfctr + i);
 365                 release_evntsel_nmi(x86_pmu.eventsel + i);
 366         }
 367
 368         if (nmi_watchdog == NMI_LOCAL_APIC)
 369                 enable_lapic_nmi_watchdog();
 370 }
 371
 372 #else
 373
 374 static bool reserve_pmc_hardware(void) { return true; }
 375 static void release_pmc_hardware(void) {}
 376
 377 #endif
 378
 379 static int reserve_ds_buffers(void);
 380 static void release_ds_buffers(void);
 381
 382 static void hw_perf_event_destroy(struct perf_event *event)
 383 {
 384         if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
 385                 release_pmc_hardware();
 386                 release_ds_buffers();
 387                 mutex_unlock(&pmc_reserve_mutex);
 388         }
 389 }
 390
 391 static inline int x86_pmu_initialized(void)
 392 {
 393         return x86_pmu.handle_irq != NULL;
 394 }
 395
 396 static inline int
 397 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event_attr *attr)
 398 {
 399         unsigned int cache_type, cache_op, cache_result;
 400         u64 config, val;
 401
 402         config = attr->config;
 403
 404         cache_type = (config >>  0) & 0xff;
 405         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
 406                 return -EINVAL;
 407
 408         cache_op = (config >>  8) & 0xff;
 409         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
 410                 return -EINVAL;
 411
 412         cache_result = (config >> 16) & 0xff;
 413         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
 414                 return -EINVAL;
 415
 416         val = hw_cache_event_ids[cache_type][cache_op][cache_result];
 417
 418         if (val == 0)
 419                 return -ENOENT;
 420
 421         if (val == -1)
 422                 return -EINVAL;
 423
 424         hwc->config |= val;
 425
 426         return 0;
 427 }
 428
 429 static int x86_setup_perfctr(struct perf_event *event)
 430 {
 431         struct perf_event_attr *attr = &event->attr;
 432         struct hw_perf_event *hwc = &event->hw;
 433         u64 config;
 434
 435         if (!hwc->sample_period) {
 436                 hwc->sample_period = x86_pmu.max_period;
 437                 hwc->last_period = hwc->sample_period;
 438                 atomic64_set(&hwc->period_left, hwc->sample_period);
 439         } else {
 440                 /*
 441                  * If we have a PMU initialized but no APIC
 442                  * interrupts, we cannot sample hardware
 443                  * events (user-space has to fall back and
 444                  * sample via a hrtimer based software event):
 445                  */
 446                 if (!x86_pmu.apic)
 447                         return -EOPNOTSUPP;
 448         }
 449
 450         if (attr->type == PERF_TYPE_RAW)
 451                 return 0;
 452
 453         if (attr->type == PERF_TYPE_HW_CACHE)
 454                 return set_ext_hw_attr(hwc, attr);
 455
 456         if (attr->config >= x86_pmu.max_events)
 457                 return -EINVAL;
 458
 459         /*
 460          * The generic map:
 461          */
 462         config = x86_pmu.event_map(attr->config);
 463
 464         if (config == 0)
 465                 return -ENOENT;
 466
 467         if (config == -1LL)
 468                 return -EINVAL;
 469
 470         /*
 471          * Branch tracing:
 472          */
 473         if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) &&
 474             (hwc->sample_period == 1)) {
 475                 /* BTS is not supported by this architecture. */
 476                 if (!x86_pmu.bts)
 477                         return -EOPNOTSUPP;
 478
 479                 /* BTS is currently only allowed for user-mode. */
 480                 if (!attr->exclude_kernel)
 481                         return -EOPNOTSUPP;
 482         }
 483
 484         hwc->config |= config;
 485
 486         return 0;
 487 }
 488
 489 static int x86_pmu_hw_config(struct perf_event *event)
 490 {
 491         if (event->attr.precise_ip) {
 492                 int precise = 0;
 493
 494                 /* Support for constant skid */
 495                 if (x86_pmu.pebs)
 496                         precise++;
 497
 498                 /* Support for IP fixup */
 499                 if (x86_pmu.lbr_nr)
 500                         precise++;
 501
 502                 if (event->attr.precise_ip > precise)
 503                         return -EOPNOTSUPP;
 504         }
 505
 506         /*
 507          * Generate PMC IRQs:
 508          * (keep 'enabled' bit clear for now)
 509          */
 510         event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
 511
 512         /*
 513          * Count user and OS events unless requested not to
 514          */
 515         if (!event->attr.exclude_user)
 516                 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
 517         if (!event->attr.exclude_kernel)
 518                 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
 519
 520         if (event->attr.type == PERF_TYPE_RAW)
 521                 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
 522
 523         return x86_setup_perfctr(event);
 524 }
 525
 526 /*
 527  * Setup the hardware configuration for a given attr_type
 528  */
 529 static int __hw_perf_event_init(struct perf_event *event)
 530 {
 531         int err;
 532
 533         if (!x86_pmu_initialized())
 534                 return -ENODEV;
 535
 536         err = 0;
 537         if (!atomic_inc_not_zero(&active_events)) {
 538                 mutex_lock(&pmc_reserve_mutex);
 539                 if (atomic_read(&active_events) == 0) {
 540                         if (!reserve_pmc_hardware())
 541                                 err = -EBUSY;
 542                         else {
 543                                 err = reserve_ds_buffers();
 544                                 if (err)
 545                                         release_pmc_hardware();
 546                         }
 547                 }
 548                 if (!err)
 549                         atomic_inc(&active_events);
 550                 mutex_unlock(&pmc_reserve_mutex);
 551         }
 552         if (err)
 553                 return err;
 554
 555         event->destroy = hw_perf_event_destroy;
 556
 557         event->hw.idx = -1;
 558         event->hw.last_cpu = -1;
 559         event->hw.last_tag = ~0ULL;
 560
 561         return x86_pmu.hw_config(event);
 562 }
 563
 564 static void x86_pmu_disable_all(void)
 565 {
 566         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 567         int idx;
 568
 569         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 570                 u64 val;
 571
 572                 if (!test_bit(idx, cpuc->active_mask))
 573                         continue;
 574                 rdmsrl(x86_pmu.eventsel + idx, val);
 575                 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
 576                         continue;
 577                 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
 578                 wrmsrl(x86_pmu.eventsel + idx, val);
 579         }
 580 }
 581
 582 void hw_perf_disable(void)
 583 {
 584         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 585
 586         if (!x86_pmu_initialized())
 587                 return;
 588
 589         if (!cpuc->enabled)
 590                 return;
 591
 592         cpuc->n_added = 0;
 593         cpuc->enabled = 0;
 594         barrier();
 595
 596         x86_pmu.disable_all();
 597 }
 598
 599 static void x86_pmu_enable_all(int added)
 600 {
 601         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 602         int idx;
 603
 604         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 605                 struct perf_event *event = cpuc->events[idx];
 606                 u64 val;
 607
 608                 if (!test_bit(idx, cpuc->active_mask))
 609                         continue;
 610
 611                 val = event->hw.config;
 612                 val |= ARCH_PERFMON_EVENTSEL_ENABLE;
 613                 wrmsrl(x86_pmu.eventsel + idx, val);
 614         }
 615 }
 616
 617 static const struct pmu pmu;
 618
 619 static inline int is_x86_event(struct perf_event *event)
 620 {
 621         return event->pmu == &pmu;
 622 }
 623
 624 static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
 625 {
 626         struct event_constraint *c, *constraints[X86_PMC_IDX_MAX];
 627         unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 628         int i, j, w, wmax, num = 0;
 629         struct hw_perf_event *hwc;
 630
 631         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 632
 633         for (i = 0; i < n; i++) {
 634                 c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
 635                 constraints[i] = c;
 636         }
 637
 638         /*
 639          * fastpath, try to reuse previous register
 640          */
 641         for (i = 0; i < n; i++) {
 642                 hwc = &cpuc->event_list[i]->hw;
 643                 c = constraints[i];
 644
 645                 /* never assigned */
 646                 if (hwc->idx == -1)
 647                         break;
 648
 649                 /* constraint still honored */
 650                 if (!test_bit(hwc->idx, c->idxmsk))
 651                         break;
 652
 653                 /* not already used */
 654                 if (test_bit(hwc->idx, used_mask))
 655                         break;
 656
 657                 __set_bit(hwc->idx, used_mask);
 658                 if (assign)
 659                         assign[i] = hwc->idx;
 660         }
 661         if (i == n)
 662                 goto done;
 663
 664         /*
 665          * begin slow path
 666          */
 667
 668         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 669
 670         /*
 671          * weight = number of possible counters
 672          *
 673          * 1    = most constrained, only works on one counter
 674          * wmax = least constrained, works on any counter
 675          *
 676          * assign events to counters starting with most
 677          * constrained events.
 678          */
 679         wmax = x86_pmu.num_counters;
 680
 681         /*
 682          * when fixed event counters are present,
 683          * wmax is incremented by 1 to account
 684          * for one more choice
 685          */
 686         if (x86_pmu.num_counters_fixed)
 687                 wmax++;
 688
 689         for (w = 1, num = n; num && w <= wmax; w++) {
 690                 /* for each event */
 691                 for (i = 0; num && i < n; i++) {
 692                         c = constraints[i];
 693                         hwc = &cpuc->event_list[i]->hw;
 694
 695                         if (c->weight != w)
 696                                 continue;
 697
 698                         for_each_set_bit(j, c->idxmsk, X86_PMC_IDX_MAX) {
 699                                 if (!test_bit(j, used_mask))
 700                                         break;
 701                         }
 702
 703                         if (j == X86_PMC_IDX_MAX)
 704                                 break;
 705
 706                         __set_bit(j, used_mask);
 707
 708                         if (assign)
 709                                 assign[i] = j;
 710                         num--;
 711                 }
 712         }
 713 done:
 714         /*
 715          * scheduling failed or is just a simulation,
 716          * free resources if necessary
 717          */
 718         if (!assign || num) {
 719                 for (i = 0; i < n; i++) {
 720                         if (x86_pmu.put_event_constraints)
 721                                 x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]);
 722                 }
 723         }
 724         return num ? -ENOSPC : 0;
 725 }
 726
 727 /*
 728  * dogrp: true if must collect siblings events (group)
 729  * returns total number of events and error code
 730  */
 731 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
 732 {
 733         struct perf_event *event;
 734         int n, max_count;
 735
 736         max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
 737
 738         /* current number of events already accepted */
 739         n = cpuc->n_events;
 740
 741         if (is_x86_event(leader)) {
 742                 if (n >= max_count)
 743                         return -ENOSPC;
 744                 cpuc->event_list[n] = leader;
 745                 n++;
 746         }
 747         if (!dogrp)
 748                 return n;
 749
 750         list_for_each_entry(event, &leader->sibling_list, group_entry) {
 751                 if (!is_x86_event(event) ||
 752                     event->state <= PERF_EVENT_STATE_OFF)
 753                         continue;
 754
 755                 if (n >= max_count)
 756                         return -ENOSPC;
 757
 758                 cpuc->event_list[n] = event;
 759                 n++;
 760         }
 761         return n;
 762 }
 763
 764 static inline void x86_assign_hw_event(struct perf_event *event,
 765                                 struct cpu_hw_events *cpuc, int i)
 766 {
 767         struct hw_perf_event *hwc = &event->hw;
 768
 769         hwc->idx = cpuc->assign[i];
 770         hwc->last_cpu = smp_processor_id();
 771         hwc->last_tag = ++cpuc->tags[i];
 772
 773         if (hwc->idx == X86_PMC_IDX_FIXED_BTS) {
 774                 hwc->config_base = 0;
 775                 hwc->event_base = 0;
 776         } else if (hwc->idx >= X86_PMC_IDX_FIXED) {
 777                 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 778                 /*
 779                  * We set it so that event_base + idx in wrmsr/rdmsr maps to
 780                  * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
 781                  */
 782                 hwc->event_base =
 783                         MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED;
 784         } else {
 785                 hwc->config_base = x86_pmu.eventsel;
 786                 hwc->event_base  = x86_pmu.perfctr;
 787         }
 788 }
 789
 790 static inline int match_prev_assignment(struct hw_perf_event *hwc,
 791                                         struct cpu_hw_events *cpuc,
 792                                         int i)
 793 {
 794         return hwc->idx == cpuc->assign[i] &&
 795                 hwc->last_cpu == smp_processor_id() &&
 796                 hwc->last_tag == cpuc->tags[i];
 797 }
 798
 799 static int x86_pmu_start(struct perf_event *event);
 800 static void x86_pmu_stop(struct perf_event *event);
 801
 802 void hw_perf_enable(void)
 803 {
 804         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 805         struct perf_event *event;
 806         struct hw_perf_event *hwc;
 807         int i, added = cpuc->n_added;
 808
 809         if (!x86_pmu_initialized())
 810                 return;
 811
 812         if (cpuc->enabled)
 813                 return;
 814
 815         if (cpuc->n_added) {
 816                 int n_running = cpuc->n_events - cpuc->n_added;
 817                 /*
 818                  * apply assignment obtained either from
 819                  * hw_perf_group_sched_in() or x86_pmu_enable()
 820                  *
 821                  * step1: save events moving to new counters
 822                  * step2: reprogram moved events into new counters
 823                  */
 824                 for (i = 0; i < n_running; i++) {
 825                         event = cpuc->event_list[i];
 826                         hwc = &event->hw;
 827
 828                         /*
 829                          * we can avoid reprogramming counter if:
 830                          * - assigned same counter as last time
 831                          * - running on same CPU as last time
 832                          * - no other event has used the counter since
 833                          */
 834                         if (hwc->idx == -1 ||
 835                             match_prev_assignment(hwc, cpuc, i))
 836                                 continue;
 837
 838                         x86_pmu_stop(event);
 839                 }
 840
 841                 for (i = 0; i < cpuc->n_events; i++) {
 842                         event = cpuc->event_list[i];
 843                         hwc = &event->hw;
 844
 845                         if (!match_prev_assignment(hwc, cpuc, i))
 846                                 x86_assign_hw_event(event, cpuc, i);
 847                         else if (i < n_running)
 848                                 continue;
 849
 850                         x86_pmu_start(event);
 851                 }
 852                 cpuc->n_added = 0;
 853                 perf_events_lapic_init();
 854         }
 855
 856         cpuc->enabled = 1;
 857         barrier();
 858
 859         x86_pmu.enable_all(added);
 860 }
 861
 862 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
 863                                           u64 enable_mask)
 864 {
 865         wrmsrl(hwc->config_base + hwc->idx, hwc->config | enable_mask);
 866 }
 867
 868 static inline void x86_pmu_disable_event(struct perf_event *event)
 869 {
 870         struct hw_perf_event *hwc = &event->hw;
 871
 872         wrmsrl(hwc->config_base + hwc->idx, hwc->config);
 873 }
 874
 875 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
 876
 877 /*
 878  * Set the next IRQ period, based on the hwc->period_left value.
 879  * To be called with the event disabled in hw:
 880  */
 881 static int
 882 x86_perf_event_set_period(struct perf_event *event)
 883 {
 884         struct hw_perf_event *hwc = &event->hw;
 885         s64 left = atomic64_read(&hwc->period_left);
 886         s64 period = hwc->sample_period;
 887         int ret = 0, idx = hwc->idx;
 888
 889         if (idx == X86_PMC_IDX_FIXED_BTS)
 890                 return 0;
 891
 892         /*
 893          * If we are way outside a reasonable range then just skip forward:
 894          */
 895         if (unlikely(left <= -period)) {
 896                 left = period;
 897                 atomic64_set(&hwc->period_left, left);
 898                 hwc->last_period = period;
 899                 ret = 1;
 900         }
 901
 902         if (unlikely(left <= 0)) {
 903                 left += period;
 904                 atomic64_set(&hwc->period_left, left);
 905                 hwc->last_period = period;
 906                 ret = 1;
 907         }
 908         /*
 909          * Quirk: certain CPUs dont like it if just 1 hw_event is left:
 910          */
 911         if (unlikely(left < 2))
 912                 left = 2;
 913
 914         if (left > x86_pmu.max_period)
 915                 left = x86_pmu.max_period;
 916
 917         per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
 918
 919         /*
 920          * The hw event starts counting from this event offset,
 921          * mark it to be able to extra future deltas:
 922          */
 923         atomic64_set(&hwc->prev_count, (u64)-left);
 924
 925         wrmsrl(hwc->event_base + idx,
 926                         (u64)(-left) & x86_pmu.cntval_mask);
 927
 928         perf_event_update_userpage(event);
 929
 930         return ret;
 931 }
 932
 933 static void x86_pmu_enable_event(struct perf_event *event)
 934 {
 935         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 936         if (cpuc->enabled)
 937                 __x86_pmu_enable_event(&event->hw,
 938                                        ARCH_PERFMON_EVENTSEL_ENABLE);
 939 }
 940
 941 /*
 942  * activate a single event
 943  *
 944  * The event is added to the group of enabled events
 945  * but only if it can be scehduled with existing events.
 946  *
 947  * Called with PMU disabled. If successful and return value 1,
 948  * then guaranteed to call perf_enable() and hw_perf_enable()
 949  */
 950 static int x86_pmu_enable(struct perf_event *event)
 951 {
 952         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 953         struct hw_perf_event *hwc;
 954         int assign[X86_PMC_IDX_MAX];
 955         int n, n0, ret;
 956
 957         hwc = &event->hw;
 958
 959         n0 = cpuc->n_events;
 960         n = collect_events(cpuc, event, false);
 961         if (n < 0)
 962                 return n;
 963
 964         ret = x86_pmu.schedule_events(cpuc, n, assign);
 965         if (ret)
 966                 return ret;
 967         /*
 968          * copy new assignment, now we know it is possible
 969          * will be used by hw_perf_enable()
 970          */
 971         memcpy(cpuc->assign, assign, n*sizeof(int));
 972
 973         cpuc->n_events = n;
 974         cpuc->n_added += n - n0;
 975
 976         return 0;
 977 }
 978
 979 static int x86_pmu_start(struct perf_event *event)
 980 {
 981         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 982         int idx = event->hw.idx;
 983
 984         if (idx == -1)
 985                 return -EAGAIN;
 986
 987         x86_perf_event_set_period(event);
 988         cpuc->events[idx] = event;
 989         __set_bit(idx, cpuc->active_mask);
 990         x86_pmu.enable(event);
 991         perf_event_update_userpage(event);
 992
 993         return 0;
 994 }
 995
 996 static void x86_pmu_unthrottle(struct perf_event *event)
 997 {
 998         int ret = x86_pmu_start(event);
 999         WARN_ON_ONCE(ret);
1000 }
1001
1002 void perf_event_print_debug(void)
1003 {
1004         u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1005         u64 pebs;
1006         struct cpu_hw_events *cpuc;
1007         unsigned long flags;
1008         int cpu, idx;
1009
1010         if (!x86_pmu.num_counters)
1011                 return;
1012
1013         local_irq_save(flags);
1014
1015         cpu = smp_processor_id();
1016         cpuc = &per_cpu(cpu_hw_events, cpu);
1017
1018         if (x86_pmu.version >= 2) {
1019                 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1020                 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1021                 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1022                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1023                 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1024
1025                 pr_info("\n");
1026                 pr_info("CPU#%d: ctrl:       %016llx\n", cpu, ctrl);
1027                 pr_info("CPU#%d: status:     %016llx\n", cpu, status);
1028                 pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);
1029                 pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);
1030                 pr_info("CPU#%d: pebs:       %016llx\n", cpu, pebs);
1031         }
1032         pr_info("CPU#%d: active:     %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1033
1034         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1035                 rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl);
1036                 rdmsrl(x86_pmu.perfctr  + idx, pmc_count);
1037
1038                 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1039
1040                 pr_info("CPU#%d:   gen-PMC%d ctrl:  %016llx\n",
1041                         cpu, idx, pmc_ctrl);
1042                 pr_info("CPU#%d:   gen-PMC%d count: %016llx\n",
1043                         cpu, idx, pmc_count);
1044                 pr_info("CPU#%d:   gen-PMC%d left:  %016llx\n",
1045                         cpu, idx, prev_left);
1046         }
1047         for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1048                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1049
1050                 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1051                         cpu, idx, pmc_count);
1052         }
1053         local_irq_restore(flags);
1054 }
1055
1056 static void x86_pmu_stop(struct perf_event *event)
1057 {
1058         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1059         struct hw_perf_event *hwc = &event->hw;
1060         int idx = hwc->idx;
1061
1062         if (!__test_and_clear_bit(idx, cpuc->active_mask))
1063                 return;
1064
1065         x86_pmu.disable(event);
1066
1067         /*
1068          * Drain the remaining delta count out of a event
1069          * that we are disabling:
1070          */
1071         x86_perf_event_update(event);
1072
1073         cpuc->events[idx] = NULL;
1074 }
1075
1076 static void x86_pmu_disable(struct perf_event *event)
1077 {
1078         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1079         int i;
1080
1081         x86_pmu_stop(event);
1082
1083         for (i = 0; i < cpuc->n_events; i++) {
1084                 if (event == cpuc->event_list[i]) {
1085
1086                         if (x86_pmu.put_event_constraints)
1087                                 x86_pmu.put_event_constraints(cpuc, event);
1088
1089                         while (++i < cpuc->n_events)
1090                                 cpuc->event_list[i-1] = cpuc->event_list[i];
1091
1092                         --cpuc->n_events;
1093                         break;
1094                 }
1095         }
1096         perf_event_update_userpage(event);
1097 }
1098
1099 static int x86_pmu_handle_irq(struct pt_regs *regs)
1100 {
1101         struct perf_sample_data data;
1102         struct cpu_hw_events *cpuc;
1103         struct perf_event *event;
1104         struct hw_perf_event *hwc;
1105         int idx, handled = 0;
1106         u64 val;
1107
1108         perf_sample_data_init(&data, 0);
1109
1110         cpuc = &__get_cpu_var(cpu_hw_events);
1111
1112         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1113                 if (!test_bit(idx, cpuc->active_mask))
1114                         continue;
1115
1116                 event = cpuc->events[idx];
1117                 hwc = &event->hw;
1118
1119                 val = x86_perf_event_update(event);
1120                 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1121                         continue;
1122
1123                 /*
1124                  * event overflow
1125                  */
1126                 handled         = 1;
1127                 data.period     = event->hw.last_period;
1128
1129                 if (!x86_perf_event_set_period(event))
1130                         continue;
1131
1132                 if (perf_event_overflow(event, 1, &data, regs))
1133                         x86_pmu_stop(event);
1134         }
1135
1136         if (handled)
1137                 inc_irq_stat(apic_perf_irqs);
1138
1139         return handled;
1140 }
1141
1142 void smp_perf_pending_interrupt(struct pt_regs *regs)
1143 {
1144         irq_enter();
1145         ack_APIC_irq();
1146         inc_irq_stat(apic_pending_irqs);
1147         perf_event_do_pending();
1148         irq_exit();
1149 }
1150
1151 void set_perf_event_pending(void)
1152 {
1153 #ifdef CONFIG_X86_LOCAL_APIC
1154         if (!x86_pmu.apic || !x86_pmu_initialized())
1155                 return;
1156
1157         apic->send_IPI_self(LOCAL_PENDING_VECTOR);
1158 #endif
1159 }
1160
1161 void perf_events_lapic_init(void)
1162 {
1163         if (!x86_pmu.apic || !x86_pmu_initialized())
1164                 return;
1165
1166         /*
1167          * Always use NMI for PMU
1168          */
1169         apic_write(APIC_LVTPC, APIC_DM_NMI);
1170 }
1171
1172 static int __kprobes
1173 perf_event_nmi_handler(struct notifier_block *self,
1174                          unsigned long cmd, void *__args)
1175 {
1176         struct die_args *args = __args;
1177         struct pt_regs *regs;
1178
1179         if (!atomic_read(&active_events))
1180                 return NOTIFY_DONE;
1181
1182         switch (cmd) {
1183         case DIE_NMI:
1184         case DIE_NMI_IPI:
1185                 break;
1186
1187         default:
1188                 return NOTIFY_DONE;
1189         }
1190
1191         regs = args->regs;
1192
1193         apic_write(APIC_LVTPC, APIC_DM_NMI);
1194         /*
1195          * Can't rely on the handled return value to say it was our NMI, two
1196          * events could trigger 'simultaneously' raising two back-to-back NMIs.
1197          *
1198          * If the first NMI handles both, the latter will be empty and daze
1199          * the CPU.
1200          */
1201         x86_pmu.handle_irq(regs);
1202
1203         return NOTIFY_STOP;
1204 }
1205
1206 static __read_mostly struct notifier_block perf_event_nmi_notifier = {
1207         .notifier_call          = perf_event_nmi_handler,
1208         .next                   = NULL,
1209         .priority               = 1
1210 };
1211
1212 static struct event_constraint unconstrained;
1213 static struct event_constraint emptyconstraint;
1214
1215 static struct event_constraint *
1216 x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1217 {
1218         struct event_constraint *c;
1219
1220         if (x86_pmu.event_constraints) {
1221                 for_each_event_constraint(c, x86_pmu.event_constraints) {
1222                         if ((event->hw.config & c->cmask) == c->code)
1223                                 return c;
1224                 }
1225         }
1226
1227         return &unconstrained;
1228 }
1229
1230 static int x86_event_sched_in(struct perf_event *event,
1231                           struct perf_cpu_context *cpuctx)
1232 {
1233         int ret = 0;
1234
1235         event->state = PERF_EVENT_STATE_ACTIVE;
1236         event->oncpu = smp_processor_id();
1237         event->tstamp_running += event->ctx->time - event->tstamp_stopped;
1238
1239         if (!is_x86_event(event))
1240                 ret = event->pmu->enable(event);
1241
1242         if (!ret && !is_software_event(event))
1243                 cpuctx->active_oncpu++;
1244
1245         if (!ret && event->attr.exclusive)
1246                 cpuctx->exclusive = 1;
1247
1248         return ret;
1249 }
1250
1251 static void x86_event_sched_out(struct perf_event *event,
1252                             struct perf_cpu_context *cpuctx)
1253 {
1254         event->state = PERF_EVENT_STATE_INACTIVE;
1255         event->oncpu = -1;
1256
1257         if (!is_x86_event(event))
1258                 event->pmu->disable(event);
1259
1260         event->tstamp_running -= event->ctx->time - event->tstamp_stopped;
1261
1262         if (!is_software_event(event))
1263                 cpuctx->active_oncpu--;
1264
1265         if (event->attr.exclusive || !cpuctx->active_oncpu)
1266                 cpuctx->exclusive = 0;
1267 }
1268
1269 /*
1270  * Called to enable a whole group of events.
1271  * Returns 1 if the group was enabled, or -EAGAIN if it could not be.
1272  * Assumes the caller has disabled interrupts and has
1273  * frozen the PMU with hw_perf_save_disable.
1274  *
1275  * called with PMU disabled. If successful and return value 1,
1276  * then guaranteed to call perf_enable() and hw_perf_enable()
1277  */
1278 int hw_perf_group_sched_in(struct perf_event *leader,
1279                struct perf_cpu_context *cpuctx,
1280                struct perf_event_context *ctx)
1281 {
1282         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1283         struct perf_event *sub;
1284         int assign[X86_PMC_IDX_MAX];
1285         int n0, n1, ret;
1286
1287         if (!x86_pmu_initialized())
1288                 return 0;
1289
1290         /* n0 = total number of events */
1291         n0 = collect_events(cpuc, leader, true);
1292         if (n0 < 0)
1293                 return n0;
1294
1295         ret = x86_pmu.schedule_events(cpuc, n0, assign);
1296         if (ret)
1297                 return ret;
1298
1299         ret = x86_event_sched_in(leader, cpuctx);
1300         if (ret)
1301                 return ret;
1302
1303         n1 = 1;
1304         list_for_each_entry(sub, &leader->sibling_list, group_entry) {
1305                 if (sub->state > PERF_EVENT_STATE_OFF) {
1306                         ret = x86_event_sched_in(sub, cpuctx);
1307                         if (ret)
1308                                 goto undo;
1309                         ++n1;
1310                 }
1311         }
1312         /*
1313          * copy new assignment, now we know it is possible
1314          * will be used by hw_perf_enable()
1315          */
1316         memcpy(cpuc->assign, assign, n0*sizeof(int));
1317
1318         cpuc->n_events  = n0;
1319         cpuc->n_added  += n1;
1320         ctx->nr_active += n1;
1321
1322         /*
1323          * 1 means successful and events are active
1324          * This is not quite true because we defer
1325          * actual activation until hw_perf_enable() but
1326          * this way we* ensure caller won't try to enable
1327          * individual events
1328          */
1329         return 1;
1330 undo:
1331         x86_event_sched_out(leader, cpuctx);
1332         n0  = 1;
1333         list_for_each_entry(sub, &leader->sibling_list, group_entry) {
1334                 if (sub->state == PERF_EVENT_STATE_ACTIVE) {
1335                         x86_event_sched_out(sub, cpuctx);
1336                         if (++n0 == n1)
1337                                 break;
1338                 }
1339         }
1340         return ret;
1341 }
1342
1343 #include "perf_event_amd.c"
1344 #include "perf_event_p6.c"
1345 #include "perf_event_p4.c"
1346 #include "perf_event_intel_lbr.c"
1347 #include "perf_event_intel_ds.c"
1348 #include "perf_event_intel.c"
1349
1350 static int __cpuinit
1351 x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1352 {
1353         unsigned int cpu = (long)hcpu;
1354         int ret = NOTIFY_OK;
1355
1356         switch (action & ~CPU_TASKS_FROZEN) {
1357         case CPU_UP_PREPARE:
1358                 if (x86_pmu.cpu_prepare)
1359                         ret = x86_pmu.cpu_prepare(cpu);
1360                 break;
1361
1362         case CPU_STARTING:
1363                 if (x86_pmu.cpu_starting)
1364                         x86_pmu.cpu_starting(cpu);
1365                 break;
1366
1367         case CPU_DYING:
1368                 if (x86_pmu.cpu_dying)
1369                         x86_pmu.cpu_dying(cpu);
1370                 break;
1371
1372         case CPU_UP_CANCELED:
1373         case CPU_DEAD:
1374                 if (x86_pmu.cpu_dead)
1375                         x86_pmu.cpu_dead(cpu);
1376                 break;
1377
1378         default:
1379                 break;
1380         }
1381
1382         return ret;
1383 }
1384
1385 static void __init pmu_check_apic(void)
1386 {
1387         if (cpu_has_apic)
1388                 return;
1389
1390         x86_pmu.apic = 0;
1391         pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1392         pr_info("no hardware sampling interrupt available.\n");
1393 }
1394
1395 void __init init_hw_perf_events(void)
1396 {
1397         struct event_constraint *c;
1398         int err;
1399
1400         pr_info("Performance Events: ");
1401
1402         switch (boot_cpu_data.x86_vendor) {
1403         case X86_VENDOR_INTEL:
1404                 err = intel_pmu_init();
1405                 break;
1406         case X86_VENDOR_AMD:
1407                 err = amd_pmu_init();
1408                 break;
1409         default:
1410                 return;
1411         }
1412         if (err != 0) {
1413                 pr_cont("no PMU driver, software events only.\n");
1414                 return;
1415         }
1416
1417         pmu_check_apic();
1418
1419         pr_cont("%s PMU driver.\n", x86_pmu.name);
1420
1421         if (x86_pmu.quirks)
1422                 x86_pmu.quirks();
1423
1424         if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) {
1425                 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
1426                      x86_pmu.num_counters, X86_PMC_MAX_GENERIC);
1427                 x86_pmu.num_counters = X86_PMC_MAX_GENERIC;
1428         }
1429         x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1430         perf_max_events = x86_pmu.num_counters;
1431
1432         if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) {
1433                 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
1434                      x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED);
1435                 x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED;
1436         }
1437
1438         x86_pmu.intel_ctrl |=
1439                 ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED;
1440
1441         perf_events_lapic_init();
1442         register_die_notifier(&perf_event_nmi_notifier);
1443
1444         unconstrained = (struct event_constraint)
1445                 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1446                                    0, x86_pmu.num_counters);
1447
1448         if (x86_pmu.event_constraints) {
1449                 for_each_event_constraint(c, x86_pmu.event_constraints) {
1450                         if (c->cmask != X86_RAW_EVENT_MASK)
1451                                 continue;
1452
1453                         c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
1454                         c->weight += x86_pmu.num_counters;
1455                 }
1456         }
1457
1458         pr_info("... version:                %d\n",     x86_pmu.version);
1459         pr_info("... bit width:              %d\n",     x86_pmu.cntval_bits);
1460         pr_info("... generic registers:      %d\n",     x86_pmu.num_counters);
1461         pr_info("... value mask:             %016Lx\n", x86_pmu.cntval_mask);
1462         pr_info("... max period:             %016Lx\n", x86_pmu.max_period);
1463         pr_info("... fixed-purpose events:   %d\n",     x86_pmu.num_counters_fixed);
1464         pr_info("... event mask:             %016Lx\n", x86_pmu.intel_ctrl);
1465
1466         perf_cpu_notifier(x86_pmu_notifier);
1467 }
1468
1469 static inline void x86_pmu_read(struct perf_event *event)
1470 {
1471         x86_perf_event_update(event);
1472 }
1473
1474 static const struct pmu pmu = {
1475         .enable         = x86_pmu_enable,
1476         .disable        = x86_pmu_disable,
1477         .start          = x86_pmu_start,
1478         .stop           = x86_pmu_stop,
1479         .read           = x86_pmu_read,
1480         .unthrottle     = x86_pmu_unthrottle,
1481 };
1482
1483 /*
1484  * validate that we can schedule this event
1485  */
1486 static int validate_event(struct perf_event *event)
1487 {
1488         struct cpu_hw_events *fake_cpuc;
1489         struct event_constraint *c;
1490         int ret = 0;
1491
1492         fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1493         if (!fake_cpuc)
1494                 return -ENOMEM;
1495
1496         c = x86_pmu.get_event_constraints(fake_cpuc, event);
1497
1498         if (!c || !c->weight)
1499                 ret = -ENOSPC;
1500
1501         if (x86_pmu.put_event_constraints)
1502                 x86_pmu.put_event_constraints(fake_cpuc, event);
1503
1504         kfree(fake_cpuc);
1505
1506         return ret;
1507 }
1508
1509 /*
1510  * validate a single event group
1511  *
1512  * validation include:
1513  *      - check events are compatible which each other
1514  *      - events do not compete for the same counter
1515  *      - number of events <= number of counters
1516  *
1517  * validation ensures the group can be loaded onto the
1518  * PMU if it was the only group available.
1519  */
1520 static int validate_group(struct perf_event *event)
1521 {
1522         struct perf_event *leader = event->group_leader;
1523         struct cpu_hw_events *fake_cpuc;
1524         int ret, n;
1525
1526         ret = -ENOMEM;
1527         fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1528         if (!fake_cpuc)
1529                 goto out;
1530
1531         /*
1532          * the event is not yet connected with its
1533          * siblings therefore we must first collect
1534          * existing siblings, then add the new event
1535          * before we can simulate the scheduling
1536          */
1537         ret = -ENOSPC;
1538         n = collect_events(fake_cpuc, leader, true);
1539         if (n < 0)
1540                 goto out_free;
1541
1542         fake_cpuc->n_events = n;
1543         n = collect_events(fake_cpuc, event, false);
1544         if (n < 0)
1545                 goto out_free;
1546
1547         fake_cpuc->n_events = n;
1548
1549         ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
1550
1551 out_free:
1552         kfree(fake_cpuc);
1553 out:
1554         return ret;
1555 }
1556
1557 const struct pmu *hw_perf_event_init(struct perf_event *event)
1558 {
1559         const struct pmu *tmp;
1560         int err;
1561
1562         err = __hw_perf_event_init(event);
1563         if (!err) {
1564                 /*
1565                  * we temporarily connect event to its pmu
1566                  * such that validate_group() can classify
1567                  * it as an x86 event using is_x86_event()
1568                  */
1569                 tmp = event->pmu;
1570                 event->pmu = &pmu;
1571
1572                 if (event->group_leader != event)
1573                         err = validate_group(event);
1574                 else
1575                         err = validate_event(event);
1576
1577                 event->pmu = tmp;
1578         }
1579         if (err) {
1580                 if (event->destroy)
1581                         event->destroy(event);
1582                 return ERR_PTR(err);
1583         }
1584
1585         return &pmu;
1586 }
1587
1588 /*
1589  * callchain support
1590  */
1591
1592 static inline
1593 void callchain_store(struct perf_callchain_entry *entry, u64 ip)
1594 {
1595         if (entry->nr < PERF_MAX_STACK_DEPTH)
1596                 entry->ip[entry->nr++] = ip;
1597 }
1598
1599 static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_irq_entry);
1600 static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_nmi_entry);
1601
1602
1603 static void
1604 backtrace_warning_symbol(void *data, char *msg, unsigned long symbol)
1605 {
1606         /* Ignore warnings */
1607 }
1608
1609 static void backtrace_warning(void *data, char *msg)
1610 {
1611         /* Ignore warnings */
1612 }
1613
1614 static int backtrace_stack(void *data, char *name)
1615 {
1616         return 0;
1617 }
1618
1619 static void backtrace_address(void *data, unsigned long addr, int reliable)
1620 {
1621         struct perf_callchain_entry *entry = data;
1622
1623         callchain_store(entry, addr);
1624 }
1625
1626 static const struct stacktrace_ops backtrace_ops = {
1627         .warning                = backtrace_warning,
1628         .warning_symbol         = backtrace_warning_symbol,
1629         .stack                  = backtrace_stack,
1630         .address                = backtrace_address,
1631         .walk_stack             = print_context_stack_bp,
1632 };
1633
1634 #include "../dumpstack.h"
1635
1636 static void
1637 perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry)
1638 {
1639         callchain_store(entry, PERF_CONTEXT_KERNEL);
1640         callchain_store(entry, regs->ip);
1641
1642         dump_trace(NULL, regs, NULL, regs->bp, &backtrace_ops, entry);
1643 }
1644
1645 #ifdef CONFIG_COMPAT
1646 static inline int
1647 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1648 {
1649         /* 32-bit process in 64-bit kernel. */
1650         struct stack_frame_ia32 frame;
1651         const void __user *fp;
1652
1653         if (!test_thread_flag(TIF_IA32))
1654                 return 0;
1655
1656         fp = compat_ptr(regs->bp);
1657         while (entry->nr < PERF_MAX_STACK_DEPTH) {
1658                 unsigned long bytes;
1659                 frame.next_frame     = 0;
1660                 frame.return_address = 0;
1661
1662                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1663                 if (bytes != sizeof(frame))
1664                         break;
1665
1666                 if (fp < compat_ptr(regs->sp))
1667                         break;
1668
1669                 callchain_store(entry, frame.return_address);
1670                 fp = compat_ptr(frame.next_frame);
1671         }
1672         return 1;
1673 }
1674 #else
1675 static inline int
1676 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1677 {
1678     return 0;
1679 }
1680 #endif
1681
1682 static void
1683 perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry)
1684 {
1685         struct stack_frame frame;
1686         const void __user *fp;
1687
1688         if (!user_mode(regs))
1689                 regs = task_pt_regs(current);
1690
1691         fp = (void __user *)regs->bp;
1692
1693         callchain_store(entry, PERF_CONTEXT_USER);
1694         callchain_store(entry, regs->ip);
1695
1696         if (perf_callchain_user32(regs, entry))
1697                 return;
1698
1699         while (entry->nr < PERF_MAX_STACK_DEPTH) {
1700                 unsigned long bytes;
1701                 frame.next_frame             = NULL;
1702                 frame.return_address = 0;
1703
1704                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1705                 if (bytes != sizeof(frame))
1706                         break;
1707
1708                 if ((unsigned long)fp < regs->sp)
1709                         break;
1710
1711                 callchain_store(entry, frame.return_address);
1712                 fp = frame.next_frame;
1713         }
1714 }
1715
1716 static void
1717 perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry)
1718 {
1719         int is_user;
1720
1721         if (!regs)
1722                 return;
1723
1724         is_user = user_mode(regs);
1725
1726         if (is_user && current->state != TASK_RUNNING)
1727                 return;
1728
1729         if (!is_user)
1730                 perf_callchain_kernel(regs, entry);
1731
1732         if (current->mm)
1733                 perf_callchain_user(regs, entry);
1734 }
1735
1736 struct perf_callchain_entry *perf_callchain(struct pt_regs *regs)
1737 {
1738         struct perf_callchain_entry *entry;
1739
1740         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1741                 /* TODO: We don't support guest os callchain now */
1742                 return NULL;
1743         }
1744
1745         if (in_nmi())
1746                 entry = &__get_cpu_var(pmc_nmi_entry);
1747         else
1748                 entry = &__get_cpu_var(pmc_irq_entry);
1749
1750         entry->nr = 0;
1751
1752         perf_do_callchain(regs, entry);
1753
1754         return entry;
1755 }
1756
1757 void perf_arch_fetch_caller_regs(struct pt_regs *regs, unsigned long ip, int skip)
1758 {
1759         regs->ip = ip;
1760         /*
1761          * perf_arch_fetch_caller_regs adds another call, we need to increment
1762          * the skip level
1763          */
1764         regs->bp = rewind_frame_pointer(skip + 1);
1765         regs->cs = __KERNEL_CS;
1766         local_save_flags(regs->flags);
1767 }
1768
1769 unsigned long perf_instruction_pointer(struct pt_regs *regs)
1770 {
1771         unsigned long ip;
1772
1773         if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
1774                 ip = perf_guest_cbs->get_guest_ip();
1775         else
1776                 ip = instruction_pointer(regs);
1777
1778         return ip;
1779 }
1780
1781 unsigned long perf_misc_flags(struct pt_regs *regs)
1782 {
1783         int misc = 0;
1784
1785         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1786                 if (perf_guest_cbs->is_user_mode())
1787                         misc |= PERF_RECORD_MISC_GUEST_USER;
1788                 else
1789                         misc |= PERF_RECORD_MISC_GUEST_KERNEL;
1790         } else {
1791                 if (user_mode(regs))
1792                         misc |= PERF_RECORD_MISC_USER;
1793                 else
1794                         misc |= PERF_RECORD_MISC_KERNEL;
1795         }
1796
1797         if (regs->flags & PERF_EFLAGS_EXACT)
1798                 misc |= PERF_RECORD_MISC_EXACT_IP;
1799
1800         return misc;
1801 }