2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
10 #include <linux/thread_info.h>
11 #include <linux/capability.h>
12 #include <linux/miscdevice.h>
13 #include <linux/interrupt.h>
14 #include <linux/ratelimit.h>
15 #include <linux/kallsyms.h>
16 #include <linux/rcupdate.h>
17 #include <linux/kobject.h>
18 #include <linux/uaccess.h>
19 #include <linux/kdebug.h>
20 #include <linux/kernel.h>
21 #include <linux/percpu.h>
22 #include <linux/string.h>
23 #include <linux/sysdev.h>
24 #include <linux/delay.h>
25 #include <linux/ctype.h>
26 #include <linux/sched.h>
27 #include <linux/sysfs.h>
28 #include <linux/types.h>
29 #include <linux/init.h>
30 #include <linux/kmod.h>
31 #include <linux/poll.h>
32 #include <linux/nmi.h>
33 #include <linux/cpu.h>
34 #include <linux/smp.h>
37 #include <linux/debugfs.h>
39 #include <asm/processor.h>
40 #include <asm/hw_irq.h>
47 #include "mce-internal.h"
49 int mce_disabled __read_mostly;
51 #define MISC_MCELOG_MINOR 227
53 #define SPINUNIT 100 /* 100ns */
57 DEFINE_PER_CPU(unsigned, mce_exception_count);
61 * 0: always panic on uncorrected errors, log corrected errors
62 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
63 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
64 * 3: never panic or SIGBUS, log all errors (for testing only)
66 static int tolerant __read_mostly = 1;
67 static int banks __read_mostly;
68 static int rip_msr __read_mostly;
69 static int mce_bootlog __read_mostly = -1;
70 static int monarch_timeout __read_mostly = -1;
71 static int mce_panic_timeout __read_mostly;
72 static int mce_dont_log_ce __read_mostly;
73 int mce_cmci_disabled __read_mostly;
74 int mce_ignore_ce __read_mostly;
75 int mce_ser __read_mostly;
77 struct mce_bank *mce_banks __read_mostly;
79 /* User mode helper program triggered by machine check event */
80 static unsigned long mce_need_notify;
81 static char mce_helper[128];
82 static char *mce_helper_argv[2] = { mce_helper, NULL };
84 static DECLARE_WAIT_QUEUE_HEAD(mce_wait);
85 static DEFINE_PER_CPU(struct mce, mces_seen);
86 static int cpu_missing;
89 /* MCA banks polled by the period polling timer for corrected events */
90 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
91 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
94 static DEFINE_PER_CPU(struct work_struct, mce_work);
96 /* Do initial initialization of a struct mce */
97 void mce_setup(struct mce *m)
99 memset(m, 0, sizeof(struct mce));
100 m->cpu = m->extcpu = smp_processor_id();
102 /* We hope get_seconds stays lockless */
103 m->time = get_seconds();
104 m->cpuvendor = boot_cpu_data.x86_vendor;
105 m->cpuid = cpuid_eax(1);
107 m->socketid = cpu_data(m->extcpu).phys_proc_id;
109 m->apicid = cpu_data(m->extcpu).initial_apicid;
110 rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap);
113 DEFINE_PER_CPU(struct mce, injectm);
114 EXPORT_PER_CPU_SYMBOL_GPL(injectm);
117 * Lockless MCE logging infrastructure.
118 * This avoids deadlocks on printk locks without having to break locks. Also
119 * separate MCEs from kernel messages to avoid bogus bug reports.
122 static struct mce_log mcelog = {
123 .signature = MCE_LOG_SIGNATURE,
125 .recordlen = sizeof(struct mce),
128 void mce_log(struct mce *mce)
130 unsigned next, entry;
135 entry = rcu_dereference(mcelog.next);
138 * When the buffer fills up discard new entries.
139 * Assume that the earlier errors are the more
142 if (entry >= MCE_LOG_LEN) {
143 set_bit(MCE_OVERFLOW,
144 (unsigned long *)&mcelog.flags);
147 /* Old left over entry. Skip: */
148 if (mcelog.entry[entry].finished) {
156 if (cmpxchg(&mcelog.next, entry, next) == entry)
159 memcpy(mcelog.entry + entry, mce, sizeof(struct mce));
161 mcelog.entry[entry].finished = 1;
165 set_bit(0, &mce_need_notify);
168 static void print_mce(struct mce *m)
171 "CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n",
172 m->extcpu, m->mcgstatus, m->bank, m->status);
174 printk(KERN_EMERG "RIP%s %02x:<%016Lx> ",
175 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
177 if (m->cs == __KERNEL_CS)
178 print_symbol("{%s}", m->ip);
181 printk(KERN_EMERG "TSC %llx ", m->tsc);
183 printk("ADDR %llx ", m->addr);
185 printk("MISC %llx ", m->misc);
187 printk(KERN_EMERG "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
188 m->cpuvendor, m->cpuid, m->time, m->socketid,
192 static void print_mce_head(void)
194 printk(KERN_EMERG "\n" KERN_EMERG "HARDWARE ERROR\n");
197 static void print_mce_tail(void)
199 printk(KERN_EMERG "This is not a software problem!\n"
200 KERN_EMERG "Run through mcelog --ascii to decode and contact your hardware vendor\n");
203 #define PANIC_TIMEOUT 5 /* 5 seconds */
205 static atomic_t mce_paniced;
207 static int fake_panic;
208 static atomic_t mce_fake_paniced;
210 /* Panic in progress. Enable interrupts and wait for final IPI */
211 static void wait_for_panic(void)
213 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
216 while (timeout-- > 0)
218 if (panic_timeout == 0)
219 panic_timeout = mce_panic_timeout;
220 panic("Panicing machine check CPU died");
223 static void mce_panic(char *msg, struct mce *final, char *exp)
229 * Make sure only one CPU runs in machine check panic
231 if (atomic_inc_return(&mce_paniced) > 1)
238 /* Don't log too much for fake panic */
239 if (atomic_inc_return(&mce_fake_paniced) > 1)
243 /* First print corrected ones that are still unlogged */
244 for (i = 0; i < MCE_LOG_LEN; i++) {
245 struct mce *m = &mcelog.entry[i];
246 if (!(m->status & MCI_STATUS_VAL))
248 if (!(m->status & MCI_STATUS_UC))
251 /* Now print uncorrected but with the final one last */
252 for (i = 0; i < MCE_LOG_LEN; i++) {
253 struct mce *m = &mcelog.entry[i];
254 if (!(m->status & MCI_STATUS_VAL))
256 if (!(m->status & MCI_STATUS_UC))
258 if (!final || memcmp(m, final, sizeof(struct mce)))
264 printk(KERN_EMERG "Some CPUs didn't answer in synchronization\n");
267 printk(KERN_EMERG "Machine check: %s\n", exp);
269 if (panic_timeout == 0)
270 panic_timeout = mce_panic_timeout;
273 printk(KERN_EMERG "Fake kernel panic: %s\n", msg);
276 /* Support code for software error injection */
278 static int msr_to_offset(u32 msr)
280 unsigned bank = __get_cpu_var(injectm.bank);
282 return offsetof(struct mce, ip);
283 if (msr == MSR_IA32_MCx_STATUS(bank))
284 return offsetof(struct mce, status);
285 if (msr == MSR_IA32_MCx_ADDR(bank))
286 return offsetof(struct mce, addr);
287 if (msr == MSR_IA32_MCx_MISC(bank))
288 return offsetof(struct mce, misc);
289 if (msr == MSR_IA32_MCG_STATUS)
290 return offsetof(struct mce, mcgstatus);
294 /* MSR access wrappers used for error injection */
295 static u64 mce_rdmsrl(u32 msr)
298 if (__get_cpu_var(injectm).finished) {
299 int offset = msr_to_offset(msr);
302 return *(u64 *)((char *)&__get_cpu_var(injectm) + offset);
308 static void mce_wrmsrl(u32 msr, u64 v)
310 if (__get_cpu_var(injectm).finished) {
311 int offset = msr_to_offset(msr);
313 *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v;
320 * Simple lockless ring to communicate PFNs from the exception handler with the
321 * process context work function. This is vastly simplified because there's
322 * only a single reader and a single writer.
324 #define MCE_RING_SIZE 16 /* we use one entry less */
327 unsigned short start;
329 unsigned long ring[MCE_RING_SIZE];
331 static DEFINE_PER_CPU(struct mce_ring, mce_ring);
333 /* Runs with CPU affinity in workqueue */
334 static int mce_ring_empty(void)
336 struct mce_ring *r = &__get_cpu_var(mce_ring);
338 return r->start == r->end;
341 static int mce_ring_get(unsigned long *pfn)
348 r = &__get_cpu_var(mce_ring);
349 if (r->start == r->end)
351 *pfn = r->ring[r->start];
352 r->start = (r->start + 1) % MCE_RING_SIZE;
359 /* Always runs in MCE context with preempt off */
360 static int mce_ring_add(unsigned long pfn)
362 struct mce_ring *r = &__get_cpu_var(mce_ring);
365 next = (r->end + 1) % MCE_RING_SIZE;
366 if (next == r->start)
368 r->ring[r->end] = pfn;
374 int mce_available(struct cpuinfo_x86 *c)
378 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
381 static void mce_schedule_work(void)
383 if (!mce_ring_empty()) {
384 struct work_struct *work = &__get_cpu_var(mce_work);
385 if (!work_pending(work))
391 * Get the address of the instruction at the time of the machine check
394 static inline void mce_get_rip(struct mce *m, struct pt_regs *regs)
397 if (regs && (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV))) {
405 m->ip = mce_rdmsrl(rip_msr);
408 #ifdef CONFIG_X86_LOCAL_APIC
410 * Called after interrupts have been reenabled again
411 * when a MCE happened during an interrupts off region
414 asmlinkage void smp_mce_self_interrupt(struct pt_regs *regs)
425 static void mce_report_event(struct pt_regs *regs)
427 if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) {
430 * Triggering the work queue here is just an insurance
431 * policy in case the syscall exit notify handler
432 * doesn't run soon enough or ends up running on the
433 * wrong CPU (can happen when audit sleeps)
439 #ifdef CONFIG_X86_LOCAL_APIC
441 * Without APIC do not notify. The event will be picked
448 * When interrupts are disabled we cannot use
449 * kernel services safely. Trigger an self interrupt
450 * through the APIC to instead do the notification
451 * after interrupts are reenabled again.
453 apic->send_IPI_self(MCE_SELF_VECTOR);
456 * Wait for idle afterwards again so that we don't leave the
457 * APIC in a non idle state because the normal APIC writes
460 apic_wait_icr_idle();
464 DEFINE_PER_CPU(unsigned, mce_poll_count);
467 * Poll for corrected events or events that happened before reset.
468 * Those are just logged through /dev/mcelog.
470 * This is executed in standard interrupt context.
472 * Note: spec recommends to panic for fatal unsignalled
473 * errors here. However this would be quite problematic --
474 * we would need to reimplement the Monarch handling and
475 * it would mess up the exclusion between exception handler
476 * and poll hander -- * so we skip this for now.
477 * These cases should not happen anyways, or only when the CPU
478 * is already totally * confused. In this case it's likely it will
479 * not fully execute the machine check handler either.
481 void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
486 __get_cpu_var(mce_poll_count)++;
490 m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
491 for (i = 0; i < banks; i++) {
492 if (!mce_banks[i].ctl || !test_bit(i, *b))
501 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
502 if (!(m.status & MCI_STATUS_VAL))
506 * Uncorrected or signalled events are handled by the exception
507 * handler when it is enabled, so don't process those here.
509 * TBD do the same check for MCI_STATUS_EN here?
511 if (!(flags & MCP_UC) &&
512 (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)))
515 if (m.status & MCI_STATUS_MISCV)
516 m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
517 if (m.status & MCI_STATUS_ADDRV)
518 m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
520 if (!(flags & MCP_TIMESTAMP))
523 * Don't get the IP here because it's unlikely to
524 * have anything to do with the actual error location.
526 if (!(flags & MCP_DONTLOG) && !mce_dont_log_ce) {
528 add_taint(TAINT_MACHINE_CHECK);
532 * Clear state for this bank.
534 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
538 * Don't clear MCG_STATUS here because it's only defined for
544 EXPORT_SYMBOL_GPL(machine_check_poll);
547 * Do a quick check if any of the events requires a panic.
548 * This decides if we keep the events around or clear them.
550 static int mce_no_way_out(struct mce *m, char **msg)
554 for (i = 0; i < banks; i++) {
555 m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
556 if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY)
563 * Variable to establish order between CPUs while scanning.
564 * Each CPU spins initially until executing is equal its number.
566 static atomic_t mce_executing;
569 * Defines order of CPUs on entry. First CPU becomes Monarch.
571 static atomic_t mce_callin;
574 * Check if a timeout waiting for other CPUs happened.
576 static int mce_timed_out(u64 *t)
579 * The others already did panic for some reason.
580 * Bail out like in a timeout.
581 * rmb() to tell the compiler that system_state
582 * might have been modified by someone else.
585 if (atomic_read(&mce_paniced))
587 if (!monarch_timeout)
589 if ((s64)*t < SPINUNIT) {
590 /* CHECKME: Make panic default for 1 too? */
592 mce_panic("Timeout synchronizing machine check over CPUs",
599 touch_nmi_watchdog();
604 * The Monarch's reign. The Monarch is the CPU who entered
605 * the machine check handler first. It waits for the others to
606 * raise the exception too and then grades them. When any
607 * error is fatal panic. Only then let the others continue.
609 * The other CPUs entering the MCE handler will be controlled by the
610 * Monarch. They are called Subjects.
612 * This way we prevent any potential data corruption in a unrecoverable case
613 * and also makes sure always all CPU's errors are examined.
615 * Also this detects the case of an machine check event coming from outer
616 * space (not detected by any CPUs) In this case some external agent wants
617 * us to shut down, so panic too.
619 * The other CPUs might still decide to panic if the handler happens
620 * in a unrecoverable place, but in this case the system is in a semi-stable
621 * state and won't corrupt anything by itself. It's ok to let the others
622 * continue for a bit first.
624 * All the spin loops have timeouts; when a timeout happens a CPU
625 * typically elects itself to be Monarch.
627 static void mce_reign(void)
630 struct mce *m = NULL;
631 int global_worst = 0;
636 * This CPU is the Monarch and the other CPUs have run
637 * through their handlers.
638 * Grade the severity of the errors of all the CPUs.
640 for_each_possible_cpu(cpu) {
641 int severity = mce_severity(&per_cpu(mces_seen, cpu), tolerant,
643 if (severity > global_worst) {
645 global_worst = severity;
646 m = &per_cpu(mces_seen, cpu);
651 * Cannot recover? Panic here then.
652 * This dumps all the mces in the log buffer and stops the
655 if (m && global_worst >= MCE_PANIC_SEVERITY && tolerant < 3)
656 mce_panic("Fatal Machine check", m, msg);
659 * For UC somewhere we let the CPU who detects it handle it.
660 * Also must let continue the others, otherwise the handling
661 * CPU could deadlock on a lock.
665 * No machine check event found. Must be some external
666 * source or one CPU is hung. Panic.
668 if (!m && tolerant < 3)
669 mce_panic("Machine check from unknown source", NULL, NULL);
672 * Now clear all the mces_seen so that they don't reappear on
675 for_each_possible_cpu(cpu)
676 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
679 static atomic_t global_nwo;
682 * Start of Monarch synchronization. This waits until all CPUs have
683 * entered the exception handler and then determines if any of them
684 * saw a fatal event that requires panic. Then it executes them
685 * in the entry order.
686 * TBD double check parallel CPU hotunplug
688 static int mce_start(int *no_way_out)
691 int cpus = num_online_cpus();
692 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
697 atomic_add(*no_way_out, &global_nwo);
699 * global_nwo should be updated before mce_callin
702 order = atomic_inc_return(&mce_callin);
707 while (atomic_read(&mce_callin) != cpus) {
708 if (mce_timed_out(&timeout)) {
709 atomic_set(&global_nwo, 0);
716 * mce_callin should be read before global_nwo
722 * Monarch: Starts executing now, the others wait.
724 atomic_set(&mce_executing, 1);
727 * Subject: Now start the scanning loop one by one in
728 * the original callin order.
729 * This way when there are any shared banks it will be
730 * only seen by one CPU before cleared, avoiding duplicates.
732 while (atomic_read(&mce_executing) < order) {
733 if (mce_timed_out(&timeout)) {
734 atomic_set(&global_nwo, 0);
742 * Cache the global no_way_out state.
744 *no_way_out = atomic_read(&global_nwo);
750 * Synchronize between CPUs after main scanning loop.
751 * This invokes the bulk of the Monarch processing.
753 static int mce_end(int order)
756 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
764 * Allow others to run.
766 atomic_inc(&mce_executing);
769 /* CHECKME: Can this race with a parallel hotplug? */
770 int cpus = num_online_cpus();
773 * Monarch: Wait for everyone to go through their scanning
776 while (atomic_read(&mce_executing) <= cpus) {
777 if (mce_timed_out(&timeout))
787 * Subject: Wait for Monarch to finish.
789 while (atomic_read(&mce_executing) != 0) {
790 if (mce_timed_out(&timeout))
796 * Don't reset anything. That's done by the Monarch.
802 * Reset all global state.
805 atomic_set(&global_nwo, 0);
806 atomic_set(&mce_callin, 0);
810 * Let others run again.
812 atomic_set(&mce_executing, 0);
817 * Check if the address reported by the CPU is in a format we can parse.
818 * It would be possible to add code for most other cases, but all would
819 * be somewhat complicated (e.g. segment offset would require an instruction
820 * parser). So only support physical addresses upto page granuality for now.
822 static int mce_usable_address(struct mce *m)
824 if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV))
826 if ((m->misc & 0x3f) > PAGE_SHIFT)
828 if (((m->misc >> 6) & 7) != MCM_ADDR_PHYS)
833 static void mce_clear_state(unsigned long *toclear)
837 for (i = 0; i < banks; i++) {
838 if (test_bit(i, toclear))
839 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
844 * The actual machine check handler. This only handles real
845 * exceptions when something got corrupted coming in through int 18.
847 * This is executed in NMI context not subject to normal locking rules. This
848 * implies that most kernel services cannot be safely used. Don't even
849 * think about putting a printk in there!
851 * On Intel systems this is entered on all CPUs in parallel through
852 * MCE broadcast. However some CPUs might be broken beyond repair,
853 * so be always careful when synchronizing with others.
855 void do_machine_check(struct pt_regs *regs, long error_code)
857 struct mce m, *final;
862 * Establish sequential order between the CPUs entering the machine
867 * If no_way_out gets set, there is no safe way to recover from this
868 * MCE. If tolerant is cranked up, we'll try anyway.
872 * If kill_it gets set, there might be a way to recover from this
876 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
877 char *msg = "Unknown";
879 atomic_inc(&mce_entry);
881 __get_cpu_var(mce_exception_count)++;
883 if (notify_die(DIE_NMI, "machine check", regs, error_code,
884 18, SIGKILL) == NOTIFY_STOP)
891 m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
892 no_way_out = mce_no_way_out(&m, &msg);
894 final = &__get_cpu_var(mces_seen);
900 * When no restart IP must always kill or panic.
902 if (!(m.mcgstatus & MCG_STATUS_RIPV))
906 * Go through all the banks in exclusion of the other CPUs.
907 * This way we don't report duplicated events on shared banks
908 * because the first one to see it will clear it.
910 order = mce_start(&no_way_out);
911 for (i = 0; i < banks; i++) {
912 __clear_bit(i, toclear);
913 if (!mce_banks[i].ctl)
920 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
921 if ((m.status & MCI_STATUS_VAL) == 0)
925 * Non uncorrected or non signaled errors are handled by
926 * machine_check_poll. Leave them alone, unless this panics.
928 if (!(m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
933 * Set taint even when machine check was not enabled.
935 add_taint(TAINT_MACHINE_CHECK);
937 severity = mce_severity(&m, tolerant, NULL);
940 * When machine check was for corrected handler don't touch,
941 * unless we're panicing.
943 if (severity == MCE_KEEP_SEVERITY && !no_way_out)
945 __set_bit(i, toclear);
946 if (severity == MCE_NO_SEVERITY) {
948 * Machine check event was not enabled. Clear, but
955 * Kill on action required.
957 if (severity == MCE_AR_SEVERITY)
960 if (m.status & MCI_STATUS_MISCV)
961 m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
962 if (m.status & MCI_STATUS_ADDRV)
963 m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
966 * Action optional error. Queue address for later processing.
967 * When the ring overflows we just ignore the AO error.
968 * RED-PEN add some logging mechanism when
969 * usable_address or mce_add_ring fails.
970 * RED-PEN don't ignore overflow for tolerant == 0
972 if (severity == MCE_AO_SEVERITY && mce_usable_address(&m))
973 mce_ring_add(m.addr >> PAGE_SHIFT);
975 mce_get_rip(&m, regs);
978 if (severity > worst) {
985 mce_clear_state(toclear);
988 * Do most of the synchronization with other CPUs.
989 * When there's any problem use only local no_way_out state.
991 if (mce_end(order) < 0)
992 no_way_out = worst >= MCE_PANIC_SEVERITY;
995 * If we have decided that we just CAN'T continue, and the user
996 * has not set tolerant to an insane level, give up and die.
998 * This is mainly used in the case when the system doesn't
999 * support MCE broadcasting or it has been disabled.
1001 if (no_way_out && tolerant < 3)
1002 mce_panic("Fatal machine check on current CPU", final, msg);
1005 * If the error seems to be unrecoverable, something should be
1006 * done. Try to kill as little as possible. If we can kill just
1007 * one task, do that. If the user has set the tolerance very
1008 * high, don't try to do anything at all.
1011 if (kill_it && tolerant < 3)
1012 force_sig(SIGBUS, current);
1014 /* notify userspace ASAP */
1015 set_thread_flag(TIF_MCE_NOTIFY);
1018 mce_report_event(regs);
1019 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1021 atomic_dec(&mce_entry);
1024 EXPORT_SYMBOL_GPL(do_machine_check);
1026 /* dummy to break dependency. actual code is in mm/memory-failure.c */
1027 void __attribute__((weak)) memory_failure(unsigned long pfn, int vector)
1029 printk(KERN_ERR "Action optional memory failure at %lx ignored\n", pfn);
1033 * Called after mce notification in process context. This code
1034 * is allowed to sleep. Call the high level VM handler to process
1035 * any corrupted pages.
1036 * Assume that the work queue code only calls this one at a time
1038 * Note we don't disable preemption, so this code might run on the wrong
1039 * CPU. In this case the event is picked up by the scheduled work queue.
1040 * This is merely a fast path to expedite processing in some common
1043 void mce_notify_process(void)
1047 while (mce_ring_get(&pfn))
1048 memory_failure(pfn, MCE_VECTOR);
1051 static void mce_process_work(struct work_struct *dummy)
1053 mce_notify_process();
1056 #ifdef CONFIG_X86_MCE_INTEL
1058 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
1059 * @cpu: The CPU on which the event occurred.
1060 * @status: Event status information
1062 * This function should be called by the thermal interrupt after the
1063 * event has been processed and the decision was made to log the event
1066 * The status parameter will be saved to the 'status' field of 'struct mce'
1067 * and historically has been the register value of the
1068 * MSR_IA32_THERMAL_STATUS (Intel) msr.
1070 void mce_log_therm_throt_event(__u64 status)
1075 m.bank = MCE_THERMAL_BANK;
1079 #endif /* CONFIG_X86_MCE_INTEL */
1082 * Periodic polling timer for "silent" machine check errors. If the
1083 * poller finds an MCE, poll 2x faster. When the poller finds no more
1084 * errors, poll 2x slower (up to check_interval seconds).
1086 static int check_interval = 5 * 60; /* 5 minutes */
1088 static DEFINE_PER_CPU(int, next_interval); /* in jiffies */
1089 static DEFINE_PER_CPU(struct timer_list, mce_timer);
1091 static void mcheck_timer(unsigned long data)
1093 struct timer_list *t = &per_cpu(mce_timer, data);
1096 WARN_ON(smp_processor_id() != data);
1098 if (mce_available(¤t_cpu_data)) {
1099 machine_check_poll(MCP_TIMESTAMP,
1100 &__get_cpu_var(mce_poll_banks));
1104 * Alert userspace if needed. If we logged an MCE, reduce the
1105 * polling interval, otherwise increase the polling interval.
1107 n = &__get_cpu_var(next_interval);
1108 if (mce_notify_irq())
1109 *n = max(*n/2, HZ/100);
1111 *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ));
1113 t->expires = jiffies + *n;
1117 static void mce_do_trigger(struct work_struct *work)
1119 call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT);
1122 static DECLARE_WORK(mce_trigger_work, mce_do_trigger);
1125 * Notify the user(s) about new machine check events.
1126 * Can be called from interrupt context, but not from machine check/NMI
1129 int mce_notify_irq(void)
1131 /* Not more than two messages every minute */
1132 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1134 clear_thread_flag(TIF_MCE_NOTIFY);
1136 if (test_and_clear_bit(0, &mce_need_notify)) {
1137 wake_up_interruptible(&mce_wait);
1140 * There is no risk of missing notifications because
1141 * work_pending is always cleared before the function is
1144 if (mce_helper[0] && !work_pending(&mce_trigger_work))
1145 schedule_work(&mce_trigger_work);
1147 if (__ratelimit(&ratelimit))
1148 printk(KERN_INFO "Machine check events logged\n");
1154 EXPORT_SYMBOL_GPL(mce_notify_irq);
1156 static int mce_banks_init(void)
1160 mce_banks = kzalloc(banks * sizeof(struct mce_bank), GFP_KERNEL);
1163 for (i = 0; i < banks; i++) {
1164 struct mce_bank *b = &mce_banks[i];
1172 * Initialize Machine Checks for a CPU.
1174 static int __cpuinit mce_cap_init(void)
1179 rdmsrl(MSR_IA32_MCG_CAP, cap);
1181 b = cap & MCG_BANKCNT_MASK;
1182 printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b);
1184 if (b > MAX_NR_BANKS) {
1186 "MCE: Using only %u machine check banks out of %u\n",
1191 /* Don't support asymmetric configurations today */
1192 WARN_ON(banks != 0 && b != banks);
1195 int err = mce_banks_init();
1200 /* Use accurate RIP reporting if available. */
1201 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1202 rip_msr = MSR_IA32_MCG_EIP;
1204 if (cap & MCG_SER_P)
1210 static void mce_init(void)
1212 mce_banks_t all_banks;
1217 * Log the machine checks left over from the previous reset.
1219 bitmap_fill(all_banks, MAX_NR_BANKS);
1220 machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks);
1222 set_in_cr4(X86_CR4_MCE);
1224 rdmsrl(MSR_IA32_MCG_CAP, cap);
1225 if (cap & MCG_CTL_P)
1226 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1228 for (i = 0; i < banks; i++) {
1229 struct mce_bank *b = &mce_banks[i];
1232 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
1233 wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
1237 /* Add per CPU specific workarounds here */
1238 static void __cpuinit mce_cpu_quirks(struct cpuinfo_x86 *c)
1240 /* This should be disabled by the BIOS, but isn't always */
1241 if (c->x86_vendor == X86_VENDOR_AMD) {
1242 if (c->x86 == 15 && banks > 4) {
1244 * disable GART TBL walk error reporting, which
1245 * trips off incorrectly with the IOMMU & 3ware
1248 clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1250 if (c->x86 <= 17 && mce_bootlog < 0) {
1252 * Lots of broken BIOS around that don't clear them
1253 * by default and leave crap in there. Don't log:
1258 * Various K7s with broken bank 0 around. Always disable
1261 if (c->x86 == 6 && banks > 0)
1262 mce_banks[0].ctl = 0;
1265 if (c->x86_vendor == X86_VENDOR_INTEL) {
1267 * SDM documents that on family 6 bank 0 should not be written
1268 * because it aliases to another special BIOS controlled
1270 * But it's not aliased anymore on model 0x1a+
1271 * Don't ignore bank 0 completely because there could be a
1272 * valid event later, merely don't write CTL0.
1275 if (c->x86 == 6 && c->x86_model < 0x1A && banks > 0)
1276 mce_banks[0].init = 0;
1279 * All newer Intel systems support MCE broadcasting. Enable
1280 * synchronization with a one second timeout.
1282 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1283 monarch_timeout < 0)
1284 monarch_timeout = USEC_PER_SEC;
1286 /* There are also broken BIOSes on some Pentium M systems. */
1287 if (c->x86 == 6 && c->x86_model == 13 && mce_bootlog < 0)
1290 if (monarch_timeout < 0)
1291 monarch_timeout = 0;
1292 if (mce_bootlog != 0)
1293 mce_panic_timeout = 30;
1296 static void __cpuinit mce_ancient_init(struct cpuinfo_x86 *c)
1300 switch (c->x86_vendor) {
1301 case X86_VENDOR_INTEL:
1302 intel_p5_mcheck_init(c);
1304 case X86_VENDOR_CENTAUR:
1305 winchip_mcheck_init(c);
1310 static void mce_cpu_features(struct cpuinfo_x86 *c)
1312 switch (c->x86_vendor) {
1313 case X86_VENDOR_INTEL:
1314 mce_intel_feature_init(c);
1316 case X86_VENDOR_AMD:
1317 mce_amd_feature_init(c);
1324 static void mce_init_timer(void)
1326 struct timer_list *t = &__get_cpu_var(mce_timer);
1327 int *n = &__get_cpu_var(next_interval);
1332 *n = check_interval * HZ;
1335 setup_timer(t, mcheck_timer, smp_processor_id());
1336 t->expires = round_jiffies(jiffies + *n);
1340 /* Handle unconfigured int18 (should never happen) */
1341 static void unexpected_machine_check(struct pt_regs *regs, long error_code)
1343 printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n",
1344 smp_processor_id());
1347 /* Call the installed machine check handler for this CPU setup. */
1348 void (*machine_check_vector)(struct pt_regs *, long error_code) =
1349 unexpected_machine_check;
1352 * Called for each booted CPU to set up machine checks.
1353 * Must be called with preempt off:
1355 void __cpuinit mcheck_init(struct cpuinfo_x86 *c)
1360 mce_ancient_init(c);
1362 if (!mce_available(c))
1365 if (mce_cap_init() < 0) {
1371 machine_check_vector = do_machine_check;
1374 mce_cpu_features(c);
1376 INIT_WORK(&__get_cpu_var(mce_work), mce_process_work);
1380 * Character device to read and clear the MCE log.
1383 static DEFINE_SPINLOCK(mce_state_lock);
1384 static int open_count; /* #times opened */
1385 static int open_exclu; /* already open exclusive? */
1387 static int mce_open(struct inode *inode, struct file *file)
1389 spin_lock(&mce_state_lock);
1391 if (open_exclu || (open_count && (file->f_flags & O_EXCL))) {
1392 spin_unlock(&mce_state_lock);
1397 if (file->f_flags & O_EXCL)
1401 spin_unlock(&mce_state_lock);
1403 return nonseekable_open(inode, file);
1406 static int mce_release(struct inode *inode, struct file *file)
1408 spin_lock(&mce_state_lock);
1413 spin_unlock(&mce_state_lock);
1418 static void collect_tscs(void *data)
1420 unsigned long *cpu_tsc = (unsigned long *)data;
1422 rdtscll(cpu_tsc[smp_processor_id()]);
1425 static DEFINE_MUTEX(mce_read_mutex);
1427 static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize,
1430 char __user *buf = ubuf;
1431 unsigned long *cpu_tsc;
1432 unsigned prev, next;
1435 cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL);
1439 mutex_lock(&mce_read_mutex);
1440 next = rcu_dereference(mcelog.next);
1442 /* Only supports full reads right now */
1443 if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) {
1444 mutex_unlock(&mce_read_mutex);
1453 for (i = prev; i < next; i++) {
1454 unsigned long start = jiffies;
1456 while (!mcelog.entry[i].finished) {
1457 if (time_after_eq(jiffies, start + 2)) {
1458 memset(mcelog.entry + i, 0,
1459 sizeof(struct mce));
1465 err |= copy_to_user(buf, mcelog.entry + i,
1466 sizeof(struct mce));
1467 buf += sizeof(struct mce);
1472 memset(mcelog.entry + prev, 0,
1473 (next - prev) * sizeof(struct mce));
1475 next = cmpxchg(&mcelog.next, prev, 0);
1476 } while (next != prev);
1478 synchronize_sched();
1481 * Collect entries that were still getting written before the
1484 on_each_cpu(collect_tscs, cpu_tsc, 1);
1486 for (i = next; i < MCE_LOG_LEN; i++) {
1487 if (mcelog.entry[i].finished &&
1488 mcelog.entry[i].tsc < cpu_tsc[mcelog.entry[i].cpu]) {
1489 err |= copy_to_user(buf, mcelog.entry+i,
1490 sizeof(struct mce));
1492 buf += sizeof(struct mce);
1493 memset(&mcelog.entry[i], 0, sizeof(struct mce));
1496 mutex_unlock(&mce_read_mutex);
1499 return err ? -EFAULT : buf - ubuf;
1502 static unsigned int mce_poll(struct file *file, poll_table *wait)
1504 poll_wait(file, &mce_wait, wait);
1505 if (rcu_dereference(mcelog.next))
1506 return POLLIN | POLLRDNORM;
1510 static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
1512 int __user *p = (int __user *)arg;
1514 if (!capable(CAP_SYS_ADMIN))
1518 case MCE_GET_RECORD_LEN:
1519 return put_user(sizeof(struct mce), p);
1520 case MCE_GET_LOG_LEN:
1521 return put_user(MCE_LOG_LEN, p);
1522 case MCE_GETCLEAR_FLAGS: {
1526 flags = mcelog.flags;
1527 } while (cmpxchg(&mcelog.flags, flags, 0) != flags);
1529 return put_user(flags, p);
1536 /* Modified in mce-inject.c, so not static or const */
1537 struct file_operations mce_chrdev_ops = {
1539 .release = mce_release,
1542 .unlocked_ioctl = mce_ioctl,
1544 EXPORT_SYMBOL_GPL(mce_chrdev_ops);
1546 static struct miscdevice mce_log_device = {
1553 * mce=off Disables machine check
1554 * mce=no_cmci Disables CMCI
1555 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
1556 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
1557 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
1558 * monarchtimeout is how long to wait for other CPUs on machine
1559 * check, or 0 to not wait
1560 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
1561 * mce=nobootlog Don't log MCEs from before booting.
1563 static int __init mcheck_enable(char *str)
1571 if (!strcmp(str, "off"))
1573 else if (!strcmp(str, "no_cmci"))
1574 mce_cmci_disabled = 1;
1575 else if (!strcmp(str, "dont_log_ce"))
1576 mce_dont_log_ce = 1;
1577 else if (!strcmp(str, "ignore_ce"))
1579 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
1580 mce_bootlog = (str[0] == 'b');
1581 else if (isdigit(str[0])) {
1582 get_option(&str, &tolerant);
1585 get_option(&str, &monarch_timeout);
1588 printk(KERN_INFO "mce argument %s ignored. Please use /sys\n",
1594 __setup("mce", mcheck_enable);
1601 * Disable machine checks on suspend and shutdown. We can't really handle
1604 static int mce_disable(void)
1608 for (i = 0; i < banks; i++) {
1609 struct mce_bank *b = &mce_banks[i];
1611 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
1616 static int mce_suspend(struct sys_device *dev, pm_message_t state)
1618 return mce_disable();
1621 static int mce_shutdown(struct sys_device *dev)
1623 return mce_disable();
1627 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1628 * Only one CPU is active at this time, the others get re-added later using
1631 static int mce_resume(struct sys_device *dev)
1634 mce_cpu_features(¤t_cpu_data);
1639 static void mce_cpu_restart(void *data)
1641 del_timer_sync(&__get_cpu_var(mce_timer));
1642 if (!mce_available(¤t_cpu_data))
1648 /* Reinit MCEs after user configuration changes */
1649 static void mce_restart(void)
1651 on_each_cpu(mce_cpu_restart, NULL, 1);
1654 /* Toggle features for corrected errors */
1655 static void mce_disable_ce(void *all)
1657 if (!mce_available(¤t_cpu_data))
1660 del_timer_sync(&__get_cpu_var(mce_timer));
1664 static void mce_enable_ce(void *all)
1666 if (!mce_available(¤t_cpu_data))
1674 static struct sysdev_class mce_sysclass = {
1675 .suspend = mce_suspend,
1676 .shutdown = mce_shutdown,
1677 .resume = mce_resume,
1678 .name = "machinecheck",
1681 DEFINE_PER_CPU(struct sys_device, mce_dev);
1684 void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
1686 static inline struct mce_bank *attr_to_bank(struct sysdev_attribute *attr)
1688 return container_of(attr, struct mce_bank, attr);
1691 static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr,
1694 return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl);
1697 static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr,
1698 const char *buf, size_t size)
1702 if (strict_strtoull(buf, 0, &new) < 0)
1705 attr_to_bank(attr)->ctl = new;
1712 show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf)
1714 strcpy(buf, mce_helper);
1716 return strlen(mce_helper) + 1;
1719 static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr,
1720 const char *buf, size_t siz)
1725 strncpy(mce_helper, buf, sizeof(mce_helper));
1726 mce_helper[sizeof(mce_helper)-1] = 0;
1727 len = strlen(mce_helper);
1728 p = strchr(mce_helper, '\n');
1736 static ssize_t set_ignore_ce(struct sys_device *s,
1737 struct sysdev_attribute *attr,
1738 const char *buf, size_t size)
1742 if (strict_strtoull(buf, 0, &new) < 0)
1745 if (mce_ignore_ce ^ !!new) {
1747 /* disable ce features */
1748 on_each_cpu(mce_disable_ce, (void *)1, 1);
1751 /* enable ce features */
1753 on_each_cpu(mce_enable_ce, (void *)1, 1);
1759 static ssize_t set_cmci_disabled(struct sys_device *s,
1760 struct sysdev_attribute *attr,
1761 const char *buf, size_t size)
1765 if (strict_strtoull(buf, 0, &new) < 0)
1768 if (mce_cmci_disabled ^ !!new) {
1771 on_each_cpu(mce_disable_ce, NULL, 1);
1772 mce_cmci_disabled = 1;
1775 mce_cmci_disabled = 0;
1776 on_each_cpu(mce_enable_ce, NULL, 1);
1782 static ssize_t store_int_with_restart(struct sys_device *s,
1783 struct sysdev_attribute *attr,
1784 const char *buf, size_t size)
1786 ssize_t ret = sysdev_store_int(s, attr, buf, size);
1791 static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger);
1792 static SYSDEV_INT_ATTR(tolerant, 0644, tolerant);
1793 static SYSDEV_INT_ATTR(monarch_timeout, 0644, monarch_timeout);
1794 static SYSDEV_INT_ATTR(dont_log_ce, 0644, mce_dont_log_ce);
1796 static struct sysdev_ext_attribute attr_check_interval = {
1797 _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int,
1798 store_int_with_restart),
1802 static struct sysdev_ext_attribute attr_ignore_ce = {
1803 _SYSDEV_ATTR(ignore_ce, 0644, sysdev_show_int, set_ignore_ce),
1807 static struct sysdev_ext_attribute attr_cmci_disabled = {
1808 _SYSDEV_ATTR(cmci_disabled, 0644, sysdev_show_int, set_cmci_disabled),
1812 static struct sysdev_attribute *mce_attrs[] = {
1813 &attr_tolerant.attr,
1814 &attr_check_interval.attr,
1816 &attr_monarch_timeout.attr,
1817 &attr_dont_log_ce.attr,
1818 &attr_ignore_ce.attr,
1819 &attr_cmci_disabled.attr,
1823 static cpumask_var_t mce_dev_initialized;
1825 /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */
1826 static __cpuinit int mce_create_device(unsigned int cpu)
1831 if (!mce_available(&boot_cpu_data))
1834 memset(&per_cpu(mce_dev, cpu).kobj, 0, sizeof(struct kobject));
1835 per_cpu(mce_dev, cpu).id = cpu;
1836 per_cpu(mce_dev, cpu).cls = &mce_sysclass;
1838 err = sysdev_register(&per_cpu(mce_dev, cpu));
1842 for (i = 0; mce_attrs[i]; i++) {
1843 err = sysdev_create_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1847 for (j = 0; j < banks; j++) {
1848 err = sysdev_create_file(&per_cpu(mce_dev, cpu),
1849 &mce_banks[j].attr);
1853 cpumask_set_cpu(cpu, mce_dev_initialized);
1858 sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[j].attr);
1861 sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[i].attr);
1863 sysdev_unregister(&per_cpu(mce_dev, cpu));
1868 static __cpuinit void mce_remove_device(unsigned int cpu)
1872 if (!cpumask_test_cpu(cpu, mce_dev_initialized))
1875 for (i = 0; mce_attrs[i]; i++)
1876 sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1878 for (i = 0; i < banks; i++)
1879 sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[i].attr);
1881 sysdev_unregister(&per_cpu(mce_dev, cpu));
1882 cpumask_clear_cpu(cpu, mce_dev_initialized);
1885 /* Make sure there are no machine checks on offlined CPUs. */
1886 static void mce_disable_cpu(void *h)
1888 unsigned long action = *(unsigned long *)h;
1891 if (!mce_available(¤t_cpu_data))
1893 if (!(action & CPU_TASKS_FROZEN))
1895 for (i = 0; i < banks; i++) {
1896 struct mce_bank *b = &mce_banks[i];
1898 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
1902 static void mce_reenable_cpu(void *h)
1904 unsigned long action = *(unsigned long *)h;
1907 if (!mce_available(¤t_cpu_data))
1910 if (!(action & CPU_TASKS_FROZEN))
1912 for (i = 0; i < banks; i++) {
1913 struct mce_bank *b = &mce_banks[i];
1915 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
1919 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
1920 static int __cpuinit
1921 mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
1923 unsigned int cpu = (unsigned long)hcpu;
1924 struct timer_list *t = &per_cpu(mce_timer, cpu);
1928 case CPU_ONLINE_FROZEN:
1929 mce_create_device(cpu);
1930 if (threshold_cpu_callback)
1931 threshold_cpu_callback(action, cpu);
1934 case CPU_DEAD_FROZEN:
1935 if (threshold_cpu_callback)
1936 threshold_cpu_callback(action, cpu);
1937 mce_remove_device(cpu);
1939 case CPU_DOWN_PREPARE:
1940 case CPU_DOWN_PREPARE_FROZEN:
1942 smp_call_function_single(cpu, mce_disable_cpu, &action, 1);
1944 case CPU_DOWN_FAILED:
1945 case CPU_DOWN_FAILED_FROZEN:
1946 t->expires = round_jiffies(jiffies +
1947 __get_cpu_var(next_interval));
1948 add_timer_on(t, cpu);
1949 smp_call_function_single(cpu, mce_reenable_cpu, &action, 1);
1952 /* intentionally ignoring frozen here */
1953 cmci_rediscover(cpu);
1959 static struct notifier_block mce_cpu_notifier __cpuinitdata = {
1960 .notifier_call = mce_cpu_callback,
1963 static __init void mce_init_banks(void)
1967 for (i = 0; i < banks; i++) {
1968 struct mce_bank *b = &mce_banks[i];
1969 struct sysdev_attribute *a = &b->attr;
1971 a->attr.name = b->attrname;
1972 snprintf(b->attrname, ATTR_LEN, "bank%d", i);
1974 a->attr.mode = 0644;
1975 a->show = show_bank;
1976 a->store = set_bank;
1980 static __init int mce_init_device(void)
1985 if (!mce_available(&boot_cpu_data))
1988 zalloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL);
1992 err = sysdev_class_register(&mce_sysclass);
1996 for_each_online_cpu(i) {
1997 err = mce_create_device(i);
2002 register_hotcpu_notifier(&mce_cpu_notifier);
2003 misc_register(&mce_log_device);
2008 device_initcall(mce_init_device);
2011 * Old style boot options parsing. Only for compatibility.
2013 static int __init mcheck_disable(char *str)
2018 __setup("nomce", mcheck_disable);
2020 #ifdef CONFIG_DEBUG_FS
2021 struct dentry *mce_get_debugfs_dir(void)
2023 static struct dentry *dmce;
2026 dmce = debugfs_create_dir("mce", NULL);
2031 static void mce_reset(void)
2034 atomic_set(&mce_fake_paniced, 0);
2035 atomic_set(&mce_executing, 0);
2036 atomic_set(&mce_callin, 0);
2037 atomic_set(&global_nwo, 0);
2040 static int fake_panic_get(void *data, u64 *val)
2046 static int fake_panic_set(void *data, u64 val)
2053 DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get,
2054 fake_panic_set, "%llu\n");
2056 static int __init mce_debugfs_init(void)
2058 struct dentry *dmce, *ffake_panic;
2060 dmce = mce_get_debugfs_dir();
2063 ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL,
2070 late_initcall(mce_debugfs_init);