2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
10 #include <linux/thread_info.h>
11 #include <linux/capability.h>
12 #include <linux/miscdevice.h>
13 #include <linux/interrupt.h>
14 #include <linux/ratelimit.h>
15 #include <linux/kallsyms.h>
16 #include <linux/rcupdate.h>
17 #include <linux/kobject.h>
18 #include <linux/uaccess.h>
19 #include <linux/kdebug.h>
20 #include <linux/kernel.h>
21 #include <linux/percpu.h>
22 #include <linux/string.h>
23 #include <linux/sysdev.h>
24 #include <linux/delay.h>
25 #include <linux/ctype.h>
26 #include <linux/sched.h>
27 #include <linux/sysfs.h>
28 #include <linux/types.h>
29 #include <linux/init.h>
30 #include <linux/kmod.h>
31 #include <linux/poll.h>
32 #include <linux/nmi.h>
33 #include <linux/cpu.h>
34 #include <linux/smp.h>
38 #include <asm/processor.h>
39 #include <asm/hw_irq.h>
46 #include "mce-internal.h"
49 /* Handle unconfigured int18 (should never happen) */
50 static void unexpected_machine_check(struct pt_regs *regs, long error_code)
52 printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n",
56 /* Call the installed machine check handler for this CPU setup. */
57 void (*machine_check_vector)(struct pt_regs *, long error_code) =
58 unexpected_machine_check;
60 int mce_disabled __read_mostly;
62 #ifdef CONFIG_X86_NEW_MCE
64 #define MISC_MCELOG_MINOR 227
66 #define SPINUNIT 100 /* 100ns */
70 DEFINE_PER_CPU(unsigned, mce_exception_count);
74 * 0: always panic on uncorrected errors, log corrected errors
75 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
76 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
77 * 3: never panic or SIGBUS, log all errors (for testing only)
79 static int tolerant __read_mostly = 1;
80 static int banks __read_mostly;
81 static u64 *bank __read_mostly;
82 static int rip_msr __read_mostly;
83 static int mce_bootlog __read_mostly = -1;
84 static int monarch_timeout __read_mostly = -1;
85 static int mce_panic_timeout __read_mostly;
86 static int mce_dont_log_ce __read_mostly;
87 int mce_cmci_disabled __read_mostly;
88 int mce_ignore_ce __read_mostly;
89 int mce_ser __read_mostly;
91 /* User mode helper program triggered by machine check event */
92 static unsigned long mce_need_notify;
93 static char mce_helper[128];
94 static char *mce_helper_argv[2] = { mce_helper, NULL };
96 static unsigned long dont_init_banks;
98 static DECLARE_WAIT_QUEUE_HEAD(mce_wait);
99 static DEFINE_PER_CPU(struct mce, mces_seen);
100 static int cpu_missing;
103 /* MCA banks polled by the period polling timer for corrected events */
104 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
105 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
108 static inline int skip_bank_init(int i)
110 return i < BITS_PER_LONG && test_bit(i, &dont_init_banks);
113 static DEFINE_PER_CPU(struct work_struct, mce_work);
115 /* Do initial initialization of a struct mce */
116 void mce_setup(struct mce *m)
118 memset(m, 0, sizeof(struct mce));
119 m->cpu = m->extcpu = smp_processor_id();
121 /* We hope get_seconds stays lockless */
122 m->time = get_seconds();
123 m->cpuvendor = boot_cpu_data.x86_vendor;
124 m->cpuid = cpuid_eax(1);
126 m->socketid = cpu_data(m->extcpu).phys_proc_id;
128 m->apicid = cpu_data(m->extcpu).initial_apicid;
129 rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap);
132 DEFINE_PER_CPU(struct mce, injectm);
133 EXPORT_PER_CPU_SYMBOL_GPL(injectm);
136 * Lockless MCE logging infrastructure.
137 * This avoids deadlocks on printk locks without having to break locks. Also
138 * separate MCEs from kernel messages to avoid bogus bug reports.
141 static struct mce_log mcelog = {
142 .signature = MCE_LOG_SIGNATURE,
144 .recordlen = sizeof(struct mce),
147 void mce_log(struct mce *mce)
149 unsigned next, entry;
154 entry = rcu_dereference(mcelog.next);
157 * When the buffer fills up discard new entries.
158 * Assume that the earlier errors are the more
161 if (entry >= MCE_LOG_LEN) {
162 set_bit(MCE_OVERFLOW,
163 (unsigned long *)&mcelog.flags);
166 /* Old left over entry. Skip: */
167 if (mcelog.entry[entry].finished) {
175 if (cmpxchg(&mcelog.next, entry, next) == entry)
178 memcpy(mcelog.entry + entry, mce, sizeof(struct mce));
180 mcelog.entry[entry].finished = 1;
184 set_bit(0, &mce_need_notify);
187 static void print_mce(struct mce *m)
190 "CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n",
191 m->extcpu, m->mcgstatus, m->bank, m->status);
193 printk(KERN_EMERG "RIP%s %02x:<%016Lx> ",
194 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
196 if (m->cs == __KERNEL_CS)
197 print_symbol("{%s}", m->ip);
200 printk(KERN_EMERG "TSC %llx ", m->tsc);
202 printk("ADDR %llx ", m->addr);
204 printk("MISC %llx ", m->misc);
206 printk(KERN_EMERG "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
207 m->cpuvendor, m->cpuid, m->time, m->socketid,
211 static void print_mce_head(void)
213 printk(KERN_EMERG "\n" KERN_EMERG "HARDWARE ERROR\n");
216 static void print_mce_tail(void)
218 printk(KERN_EMERG "This is not a software problem!\n"
219 KERN_EMERG "Run through mcelog --ascii to decode and contact your hardware vendor\n");
222 #define PANIC_TIMEOUT 5 /* 5 seconds */
224 static atomic_t mce_paniced;
226 /* Panic in progress. Enable interrupts and wait for final IPI */
227 static void wait_for_panic(void)
229 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
232 while (timeout-- > 0)
234 if (panic_timeout == 0)
235 panic_timeout = mce_panic_timeout;
236 panic("Panicing machine check CPU died");
239 static void mce_panic(char *msg, struct mce *final, char *exp)
244 * Make sure only one CPU runs in machine check panic
246 if (atomic_add_return(1, &mce_paniced) > 1)
253 /* First print corrected ones that are still unlogged */
254 for (i = 0; i < MCE_LOG_LEN; i++) {
255 struct mce *m = &mcelog.entry[i];
256 if (!(m->status & MCI_STATUS_VAL))
258 if (!(m->status & MCI_STATUS_UC))
261 /* Now print uncorrected but with the final one last */
262 for (i = 0; i < MCE_LOG_LEN; i++) {
263 struct mce *m = &mcelog.entry[i];
264 if (!(m->status & MCI_STATUS_VAL))
266 if (!(m->status & MCI_STATUS_UC))
268 if (!final || memcmp(m, final, sizeof(struct mce)))
274 printk(KERN_EMERG "Some CPUs didn't answer in synchronization\n");
277 printk(KERN_EMERG "Machine check: %s\n", exp);
278 if (panic_timeout == 0)
279 panic_timeout = mce_panic_timeout;
283 /* Support code for software error injection */
285 static int msr_to_offset(u32 msr)
287 unsigned bank = __get_cpu_var(injectm.bank);
289 return offsetof(struct mce, ip);
290 if (msr == MSR_IA32_MC0_STATUS + bank*4)
291 return offsetof(struct mce, status);
292 if (msr == MSR_IA32_MC0_ADDR + bank*4)
293 return offsetof(struct mce, addr);
294 if (msr == MSR_IA32_MC0_MISC + bank*4)
295 return offsetof(struct mce, misc);
296 if (msr == MSR_IA32_MCG_STATUS)
297 return offsetof(struct mce, mcgstatus);
301 /* MSR access wrappers used for error injection */
302 static u64 mce_rdmsrl(u32 msr)
305 if (__get_cpu_var(injectm).finished) {
306 int offset = msr_to_offset(msr);
309 return *(u64 *)((char *)&__get_cpu_var(injectm) + offset);
315 static void mce_wrmsrl(u32 msr, u64 v)
317 if (__get_cpu_var(injectm).finished) {
318 int offset = msr_to_offset(msr);
320 *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v;
327 * Simple lockless ring to communicate PFNs from the exception handler with the
328 * process context work function. This is vastly simplified because there's
329 * only a single reader and a single writer.
331 #define MCE_RING_SIZE 16 /* we use one entry less */
334 unsigned short start;
336 unsigned long ring[MCE_RING_SIZE];
338 static DEFINE_PER_CPU(struct mce_ring, mce_ring);
340 /* Runs with CPU affinity in workqueue */
341 static int mce_ring_empty(void)
343 struct mce_ring *r = &__get_cpu_var(mce_ring);
345 return r->start == r->end;
348 static int mce_ring_get(unsigned long *pfn)
355 r = &__get_cpu_var(mce_ring);
356 if (r->start == r->end)
358 *pfn = r->ring[r->start];
359 r->start = (r->start + 1) % MCE_RING_SIZE;
366 /* Always runs in MCE context with preempt off */
367 static int mce_ring_add(unsigned long pfn)
369 struct mce_ring *r = &__get_cpu_var(mce_ring);
372 next = (r->end + 1) % MCE_RING_SIZE;
373 if (next == r->start)
375 r->ring[r->end] = pfn;
381 int mce_available(struct cpuinfo_x86 *c)
385 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
388 static void mce_schedule_work(void)
390 if (!mce_ring_empty()) {
391 struct work_struct *work = &__get_cpu_var(mce_work);
392 if (!work_pending(work))
398 * Get the address of the instruction at the time of the machine check
401 static inline void mce_get_rip(struct mce *m, struct pt_regs *regs)
404 if (regs && (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV))) {
412 m->ip = mce_rdmsrl(rip_msr);
415 #ifdef CONFIG_X86_LOCAL_APIC
417 * Called after interrupts have been reenabled again
418 * when a MCE happened during an interrupts off region
421 asmlinkage void smp_mce_self_interrupt(struct pt_regs *regs)
432 static void mce_report_event(struct pt_regs *regs)
434 if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) {
437 * Triggering the work queue here is just an insurance
438 * policy in case the syscall exit notify handler
439 * doesn't run soon enough or ends up running on the
440 * wrong CPU (can happen when audit sleeps)
446 #ifdef CONFIG_X86_LOCAL_APIC
448 * Without APIC do not notify. The event will be picked
455 * When interrupts are disabled we cannot use
456 * kernel services safely. Trigger an self interrupt
457 * through the APIC to instead do the notification
458 * after interrupts are reenabled again.
460 apic->send_IPI_self(MCE_SELF_VECTOR);
463 * Wait for idle afterwards again so that we don't leave the
464 * APIC in a non idle state because the normal APIC writes
467 apic_wait_icr_idle();
471 DEFINE_PER_CPU(unsigned, mce_poll_count);
474 * Poll for corrected events or events that happened before reset.
475 * Those are just logged through /dev/mcelog.
477 * This is executed in standard interrupt context.
479 * Note: spec recommends to panic for fatal unsignalled
480 * errors here. However this would be quite problematic --
481 * we would need to reimplement the Monarch handling and
482 * it would mess up the exclusion between exception handler
483 * and poll hander -- * so we skip this for now.
484 * These cases should not happen anyways, or only when the CPU
485 * is already totally * confused. In this case it's likely it will
486 * not fully execute the machine check handler either.
488 void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
493 __get_cpu_var(mce_poll_count)++;
497 m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
498 for (i = 0; i < banks; i++) {
499 if (!bank[i] || !test_bit(i, *b))
508 m.status = mce_rdmsrl(MSR_IA32_MC0_STATUS + i*4);
509 if (!(m.status & MCI_STATUS_VAL))
513 * Uncorrected or signalled events are handled by the exception
514 * handler when it is enabled, so don't process those here.
516 * TBD do the same check for MCI_STATUS_EN here?
518 if (!(flags & MCP_UC) &&
519 (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)))
522 if (m.status & MCI_STATUS_MISCV)
523 m.misc = mce_rdmsrl(MSR_IA32_MC0_MISC + i*4);
524 if (m.status & MCI_STATUS_ADDRV)
525 m.addr = mce_rdmsrl(MSR_IA32_MC0_ADDR + i*4);
527 if (!(flags & MCP_TIMESTAMP))
530 * Don't get the IP here because it's unlikely to
531 * have anything to do with the actual error location.
533 if (!(flags & MCP_DONTLOG) && !mce_dont_log_ce) {
535 add_taint(TAINT_MACHINE_CHECK);
539 * Clear state for this bank.
541 mce_wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0);
545 * Don't clear MCG_STATUS here because it's only defined for
551 EXPORT_SYMBOL_GPL(machine_check_poll);
554 * Do a quick check if any of the events requires a panic.
555 * This decides if we keep the events around or clear them.
557 static int mce_no_way_out(struct mce *m, char **msg)
561 for (i = 0; i < banks; i++) {
562 m->status = mce_rdmsrl(MSR_IA32_MC0_STATUS + i*4);
563 if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY)
570 * Variable to establish order between CPUs while scanning.
571 * Each CPU spins initially until executing is equal its number.
573 static atomic_t mce_executing;
576 * Defines order of CPUs on entry. First CPU becomes Monarch.
578 static atomic_t mce_callin;
581 * Check if a timeout waiting for other CPUs happened.
583 static int mce_timed_out(u64 *t)
586 * The others already did panic for some reason.
587 * Bail out like in a timeout.
588 * rmb() to tell the compiler that system_state
589 * might have been modified by someone else.
592 if (atomic_read(&mce_paniced))
594 if (!monarch_timeout)
596 if ((s64)*t < SPINUNIT) {
597 /* CHECKME: Make panic default for 1 too? */
599 mce_panic("Timeout synchronizing machine check over CPUs",
606 touch_nmi_watchdog();
611 * The Monarch's reign. The Monarch is the CPU who entered
612 * the machine check handler first. It waits for the others to
613 * raise the exception too and then grades them. When any
614 * error is fatal panic. Only then let the others continue.
616 * The other CPUs entering the MCE handler will be controlled by the
617 * Monarch. They are called Subjects.
619 * This way we prevent any potential data corruption in a unrecoverable case
620 * and also makes sure always all CPU's errors are examined.
622 * Also this detects the case of an machine check event coming from outer
623 * space (not detected by any CPUs) In this case some external agent wants
624 * us to shut down, so panic too.
626 * The other CPUs might still decide to panic if the handler happens
627 * in a unrecoverable place, but in this case the system is in a semi-stable
628 * state and won't corrupt anything by itself. It's ok to let the others
629 * continue for a bit first.
631 * All the spin loops have timeouts; when a timeout happens a CPU
632 * typically elects itself to be Monarch.
634 static void mce_reign(void)
637 struct mce *m = NULL;
638 int global_worst = 0;
643 * This CPU is the Monarch and the other CPUs have run
644 * through their handlers.
645 * Grade the severity of the errors of all the CPUs.
647 for_each_possible_cpu(cpu) {
648 int severity = mce_severity(&per_cpu(mces_seen, cpu), tolerant,
650 if (severity > global_worst) {
652 global_worst = severity;
653 m = &per_cpu(mces_seen, cpu);
658 * Cannot recover? Panic here then.
659 * This dumps all the mces in the log buffer and stops the
662 if (m && global_worst >= MCE_PANIC_SEVERITY && tolerant < 3)
663 mce_panic("Fatal Machine check", m, msg);
666 * For UC somewhere we let the CPU who detects it handle it.
667 * Also must let continue the others, otherwise the handling
668 * CPU could deadlock on a lock.
672 * No machine check event found. Must be some external
673 * source or one CPU is hung. Panic.
675 if (!m && tolerant < 3)
676 mce_panic("Machine check from unknown source", NULL, NULL);
679 * Now clear all the mces_seen so that they don't reappear on
682 for_each_possible_cpu(cpu)
683 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
686 static atomic_t global_nwo;
689 * Start of Monarch synchronization. This waits until all CPUs have
690 * entered the exception handler and then determines if any of them
691 * saw a fatal event that requires panic. Then it executes them
692 * in the entry order.
693 * TBD double check parallel CPU hotunplug
695 static int mce_start(int *no_way_out)
698 int cpus = num_online_cpus();
699 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
704 atomic_add(*no_way_out, &global_nwo);
706 * global_nwo should be updated before mce_callin
709 order = atomic_add_return(1, &mce_callin);
714 while (atomic_read(&mce_callin) != cpus) {
715 if (mce_timed_out(&timeout)) {
716 atomic_set(&global_nwo, 0);
723 * mce_callin should be read before global_nwo
729 * Monarch: Starts executing now, the others wait.
731 atomic_set(&mce_executing, 1);
734 * Subject: Now start the scanning loop one by one in
735 * the original callin order.
736 * This way when there are any shared banks it will be
737 * only seen by one CPU before cleared, avoiding duplicates.
739 while (atomic_read(&mce_executing) < order) {
740 if (mce_timed_out(&timeout)) {
741 atomic_set(&global_nwo, 0);
749 * Cache the global no_way_out state.
751 *no_way_out = atomic_read(&global_nwo);
757 * Synchronize between CPUs after main scanning loop.
758 * This invokes the bulk of the Monarch processing.
760 static int mce_end(int order)
763 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
771 * Allow others to run.
773 atomic_inc(&mce_executing);
776 /* CHECKME: Can this race with a parallel hotplug? */
777 int cpus = num_online_cpus();
780 * Monarch: Wait for everyone to go through their scanning
783 while (atomic_read(&mce_executing) <= cpus) {
784 if (mce_timed_out(&timeout))
794 * Subject: Wait for Monarch to finish.
796 while (atomic_read(&mce_executing) != 0) {
797 if (mce_timed_out(&timeout))
803 * Don't reset anything. That's done by the Monarch.
809 * Reset all global state.
812 atomic_set(&global_nwo, 0);
813 atomic_set(&mce_callin, 0);
817 * Let others run again.
819 atomic_set(&mce_executing, 0);
824 * Check if the address reported by the CPU is in a format we can parse.
825 * It would be possible to add code for most other cases, but all would
826 * be somewhat complicated (e.g. segment offset would require an instruction
827 * parser). So only support physical addresses upto page granuality for now.
829 static int mce_usable_address(struct mce *m)
831 if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV))
833 if ((m->misc & 0x3f) > PAGE_SHIFT)
835 if (((m->misc >> 6) & 7) != MCM_ADDR_PHYS)
840 static void mce_clear_state(unsigned long *toclear)
844 for (i = 0; i < banks; i++) {
845 if (test_bit(i, toclear))
846 mce_wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0);
851 * The actual machine check handler. This only handles real
852 * exceptions when something got corrupted coming in through int 18.
854 * This is executed in NMI context not subject to normal locking rules. This
855 * implies that most kernel services cannot be safely used. Don't even
856 * think about putting a printk in there!
858 * On Intel systems this is entered on all CPUs in parallel through
859 * MCE broadcast. However some CPUs might be broken beyond repair,
860 * so be always careful when synchronizing with others.
862 void do_machine_check(struct pt_regs *regs, long error_code)
864 struct mce m, *final;
869 * Establish sequential order between the CPUs entering the machine
874 * If no_way_out gets set, there is no safe way to recover from this
875 * MCE. If tolerant is cranked up, we'll try anyway.
879 * If kill_it gets set, there might be a way to recover from this
883 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
884 char *msg = "Unknown";
886 atomic_inc(&mce_entry);
888 __get_cpu_var(mce_exception_count)++;
890 if (notify_die(DIE_NMI, "machine check", regs, error_code,
891 18, SIGKILL) == NOTIFY_STOP)
898 m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
899 no_way_out = mce_no_way_out(&m, &msg);
901 final = &__get_cpu_var(mces_seen);
907 * When no restart IP must always kill or panic.
909 if (!(m.mcgstatus & MCG_STATUS_RIPV))
913 * Go through all the banks in exclusion of the other CPUs.
914 * This way we don't report duplicated events on shared banks
915 * because the first one to see it will clear it.
917 order = mce_start(&no_way_out);
918 for (i = 0; i < banks; i++) {
919 __clear_bit(i, toclear);
927 m.status = mce_rdmsrl(MSR_IA32_MC0_STATUS + i*4);
928 if ((m.status & MCI_STATUS_VAL) == 0)
932 * Non uncorrected or non signaled errors are handled by
933 * machine_check_poll. Leave them alone, unless this panics.
935 if (!(m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
940 * Set taint even when machine check was not enabled.
942 add_taint(TAINT_MACHINE_CHECK);
944 severity = mce_severity(&m, tolerant, NULL);
947 * When machine check was for corrected handler don't touch,
948 * unless we're panicing.
950 if (severity == MCE_KEEP_SEVERITY && !no_way_out)
952 __set_bit(i, toclear);
953 if (severity == MCE_NO_SEVERITY) {
955 * Machine check event was not enabled. Clear, but
962 * Kill on action required.
964 if (severity == MCE_AR_SEVERITY)
967 if (m.status & MCI_STATUS_MISCV)
968 m.misc = mce_rdmsrl(MSR_IA32_MC0_MISC + i*4);
969 if (m.status & MCI_STATUS_ADDRV)
970 m.addr = mce_rdmsrl(MSR_IA32_MC0_ADDR + i*4);
973 * Action optional error. Queue address for later processing.
974 * When the ring overflows we just ignore the AO error.
975 * RED-PEN add some logging mechanism when
976 * usable_address or mce_add_ring fails.
977 * RED-PEN don't ignore overflow for tolerant == 0
979 if (severity == MCE_AO_SEVERITY && mce_usable_address(&m))
980 mce_ring_add(m.addr >> PAGE_SHIFT);
982 mce_get_rip(&m, regs);
985 if (severity > worst) {
992 mce_clear_state(toclear);
995 * Do most of the synchronization with other CPUs.
996 * When there's any problem use only local no_way_out state.
998 if (mce_end(order) < 0)
999 no_way_out = worst >= MCE_PANIC_SEVERITY;
1002 * If we have decided that we just CAN'T continue, and the user
1003 * has not set tolerant to an insane level, give up and die.
1005 * This is mainly used in the case when the system doesn't
1006 * support MCE broadcasting or it has been disabled.
1008 if (no_way_out && tolerant < 3)
1009 mce_panic("Fatal machine check on current CPU", final, msg);
1012 * If the error seems to be unrecoverable, something should be
1013 * done. Try to kill as little as possible. If we can kill just
1014 * one task, do that. If the user has set the tolerance very
1015 * high, don't try to do anything at all.
1018 if (kill_it && tolerant < 3)
1019 force_sig(SIGBUS, current);
1021 /* notify userspace ASAP */
1022 set_thread_flag(TIF_MCE_NOTIFY);
1025 mce_report_event(regs);
1026 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1028 atomic_dec(&mce_entry);
1031 EXPORT_SYMBOL_GPL(do_machine_check);
1033 /* dummy to break dependency. actual code is in mm/memory-failure.c */
1034 void __attribute__((weak)) memory_failure(unsigned long pfn, int vector)
1036 printk(KERN_ERR "Action optional memory failure at %lx ignored\n", pfn);
1040 * Called after mce notification in process context. This code
1041 * is allowed to sleep. Call the high level VM handler to process
1042 * any corrupted pages.
1043 * Assume that the work queue code only calls this one at a time
1045 * Note we don't disable preemption, so this code might run on the wrong
1046 * CPU. In this case the event is picked up by the scheduled work queue.
1047 * This is merely a fast path to expedite processing in some common
1050 void mce_notify_process(void)
1054 while (mce_ring_get(&pfn))
1055 memory_failure(pfn, MCE_VECTOR);
1058 static void mce_process_work(struct work_struct *dummy)
1060 mce_notify_process();
1063 #ifdef CONFIG_X86_MCE_INTEL
1065 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
1066 * @cpu: The CPU on which the event occurred.
1067 * @status: Event status information
1069 * This function should be called by the thermal interrupt after the
1070 * event has been processed and the decision was made to log the event
1073 * The status parameter will be saved to the 'status' field of 'struct mce'
1074 * and historically has been the register value of the
1075 * MSR_IA32_THERMAL_STATUS (Intel) msr.
1077 void mce_log_therm_throt_event(__u64 status)
1082 m.bank = MCE_THERMAL_BANK;
1086 #endif /* CONFIG_X86_MCE_INTEL */
1089 * Periodic polling timer for "silent" machine check errors. If the
1090 * poller finds an MCE, poll 2x faster. When the poller finds no more
1091 * errors, poll 2x slower (up to check_interval seconds).
1093 static int check_interval = 5 * 60; /* 5 minutes */
1095 static DEFINE_PER_CPU(int, next_interval); /* in jiffies */
1096 static DEFINE_PER_CPU(struct timer_list, mce_timer);
1098 static void mcheck_timer(unsigned long data)
1100 struct timer_list *t = &per_cpu(mce_timer, data);
1103 WARN_ON(smp_processor_id() != data);
1105 if (mce_available(¤t_cpu_data)) {
1106 machine_check_poll(MCP_TIMESTAMP,
1107 &__get_cpu_var(mce_poll_banks));
1111 * Alert userspace if needed. If we logged an MCE, reduce the
1112 * polling interval, otherwise increase the polling interval.
1114 n = &__get_cpu_var(next_interval);
1115 if (mce_notify_irq())
1116 *n = max(*n/2, HZ/100);
1118 *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ));
1120 t->expires = jiffies + *n;
1124 static void mce_do_trigger(struct work_struct *work)
1126 call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT);
1129 static DECLARE_WORK(mce_trigger_work, mce_do_trigger);
1132 * Notify the user(s) about new machine check events.
1133 * Can be called from interrupt context, but not from machine check/NMI
1136 int mce_notify_irq(void)
1138 /* Not more than two messages every minute */
1139 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1141 clear_thread_flag(TIF_MCE_NOTIFY);
1143 if (test_and_clear_bit(0, &mce_need_notify)) {
1144 wake_up_interruptible(&mce_wait);
1147 * There is no risk of missing notifications because
1148 * work_pending is always cleared before the function is
1151 if (mce_helper[0] && !work_pending(&mce_trigger_work))
1152 schedule_work(&mce_trigger_work);
1154 if (__ratelimit(&ratelimit))
1155 printk(KERN_INFO "Machine check events logged\n");
1161 EXPORT_SYMBOL_GPL(mce_notify_irq);
1164 * Initialize Machine Checks for a CPU.
1166 static int mce_cap_init(void)
1171 rdmsrl(MSR_IA32_MCG_CAP, cap);
1173 b = cap & MCG_BANKCNT_MASK;
1174 printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b);
1176 if (b > MAX_NR_BANKS) {
1178 "MCE: Using only %u machine check banks out of %u\n",
1183 /* Don't support asymmetric configurations today */
1184 WARN_ON(banks != 0 && b != banks);
1187 bank = kmalloc(banks * sizeof(u64), GFP_KERNEL);
1190 memset(bank, 0xff, banks * sizeof(u64));
1193 /* Use accurate RIP reporting if available. */
1194 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1195 rip_msr = MSR_IA32_MCG_EIP;
1197 if (cap & MCG_SER_P)
1203 static void mce_init(void)
1205 mce_banks_t all_banks;
1210 * Log the machine checks left over from the previous reset.
1212 bitmap_fill(all_banks, MAX_NR_BANKS);
1213 machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks);
1215 set_in_cr4(X86_CR4_MCE);
1217 rdmsrl(MSR_IA32_MCG_CAP, cap);
1218 if (cap & MCG_CTL_P)
1219 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1221 for (i = 0; i < banks; i++) {
1222 if (skip_bank_init(i))
1224 wrmsrl(MSR_IA32_MC0_CTL+4*i, bank[i]);
1225 wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0);
1229 /* Add per CPU specific workarounds here */
1230 static void mce_cpu_quirks(struct cpuinfo_x86 *c)
1232 /* This should be disabled by the BIOS, but isn't always */
1233 if (c->x86_vendor == X86_VENDOR_AMD) {
1234 if (c->x86 == 15 && banks > 4) {
1236 * disable GART TBL walk error reporting, which
1237 * trips off incorrectly with the IOMMU & 3ware
1240 clear_bit(10, (unsigned long *)&bank[4]);
1242 if (c->x86 <= 17 && mce_bootlog < 0) {
1244 * Lots of broken BIOS around that don't clear them
1245 * by default and leave crap in there. Don't log:
1250 * Various K7s with broken bank 0 around. Always disable
1257 if (c->x86_vendor == X86_VENDOR_INTEL) {
1259 * SDM documents that on family 6 bank 0 should not be written
1260 * because it aliases to another special BIOS controlled
1262 * But it's not aliased anymore on model 0x1a+
1263 * Don't ignore bank 0 completely because there could be a
1264 * valid event later, merely don't write CTL0.
1267 if (c->x86 == 6 && c->x86_model < 0x1A)
1268 __set_bit(0, &dont_init_banks);
1271 * All newer Intel systems support MCE broadcasting. Enable
1272 * synchronization with a one second timeout.
1274 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1275 monarch_timeout < 0)
1276 monarch_timeout = USEC_PER_SEC;
1278 if (monarch_timeout < 0)
1279 monarch_timeout = 0;
1280 if (mce_bootlog != 0)
1281 mce_panic_timeout = 30;
1284 static void __cpuinit mce_ancient_init(struct cpuinfo_x86 *c)
1288 switch (c->x86_vendor) {
1289 case X86_VENDOR_INTEL:
1290 if (mce_p5_enabled())
1291 intel_p5_mcheck_init(c);
1293 case X86_VENDOR_CENTAUR:
1294 winchip_mcheck_init(c);
1299 static void mce_cpu_features(struct cpuinfo_x86 *c)
1301 switch (c->x86_vendor) {
1302 case X86_VENDOR_INTEL:
1303 mce_intel_feature_init(c);
1305 case X86_VENDOR_AMD:
1306 mce_amd_feature_init(c);
1313 static void mce_init_timer(void)
1315 struct timer_list *t = &__get_cpu_var(mce_timer);
1316 int *n = &__get_cpu_var(next_interval);
1321 *n = check_interval * HZ;
1324 setup_timer(t, mcheck_timer, smp_processor_id());
1325 t->expires = round_jiffies(jiffies + *n);
1330 * Called for each booted CPU to set up machine checks.
1331 * Must be called with preempt off:
1333 void __cpuinit mcheck_init(struct cpuinfo_x86 *c)
1338 mce_ancient_init(c);
1340 if (!mce_available(c))
1343 if (mce_cap_init() < 0) {
1349 machine_check_vector = do_machine_check;
1352 mce_cpu_features(c);
1354 INIT_WORK(&__get_cpu_var(mce_work), mce_process_work);
1358 * Character device to read and clear the MCE log.
1361 static DEFINE_SPINLOCK(mce_state_lock);
1362 static int open_count; /* #times opened */
1363 static int open_exclu; /* already open exclusive? */
1365 static int mce_open(struct inode *inode, struct file *file)
1367 spin_lock(&mce_state_lock);
1369 if (open_exclu || (open_count && (file->f_flags & O_EXCL))) {
1370 spin_unlock(&mce_state_lock);
1375 if (file->f_flags & O_EXCL)
1379 spin_unlock(&mce_state_lock);
1381 return nonseekable_open(inode, file);
1384 static int mce_release(struct inode *inode, struct file *file)
1386 spin_lock(&mce_state_lock);
1391 spin_unlock(&mce_state_lock);
1396 static void collect_tscs(void *data)
1398 unsigned long *cpu_tsc = (unsigned long *)data;
1400 rdtscll(cpu_tsc[smp_processor_id()]);
1403 static DEFINE_MUTEX(mce_read_mutex);
1405 static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize,
1408 char __user *buf = ubuf;
1409 unsigned long *cpu_tsc;
1410 unsigned prev, next;
1413 cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL);
1417 mutex_lock(&mce_read_mutex);
1418 next = rcu_dereference(mcelog.next);
1420 /* Only supports full reads right now */
1421 if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) {
1422 mutex_unlock(&mce_read_mutex);
1431 for (i = prev; i < next; i++) {
1432 unsigned long start = jiffies;
1434 while (!mcelog.entry[i].finished) {
1435 if (time_after_eq(jiffies, start + 2)) {
1436 memset(mcelog.entry + i, 0,
1437 sizeof(struct mce));
1443 err |= copy_to_user(buf, mcelog.entry + i,
1444 sizeof(struct mce));
1445 buf += sizeof(struct mce);
1450 memset(mcelog.entry + prev, 0,
1451 (next - prev) * sizeof(struct mce));
1453 next = cmpxchg(&mcelog.next, prev, 0);
1454 } while (next != prev);
1456 synchronize_sched();
1459 * Collect entries that were still getting written before the
1462 on_each_cpu(collect_tscs, cpu_tsc, 1);
1464 for (i = next; i < MCE_LOG_LEN; i++) {
1465 if (mcelog.entry[i].finished &&
1466 mcelog.entry[i].tsc < cpu_tsc[mcelog.entry[i].cpu]) {
1467 err |= copy_to_user(buf, mcelog.entry+i,
1468 sizeof(struct mce));
1470 buf += sizeof(struct mce);
1471 memset(&mcelog.entry[i], 0, sizeof(struct mce));
1474 mutex_unlock(&mce_read_mutex);
1477 return err ? -EFAULT : buf - ubuf;
1480 static unsigned int mce_poll(struct file *file, poll_table *wait)
1482 poll_wait(file, &mce_wait, wait);
1483 if (rcu_dereference(mcelog.next))
1484 return POLLIN | POLLRDNORM;
1488 static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
1490 int __user *p = (int __user *)arg;
1492 if (!capable(CAP_SYS_ADMIN))
1496 case MCE_GET_RECORD_LEN:
1497 return put_user(sizeof(struct mce), p);
1498 case MCE_GET_LOG_LEN:
1499 return put_user(MCE_LOG_LEN, p);
1500 case MCE_GETCLEAR_FLAGS: {
1504 flags = mcelog.flags;
1505 } while (cmpxchg(&mcelog.flags, flags, 0) != flags);
1507 return put_user(flags, p);
1514 /* Modified in mce-inject.c, so not static or const */
1515 struct file_operations mce_chrdev_ops = {
1517 .release = mce_release,
1520 .unlocked_ioctl = mce_ioctl,
1522 EXPORT_SYMBOL_GPL(mce_chrdev_ops);
1524 static struct miscdevice mce_log_device = {
1531 * mce=off Disables machine check
1532 * mce=no_cmci Disables CMCI
1533 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
1534 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
1535 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
1536 * monarchtimeout is how long to wait for other CPUs on machine
1537 * check, or 0 to not wait
1538 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
1539 * mce=nobootlog Don't log MCEs from before booting.
1541 static int __init mcheck_enable(char *str)
1547 if (!strcmp(str, "off"))
1549 else if (!strcmp(str, "no_cmci"))
1550 mce_cmci_disabled = 1;
1551 else if (!strcmp(str, "dont_log_ce"))
1552 mce_dont_log_ce = 1;
1553 else if (!strcmp(str, "ignore_ce"))
1555 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
1556 mce_bootlog = (str[0] == 'b');
1557 else if (isdigit(str[0])) {
1558 get_option(&str, &tolerant);
1561 get_option(&str, &monarch_timeout);
1564 printk(KERN_INFO "mce argument %s ignored. Please use /sys\n",
1570 __setup("mce", mcheck_enable);
1577 * Disable machine checks on suspend and shutdown. We can't really handle
1580 static int mce_disable(void)
1584 for (i = 0; i < banks; i++) {
1585 if (!skip_bank_init(i))
1586 wrmsrl(MSR_IA32_MC0_CTL + i*4, 0);
1591 static int mce_suspend(struct sys_device *dev, pm_message_t state)
1593 return mce_disable();
1596 static int mce_shutdown(struct sys_device *dev)
1598 return mce_disable();
1602 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1603 * Only one CPU is active at this time, the others get re-added later using
1606 static int mce_resume(struct sys_device *dev)
1609 mce_cpu_features(¤t_cpu_data);
1614 static void mce_cpu_restart(void *data)
1616 del_timer_sync(&__get_cpu_var(mce_timer));
1617 if (!mce_available(¤t_cpu_data))
1623 /* Reinit MCEs after user configuration changes */
1624 static void mce_restart(void)
1626 on_each_cpu(mce_cpu_restart, NULL, 1);
1629 /* Toggle features for corrected errors */
1630 static void mce_disable_ce(void *all)
1632 if (!mce_available(¤t_cpu_data))
1635 del_timer_sync(&__get_cpu_var(mce_timer));
1639 static void mce_enable_ce(void *all)
1641 if (!mce_available(¤t_cpu_data))
1649 static struct sysdev_class mce_sysclass = {
1650 .suspend = mce_suspend,
1651 .shutdown = mce_shutdown,
1652 .resume = mce_resume,
1653 .name = "machinecheck",
1656 DEFINE_PER_CPU(struct sys_device, mce_dev);
1659 void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
1661 static struct sysdev_attribute *bank_attrs;
1663 static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr,
1666 u64 b = bank[attr - bank_attrs];
1668 return sprintf(buf, "%llx\n", b);
1671 static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr,
1672 const char *buf, size_t size)
1676 if (strict_strtoull(buf, 0, &new) < 0)
1679 bank[attr - bank_attrs] = new;
1686 show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf)
1688 strcpy(buf, mce_helper);
1690 return strlen(mce_helper) + 1;
1693 static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr,
1694 const char *buf, size_t siz)
1699 strncpy(mce_helper, buf, sizeof(mce_helper));
1700 mce_helper[sizeof(mce_helper)-1] = 0;
1701 len = strlen(mce_helper);
1702 p = strchr(mce_helper, '\n');
1710 static ssize_t set_ignore_ce(struct sys_device *s,
1711 struct sysdev_attribute *attr,
1712 const char *buf, size_t size)
1716 if (strict_strtoull(buf, 0, &new) < 0)
1719 if (mce_ignore_ce ^ !!new) {
1721 /* disable ce features */
1722 on_each_cpu(mce_disable_ce, (void *)1, 1);
1725 /* enable ce features */
1727 on_each_cpu(mce_enable_ce, (void *)1, 1);
1733 static ssize_t set_cmci_disabled(struct sys_device *s,
1734 struct sysdev_attribute *attr,
1735 const char *buf, size_t size)
1739 if (strict_strtoull(buf, 0, &new) < 0)
1742 if (mce_cmci_disabled ^ !!new) {
1745 on_each_cpu(mce_disable_ce, NULL, 1);
1746 mce_cmci_disabled = 1;
1749 mce_cmci_disabled = 0;
1750 on_each_cpu(mce_enable_ce, NULL, 1);
1756 static ssize_t store_int_with_restart(struct sys_device *s,
1757 struct sysdev_attribute *attr,
1758 const char *buf, size_t size)
1760 ssize_t ret = sysdev_store_int(s, attr, buf, size);
1765 static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger);
1766 static SYSDEV_INT_ATTR(tolerant, 0644, tolerant);
1767 static SYSDEV_INT_ATTR(monarch_timeout, 0644, monarch_timeout);
1768 static SYSDEV_INT_ATTR(dont_log_ce, 0644, mce_dont_log_ce);
1770 static struct sysdev_ext_attribute attr_check_interval = {
1771 _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int,
1772 store_int_with_restart),
1776 static struct sysdev_ext_attribute attr_ignore_ce = {
1777 _SYSDEV_ATTR(ignore_ce, 0644, sysdev_show_int, set_ignore_ce),
1781 static struct sysdev_ext_attribute attr_cmci_disabled = {
1782 _SYSDEV_ATTR(ignore_ce, 0644, sysdev_show_int, set_cmci_disabled),
1786 static struct sysdev_attribute *mce_attrs[] = {
1787 &attr_tolerant.attr,
1788 &attr_check_interval.attr,
1790 &attr_monarch_timeout.attr,
1791 &attr_dont_log_ce.attr,
1792 &attr_ignore_ce.attr,
1793 &attr_cmci_disabled.attr,
1797 static cpumask_var_t mce_dev_initialized;
1799 /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */
1800 static __cpuinit int mce_create_device(unsigned int cpu)
1805 if (!mce_available(&boot_cpu_data))
1808 memset(&per_cpu(mce_dev, cpu).kobj, 0, sizeof(struct kobject));
1809 per_cpu(mce_dev, cpu).id = cpu;
1810 per_cpu(mce_dev, cpu).cls = &mce_sysclass;
1812 err = sysdev_register(&per_cpu(mce_dev, cpu));
1816 for (i = 0; mce_attrs[i]; i++) {
1817 err = sysdev_create_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1821 for (i = 0; i < banks; i++) {
1822 err = sysdev_create_file(&per_cpu(mce_dev, cpu),
1827 cpumask_set_cpu(cpu, mce_dev_initialized);
1832 sysdev_remove_file(&per_cpu(mce_dev, cpu), &bank_attrs[i]);
1835 sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1837 sysdev_unregister(&per_cpu(mce_dev, cpu));
1842 static __cpuinit void mce_remove_device(unsigned int cpu)
1846 if (!cpumask_test_cpu(cpu, mce_dev_initialized))
1849 for (i = 0; mce_attrs[i]; i++)
1850 sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1852 for (i = 0; i < banks; i++)
1853 sysdev_remove_file(&per_cpu(mce_dev, cpu), &bank_attrs[i]);
1855 sysdev_unregister(&per_cpu(mce_dev, cpu));
1856 cpumask_clear_cpu(cpu, mce_dev_initialized);
1859 /* Make sure there are no machine checks on offlined CPUs. */
1860 static void mce_disable_cpu(void *h)
1862 unsigned long action = *(unsigned long *)h;
1865 if (!mce_available(¤t_cpu_data))
1867 if (!(action & CPU_TASKS_FROZEN))
1869 for (i = 0; i < banks; i++) {
1870 if (!skip_bank_init(i))
1871 wrmsrl(MSR_IA32_MC0_CTL + i*4, 0);
1875 static void mce_reenable_cpu(void *h)
1877 unsigned long action = *(unsigned long *)h;
1880 if (!mce_available(¤t_cpu_data))
1883 if (!(action & CPU_TASKS_FROZEN))
1885 for (i = 0; i < banks; i++) {
1886 if (!skip_bank_init(i))
1887 wrmsrl(MSR_IA32_MC0_CTL + i*4, bank[i]);
1891 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
1892 static int __cpuinit
1893 mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
1895 unsigned int cpu = (unsigned long)hcpu;
1896 struct timer_list *t = &per_cpu(mce_timer, cpu);
1900 case CPU_ONLINE_FROZEN:
1901 mce_create_device(cpu);
1902 if (threshold_cpu_callback)
1903 threshold_cpu_callback(action, cpu);
1906 case CPU_DEAD_FROZEN:
1907 if (threshold_cpu_callback)
1908 threshold_cpu_callback(action, cpu);
1909 mce_remove_device(cpu);
1911 case CPU_DOWN_PREPARE:
1912 case CPU_DOWN_PREPARE_FROZEN:
1914 smp_call_function_single(cpu, mce_disable_cpu, &action, 1);
1916 case CPU_DOWN_FAILED:
1917 case CPU_DOWN_FAILED_FROZEN:
1918 t->expires = round_jiffies(jiffies +
1919 __get_cpu_var(next_interval));
1920 add_timer_on(t, cpu);
1921 smp_call_function_single(cpu, mce_reenable_cpu, &action, 1);
1924 /* intentionally ignoring frozen here */
1925 cmci_rediscover(cpu);
1931 static struct notifier_block mce_cpu_notifier __cpuinitdata = {
1932 .notifier_call = mce_cpu_callback,
1935 static __init int mce_init_banks(void)
1939 bank_attrs = kzalloc(sizeof(struct sysdev_attribute) * banks,
1944 for (i = 0; i < banks; i++) {
1945 struct sysdev_attribute *a = &bank_attrs[i];
1947 a->attr.name = kasprintf(GFP_KERNEL, "bank%d", i);
1951 a->attr.mode = 0644;
1952 a->show = show_bank;
1953 a->store = set_bank;
1959 kfree(bank_attrs[i].attr.name);
1966 static __init int mce_init_device(void)
1971 if (!mce_available(&boot_cpu_data))
1974 alloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL);
1976 err = mce_init_banks();
1980 err = sysdev_class_register(&mce_sysclass);
1984 for_each_online_cpu(i) {
1985 err = mce_create_device(i);
1990 register_hotcpu_notifier(&mce_cpu_notifier);
1991 misc_register(&mce_log_device);
1996 device_initcall(mce_init_device);
1998 #else /* CONFIG_X86_OLD_MCE: */
2001 EXPORT_SYMBOL_GPL(nr_mce_banks); /* non-fatal.o */
2003 /* This has to be run for each processor */
2004 void mcheck_init(struct cpuinfo_x86 *c)
2006 if (mce_disabled == 1)
2009 switch (c->x86_vendor) {
2010 case X86_VENDOR_AMD:
2014 case X86_VENDOR_INTEL:
2016 intel_p5_mcheck_init(c);
2018 intel_p6_mcheck_init(c);
2020 intel_p4_mcheck_init(c);
2023 case X86_VENDOR_CENTAUR:
2025 winchip_mcheck_init(c);
2031 printk(KERN_INFO "mce: CPU supports %d MCE banks\n", nr_mce_banks);
2034 static int __init mcheck_enable(char *str)
2040 __setup("mce", mcheck_enable);
2042 #endif /* CONFIG_X86_OLD_MCE */
2045 * Old style boot options parsing. Only for compatibility.
2047 static int __init mcheck_disable(char *str)
2052 __setup("nomce", mcheck_disable);