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   1 #ifndef _ASM_X86_SYSTEM_H
   2 #define _ASM_X86_SYSTEM_H
   3
   4 #include <asm/asm.h>
   5 #include <asm/segment.h>
   6 #include <asm/cpufeature.h>
   7 #include <asm/cmpxchg.h>
   8 #include <asm/nops.h>
   9
  10 #include <linux/kernel.h>
  11 #include <linux/irqflags.h>
  12
  13 /* entries in ARCH_DLINFO: */
  14 #ifdef CONFIG_IA32_EMULATION
  15 # define AT_VECTOR_SIZE_ARCH 2
  16 #else
  17 # define AT_VECTOR_SIZE_ARCH 1
  18 #endif
  19
  20 struct task_struct; /* one of the stranger aspects of C forward declarations */
  21 struct task_struct *__switch_to(struct task_struct *prev,
  22                                 struct task_struct *next);
  23
  24 #ifdef CONFIG_X86_32
  25
  26 #ifdef CONFIG_CC_STACKPROTECTOR
  27 #define __switch_canary                                                 \
  28         "movl %P[task_canary](%[next]), %%ebx\n\t"                      \
  29         "movl %%ebx, "__percpu_arg([stack_canary])"\n\t"
  30 #define __switch_canary_oparam                                          \
  31         , [stack_canary] "=m" (per_cpu_var(stack_canary))
  32 #define __switch_canary_iparam                                          \
  33         , [task_canary] "i" (offsetof(struct task_struct, stack_canary))
  34 #else   /* CC_STACKPROTECTOR */
  35 #define __switch_canary
  36 #define __switch_canary_oparam
  37 #define __switch_canary_iparam
  38 #endif  /* CC_STACKPROTECTOR */
  39
  40 /*
  41  * Saving eflags is important. It switches not only IOPL between tasks,
  42  * it also protects other tasks from NT leaking through sysenter etc.
  43  */
  44 #define switch_to(prev, next, last)                                     \
  45 do {                                                                    \
  46         /*                                                              \
  47          * Context-switching clobbers all registers, so we clobber      \
  48          * them explicitly, via unused output variables.                \
  49          * (EAX and EBP is not listed because EBP is saved/restored     \
  50          * explicitly for wchan access and EAX is the return value of   \
  51          * __switch_to())                                               \
  52          */                                                             \
  53         unsigned long ebx, ecx, edx, esi, edi;                          \
  54                                                                         \
  55         asm volatile("pushfl\n\t"               /* save    flags */     \
  56                      "pushl %%ebp\n\t"          /* save    EBP   */     \
  57                      "movl %%esp,%[prev_sp]\n\t"        /* save    ESP   */ \
  58                      "movl %[next_sp],%%esp\n\t"        /* restore ESP   */ \
  59                      "movl $1f,%[prev_ip]\n\t"  /* save    EIP   */     \
  60                      "pushl %[next_ip]\n\t"     /* restore EIP   */     \
  61                      __switch_canary                                    \
  62                      "jmp __switch_to\n"        /* regparm call  */     \
  63                      "1:\t"                                             \
  64                      "popl %%ebp\n\t"           /* restore EBP   */     \
  65                      "popfl\n"                  /* restore flags */     \
  66                                                                         \
  67                      /* output parameters */                            \
  68                      : [prev_sp] "=m" (prev->thread.sp),                \
  69                        [prev_ip] "=m" (prev->thread.ip),                \
  70                        "=a" (last),                                     \
  71                                                                         \
  72                        /* clobbered output registers: */                \
  73                        "=b" (ebx), "=c" (ecx), "=d" (edx),              \
  74                        "=S" (esi), "=D" (edi)                           \
  75                                                                         \
  76                        __switch_canary_oparam                           \
  77                                                                         \
  78                        /* input parameters: */                          \
  79                      : [next_sp]  "m" (next->thread.sp),                \
  80                        [next_ip]  "m" (next->thread.ip),                \
  81                                                                         \
  82                        /* regparm parameters for __switch_to(): */      \
  83                        [prev]     "a" (prev),                           \
  84                        [next]     "d" (next)                            \
  85                                                                         \
  86                        __switch_canary_iparam                           \
  87                                                                         \
  88                      : /* reloaded segment registers */                 \
  89                         "memory");                                      \
  90 } while (0)
  91
  92 /*
  93  * disable hlt during certain critical i/o operations
  94  */
  95 #define HAVE_DISABLE_HLT
  96 #else
  97 #define __SAVE(reg, offset) "movq %%" #reg ",(14-" #offset ")*8(%%rsp)\n\t"
  98 #define __RESTORE(reg, offset) "movq (14-" #offset ")*8(%%rsp),%%" #reg "\n\t"
  99
 100 /* frame pointer must be last for get_wchan */
 101 #define SAVE_CONTEXT    "pushf ; pushq %%rbp ; movq %%rsi,%%rbp\n\t"
 102 #define RESTORE_CONTEXT "movq %%rbp,%%rsi ; popq %%rbp ; popf\t"
 103
 104 #define __EXTRA_CLOBBER  \
 105         , "rcx", "rbx", "rdx", "r8", "r9", "r10", "r11", \
 106           "r12", "r13", "r14", "r15"
 107
 108 #ifdef CONFIG_CC_STACKPROTECTOR
 109 #define __switch_canary                                                   \
 110         "movq %P[task_canary](%%rsi),%%r8\n\t"                            \
 111         "movq %%r8,"__percpu_arg([gs_canary])"\n\t"
 112 #define __switch_canary_oparam                                            \
 113         , [gs_canary] "=m" (per_cpu_var(irq_stack_union.stack_canary))
 114 #define __switch_canary_iparam                                            \
 115         , [task_canary] "i" (offsetof(struct task_struct, stack_canary))
 116 #else   /* CC_STACKPROTECTOR */
 117 #define __switch_canary
 118 #define __switch_canary_oparam
 119 #define __switch_canary_iparam
 120 #endif  /* CC_STACKPROTECTOR */
 121
 122 /* Save restore flags to clear handle leaking NT */
 123 #define switch_to(prev, next, last) \
 124         asm volatile(SAVE_CONTEXT                                         \
 125              "movq %%rsp,%P[threadrsp](%[prev])\n\t" /* save RSP */       \
 126              "movq %P[threadrsp](%[next]),%%rsp\n\t" /* restore RSP */    \
 127              "call __switch_to\n\t"                                       \
 128              ".globl thread_return\n"                                     \
 129              "thread_return:\n\t"                                         \
 130              "movq "__percpu_arg([current_task])",%%rsi\n\t"              \
 131              __switch_canary                                              \
 132              "movq %P[thread_info](%%rsi),%%r8\n\t"                       \
 133              LOCK_PREFIX "btr  %[tif_fork],%P[ti_flags](%%r8)\n\t"        \
 134              "movq %%rax,%%rdi\n\t"                                       \
 135              "jc   ret_from_fork\n\t"                                     \
 136              RESTORE_CONTEXT                                              \
 137              : "=a" (last)                                                \
 138                __switch_canary_oparam                                     \
 139              : [next] "S" (next), [prev] "D" (prev),                      \
 140                [threadrsp] "i" (offsetof(struct task_struct, thread.sp)), \
 141                [ti_flags] "i" (offsetof(struct thread_info, flags)),      \
 142                [tif_fork] "i" (TIF_FORK),                                 \
 143                [thread_info] "i" (offsetof(struct task_struct, stack)),   \
 144                [current_task] "m" (per_cpu_var(current_task))             \
 145                __switch_canary_iparam                                     \
 146              : "memory", "cc" __EXTRA_CLOBBER)
 147 #endif
 148
 149 #ifdef __KERNEL__
 150 #define _set_base(addr, base) do { unsigned long __pr; \
 151 __asm__ __volatile__ ("movw %%dx,%1\n\t" \
 152         "rorl $16,%%edx\n\t" \
 153         "movb %%dl,%2\n\t" \
 154         "movb %%dh,%3" \
 155         :"=&d" (__pr) \
 156         :"m" (*((addr)+2)), \
 157          "m" (*((addr)+4)), \
 158          "m" (*((addr)+7)), \
 159          "0" (base) \
 160         ); } while (0)
 161
 162 #define _set_limit(addr, limit) do { unsigned long __lr; \
 163 __asm__ __volatile__ ("movw %%dx,%1\n\t" \
 164         "rorl $16,%%edx\n\t" \
 165         "movb %2,%%dh\n\t" \
 166         "andb $0xf0,%%dh\n\t" \
 167         "orb %%dh,%%dl\n\t" \
 168         "movb %%dl,%2" \
 169         :"=&d" (__lr) \
 170         :"m" (*(addr)), \
 171          "m" (*((addr)+6)), \
 172          "0" (limit) \
 173         ); } while (0)
 174
 175 #define set_base(ldt, base) _set_base(((char *)&(ldt)) , (base))
 176 #define set_limit(ldt, limit) _set_limit(((char *)&(ldt)) , ((limit)-1))
 177
 178 extern void native_load_gs_index(unsigned);
 179
 180 /*
 181  * Load a segment. Fall back on loading the zero
 182  * segment if something goes wrong..
 183  */
 184 #define loadsegment(seg, value)                 \
 185         asm volatile("\n"                       \
 186                      "1:\t"                     \
 187                      "movl %k0,%%" #seg "\n"    \
 188                      "2:\n"                     \
 189                      ".section .fixup,\"ax\"\n" \
 190                      "3:\t"                     \
 191                      "movl %k1, %%" #seg "\n\t" \
 192                      "jmp 2b\n"                 \
 193                      ".previous\n"              \
 194                      _ASM_EXTABLE(1b,3b)        \
 195                      : :"r" (value), "r" (0) : "memory")
 196
 197
 198 /*
 199  * Save a segment register away
 200  */
 201 #define savesegment(seg, value)                         \
 202         asm("mov %%" #seg ",%0":"=r" (value) : : "memory")
 203
 204 /*
 205  * x86_32 user gs accessors.
 206  */
 207 #ifdef CONFIG_X86_32
 208 #ifdef CONFIG_X86_32_LAZY_GS
 209 #define get_user_gs(regs)       (u16)({unsigned long v; savesegment(gs, v); v;})
 210 #define set_user_gs(regs, v)    loadsegment(gs, (unsigned long)(v))
 211 #define task_user_gs(tsk)       ((tsk)->thread.gs)
 212 #define lazy_save_gs(v)         savesegment(gs, (v))
 213 #define lazy_load_gs(v)         loadsegment(gs, (v))
 214 #else   /* X86_32_LAZY_GS */
 215 #define get_user_gs(regs)       (u16)((regs)->gs)
 216 #define set_user_gs(regs, v)    do { (regs)->gs = (v); } while (0)
 217 #define task_user_gs(tsk)       (task_pt_regs(tsk)->gs)
 218 #define lazy_save_gs(v)         do { } while (0)
 219 #define lazy_load_gs(v)         do { } while (0)
 220 #endif  /* X86_32_LAZY_GS */
 221 #endif  /* X86_32 */
 222
 223 static inline unsigned long get_limit(unsigned long segment)
 224 {
 225         unsigned long __limit;
 226         asm("lsll %1,%0" : "=r" (__limit) : "r" (segment));
 227         return __limit + 1;
 228 }
 229
 230 static inline void native_clts(void)
 231 {
 232         asm volatile("clts");
 233 }
 234
 235 /*
 236  * Volatile isn't enough to prevent the compiler from reordering the
 237  * read/write functions for the control registers and messing everything up.
 238  * A memory clobber would solve the problem, but would prevent reordering of
 239  * all loads stores around it, which can hurt performance. Solution is to
 240  * use a variable and mimic reads and writes to it to enforce serialization
 241  */
 242 static unsigned long __force_order;
 243
 244 static inline unsigned long native_read_cr0(void)
 245 {
 246         unsigned long val;
 247         asm volatile("mov %%cr0,%0\n\t" : "=r" (val), "=m" (__force_order));
 248         return val;
 249 }
 250
 251 static inline void native_write_cr0(unsigned long val)
 252 {
 253         asm volatile("mov %0,%%cr0": : "r" (val), "m" (__force_order));
 254 }
 255
 256 static inline unsigned long native_read_cr2(void)
 257 {
 258         unsigned long val;
 259         asm volatile("mov %%cr2,%0\n\t" : "=r" (val), "=m" (__force_order));
 260         return val;
 261 }
 262
 263 static inline void native_write_cr2(unsigned long val)
 264 {
 265         asm volatile("mov %0,%%cr2": : "r" (val), "m" (__force_order));
 266 }
 267
 268 static inline unsigned long native_read_cr3(void)
 269 {
 270         unsigned long val;
 271         asm volatile("mov %%cr3,%0\n\t" : "=r" (val), "=m" (__force_order));
 272         return val;
 273 }
 274
 275 static inline void native_write_cr3(unsigned long val)
 276 {
 277         asm volatile("mov %0,%%cr3": : "r" (val), "m" (__force_order));
 278 }
 279
 280 static inline unsigned long native_read_cr4(void)
 281 {
 282         unsigned long val;
 283         asm volatile("mov %%cr4,%0\n\t" : "=r" (val), "=m" (__force_order));
 284         return val;
 285 }
 286
 287 static inline unsigned long native_read_cr4_safe(void)
 288 {
 289         unsigned long val;
 290         /* This could fault if %cr4 does not exist. In x86_64, a cr4 always
 291          * exists, so it will never fail. */
 292 #ifdef CONFIG_X86_32
 293         asm volatile("1: mov %%cr4, %0\n"
 294                      "2:\n"
 295                      _ASM_EXTABLE(1b, 2b)
 296                      : "=r" (val), "=m" (__force_order) : "0" (0));
 297 #else
 298         val = native_read_cr4();
 299 #endif
 300         return val;
 301 }
 302
 303 static inline void native_write_cr4(unsigned long val)
 304 {
 305         asm volatile("mov %0,%%cr4": : "r" (val), "m" (__force_order));
 306 }
 307
 308 #ifdef CONFIG_X86_64
 309 static inline unsigned long native_read_cr8(void)
 310 {
 311         unsigned long cr8;
 312         asm volatile("movq %%cr8,%0" : "=r" (cr8));
 313         return cr8;
 314 }
 315
 316 static inline void native_write_cr8(unsigned long val)
 317 {
 318         asm volatile("movq %0,%%cr8" :: "r" (val) : "memory");
 319 }
 320 #endif
 321
 322 static inline void native_wbinvd(void)
 323 {
 324         asm volatile("wbinvd": : :"memory");
 325 }
 326
 327 #ifdef CONFIG_PARAVIRT
 328 #include <asm/paravirt.h>
 329 #else
 330 #define read_cr0()      (native_read_cr0())
 331 #define write_cr0(x)    (native_write_cr0(x))
 332 #define read_cr2()      (native_read_cr2())
 333 #define write_cr2(x)    (native_write_cr2(x))
 334 #define read_cr3()      (native_read_cr3())
 335 #define write_cr3(x)    (native_write_cr3(x))
 336 #define read_cr4()      (native_read_cr4())
 337 #define read_cr4_safe() (native_read_cr4_safe())
 338 #define write_cr4(x)    (native_write_cr4(x))
 339 #define wbinvd()        (native_wbinvd())
 340 #ifdef CONFIG_X86_64
 341 #define read_cr8()      (native_read_cr8())
 342 #define write_cr8(x)    (native_write_cr8(x))
 343 #define load_gs_index   native_load_gs_index
 344 #endif
 345
 346 /* Clear the 'TS' bit */
 347 #define clts()          (native_clts())
 348
 349 #endif/* CONFIG_PARAVIRT */
 350
 351 #define stts() write_cr0(read_cr0() | X86_CR0_TS)
 352
 353 #endif /* __KERNEL__ */
 354
 355 static inline void clflush(volatile void *__p)
 356 {
 357         asm volatile("clflush %0" : "+m" (*(volatile char __force *)__p));
 358 }
 359
 360 #define nop() asm volatile ("nop")
 361
 362 void disable_hlt(void);
 363 void enable_hlt(void);
 364
 365 void cpu_idle_wait(void);
 366
 367 extern unsigned long arch_align_stack(unsigned long sp);
 368 extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
 369
 370 void default_idle(void);
 371
 372 void stop_this_cpu(void *dummy);
 373
 374 /*
 375  * Force strict CPU ordering.
 376  * And yes, this is required on UP too when we're talking
 377  * to devices.
 378  */
 379 #ifdef CONFIG_X86_32
 380 /*
 381  * Some non-Intel clones support out of order store. wmb() ceases to be a
 382  * nop for these.
 383  */
 384 #define mb() alternative("lock; addl $0,0(%%esp)", "mfence", X86_FEATURE_XMM2)
 385 #define rmb() alternative("lock; addl $0,0(%%esp)", "lfence", X86_FEATURE_XMM2)
 386 #define wmb() alternative("lock; addl $0,0(%%esp)", "sfence", X86_FEATURE_XMM)
 387 #else
 388 #define mb()    asm volatile("mfence":::"memory")
 389 #define rmb()   asm volatile("lfence":::"memory")
 390 #define wmb()   asm volatile("sfence" ::: "memory")
 391 #endif
 392
 393 /**
 394  * read_barrier_depends - Flush all pending reads that subsequents reads
 395  * depend on.
 396  *
 397  * No data-dependent reads from memory-like regions are ever reordered
 398  * over this barrier.  All reads preceding this primitive are guaranteed
 399  * to access memory (but not necessarily other CPUs' caches) before any
 400  * reads following this primitive that depend on the data return by
 401  * any of the preceding reads.  This primitive is much lighter weight than
 402  * rmb() on most CPUs, and is never heavier weight than is
 403  * rmb().
 404  *
 405  * These ordering constraints are respected by both the local CPU
 406  * and the compiler.
 407  *
 408  * Ordering is not guaranteed by anything other than these primitives,
 409  * not even by data dependencies.  See the documentation for
 410  * memory_barrier() for examples and URLs to more information.
 411  *
 412  * For example, the following code would force ordering (the initial
 413  * value of "a" is zero, "b" is one, and "p" is "&a"):
 414  *
 415  * <programlisting>
 416  *      CPU 0                           CPU 1
 417  *
 418  *      b = 2;
 419  *      memory_barrier();
 420  *      p = &b;                         q = p;
 421  *                                      read_barrier_depends();
 422  *                                      d = *q;
 423  * </programlisting>
 424  *
 425  * because the read of "*q" depends on the read of "p" and these
 426  * two reads are separated by a read_barrier_depends().  However,
 427  * the following code, with the same initial values for "a" and "b":
 428  *
 429  * <programlisting>
 430  *      CPU 0                           CPU 1
 431  *
 432  *      a = 2;
 433  *      memory_barrier();
 434  *      b = 3;                          y = b;
 435  *                                      read_barrier_depends();
 436  *                                      x = a;
 437  * </programlisting>
 438  *
 439  * does not enforce ordering, since there is no data dependency between
 440  * the read of "a" and the read of "b".  Therefore, on some CPUs, such
 441  * as Alpha, "y" could be set to 3 and "x" to 0.  Use rmb()
 442  * in cases like this where there are no data dependencies.
 443  **/
 444
 445 #define read_barrier_depends()  do { } while (0)
 446
 447 #ifdef CONFIG_SMP
 448 #define smp_mb()        mb()
 449 #ifdef CONFIG_X86_PPRO_FENCE
 450 # define smp_rmb()      rmb()
 451 #else
 452 # define smp_rmb()      barrier()
 453 #endif
 454 #ifdef CONFIG_X86_OOSTORE
 455 # define smp_wmb()      wmb()
 456 #else
 457 # define smp_wmb()      barrier()
 458 #endif
 459 #define smp_read_barrier_depends()      read_barrier_depends()
 460 #define set_mb(var, value) do { (void)xchg(&var, value); } while (0)
 461 #else
 462 #define smp_mb()        barrier()
 463 #define smp_rmb()       barrier()
 464 #define smp_wmb()       barrier()
 465 #define smp_read_barrier_depends()      do { } while (0)
 466 #define set_mb(var, value) do { var = value; barrier(); } while (0)
 467 #endif
 468
 469 /*
 470  * Stop RDTSC speculation. This is needed when you need to use RDTSC
 471  * (or get_cycles or vread that possibly accesses the TSC) in a defined
 472  * code region.
 473  *
 474  * (Could use an alternative three way for this if there was one.)
 475  */
 476 static inline void rdtsc_barrier(void)
 477 {
 478         alternative(ASM_NOP3, "mfence", X86_FEATURE_MFENCE_RDTSC);
 479         alternative(ASM_NOP3, "lfence", X86_FEATURE_LFENCE_RDTSC);
 480 }
 481
 482 #endif /* _ASM_X86_SYSTEM_H */