5 * KVM x86 specific structures and definitions
9 #include <linux/types.h>
10 #include <linux/ioctl.h>
12 /* Select x86 specific features in <linux/kvm.h> */
13 #define __KVM_HAVE_PIT
14 #define __KVM_HAVE_IOAPIC
15 #define __KVM_HAVE_DEVICE_ASSIGNMENT
16 #define __KVM_HAVE_MSI
17 #define __KVM_HAVE_USER_NMI
18 #define __KVM_HAVE_GUEST_DEBUG
19 #define __KVM_HAVE_MSIX
20 #define __KVM_HAVE_MCE
21 #define __KVM_HAVE_PIT_STATE2
22 #define __KVM_HAVE_XEN_HVM
24 /* Architectural interrupt line count. */
25 #define KVM_NR_INTERRUPTS 256
27 struct kvm_memory_alias {
28 __u32 slot; /* this has a different namespace than memory slots */
30 __u64 guest_phys_addr;
32 __u64 target_phys_addr;
35 /* for KVM_GET_IRQCHIP and KVM_SET_IRQCHIP */
36 struct kvm_pic_state {
37 __u8 last_irr; /* edge detection */
38 __u8 irr; /* interrupt request register */
39 __u8 imr; /* interrupt mask register */
40 __u8 isr; /* interrupt service register */
41 __u8 priority_add; /* highest irq priority */
48 __u8 rotate_on_auto_eoi;
49 __u8 special_fully_nested_mode;
50 __u8 init4; /* true if 4 byte init */
51 __u8 elcr; /* PIIX edge/trigger selection */
55 #define KVM_IOAPIC_NUM_PINS 24
56 struct kvm_ioapic_state {
68 __u8 delivery_status:1;
77 } redirtbl[KVM_IOAPIC_NUM_PINS];
80 #define KVM_IRQCHIP_PIC_MASTER 0
81 #define KVM_IRQCHIP_PIC_SLAVE 1
82 #define KVM_IRQCHIP_IOAPIC 2
83 #define KVM_NR_IRQCHIPS 3
85 /* for KVM_GET_REGS and KVM_SET_REGS */
87 /* out (KVM_GET_REGS) / in (KVM_SET_REGS) */
88 __u64 rax, rbx, rcx, rdx;
89 __u64 rsi, rdi, rsp, rbp;
90 __u64 r8, r9, r10, r11;
91 __u64 r12, r13, r14, r15;
95 /* for KVM_GET_LAPIC and KVM_SET_LAPIC */
96 #define KVM_APIC_REG_SIZE 0x400
97 struct kvm_lapic_state {
98 char regs[KVM_APIC_REG_SIZE];
106 __u8 present, dpl, db, s, l, g, avl;
118 /* for KVM_GET_SREGS and KVM_SET_SREGS */
120 /* out (KVM_GET_SREGS) / in (KVM_SET_SREGS) */
121 struct kvm_segment cs, ds, es, fs, gs, ss;
122 struct kvm_segment tr, ldt;
123 struct kvm_dtable gdt, idt;
124 __u64 cr0, cr2, cr3, cr4, cr8;
127 __u64 interrupt_bitmap[(KVM_NR_INTERRUPTS + 63) / 64];
130 /* for KVM_GET_FPU and KVM_SET_FPU */
135 __u8 ftwx; /* in fxsave format */
145 struct kvm_msr_entry {
151 /* for KVM_GET_MSRS and KVM_SET_MSRS */
153 __u32 nmsrs; /* number of msrs in entries */
156 struct kvm_msr_entry entries[0];
159 /* for KVM_GET_MSR_INDEX_LIST */
160 struct kvm_msr_list {
161 __u32 nmsrs; /* number of msrs in entries */
166 struct kvm_cpuid_entry {
175 /* for KVM_SET_CPUID */
179 struct kvm_cpuid_entry entries[0];
182 struct kvm_cpuid_entry2 {
193 #define KVM_CPUID_FLAG_SIGNIFCANT_INDEX 1
194 #define KVM_CPUID_FLAG_STATEFUL_FUNC 2
195 #define KVM_CPUID_FLAG_STATE_READ_NEXT 4
197 /* for KVM_SET_CPUID2 */
201 struct kvm_cpuid_entry2 entries[0];
204 /* for KVM_GET_PIT and KVM_SET_PIT */
205 struct kvm_pit_channel_state {
206 __u32 count; /* can be 65536 */
218 __s64 count_load_time;
221 struct kvm_debug_exit_arch {
229 #define KVM_GUESTDBG_USE_SW_BP 0x00010000
230 #define KVM_GUESTDBG_USE_HW_BP 0x00020000
231 #define KVM_GUESTDBG_INJECT_DB 0x00040000
232 #define KVM_GUESTDBG_INJECT_BP 0x00080000
234 /* for KVM_SET_GUEST_DEBUG */
235 struct kvm_guest_debug_arch {
239 struct kvm_pit_state {
240 struct kvm_pit_channel_state channels[3];
243 #define KVM_PIT_FLAGS_HPET_LEGACY 0x00000001
245 struct kvm_pit_state2 {
246 struct kvm_pit_channel_state channels[3];
251 struct kvm_reinject_control {
255 #endif /* _ASM_X86_KVM_H */