2 * arch/sparc/kernel/sun4c_irq.c:
4 * djhr: Hacked out of irq.c into a CPU dependent version.
6 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
7 * Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx)
8 * Copyright (C) 1995 Pete A. Zaitcev (zaitcev@yahoo.com)
9 * Copyright (C) 1996 Dave Redman (djhr@tadpole.co.uk)
12 #include <linux/errno.h>
13 #include <linux/linkage.h>
14 #include <linux/kernel_stat.h>
15 #include <linux/signal.h>
16 #include <linux/sched.h>
17 #include <linux/ptrace.h>
18 #include <linux/interrupt.h>
19 #include <linux/slab.h>
20 #include <linux/init.h>
22 #include <linux/of_device.h>
25 #include <asm/ptrace.h>
26 #include <asm/processor.h>
27 #include <asm/system.h>
29 #include <asm/vaddrs.h>
30 #include <asm/timer.h>
31 #include <asm/openprom.h>
32 #include <asm/oplib.h>
33 #include <asm/traps.h>
36 #include <asm/idprom.h>
37 #include <asm/machines.h>
40 * Bit field defines for the interrupt registers on various
44 /* The sun4c interrupt register. */
45 #define SUN4C_INT_ENABLE 0x01 /* Allow interrupts. */
46 #define SUN4C_INT_E14 0x80 /* Enable level 14 IRQ. */
47 #define SUN4C_INT_E10 0x20 /* Enable level 10 IRQ. */
48 #define SUN4C_INT_E8 0x10 /* Enable level 8 IRQ. */
49 #define SUN4C_INT_E6 0x08 /* Enable level 6 IRQ. */
50 #define SUN4C_INT_E4 0x04 /* Enable level 4 IRQ. */
51 #define SUN4C_INT_E1 0x02 /* Enable level 1 IRQ. */
53 /* Pointer to the interrupt enable byte
55 * Dave Redman (djhr@tadpole.co.uk)
56 * What you may not be aware of is that entry.S requires this variable.
58 * --- linux_trap_nmi_sun4c --
60 * so don't go making it static, like I tried. sigh.
62 unsigned char *interrupt_enable = NULL;
64 static void sun4c_disable_irq(unsigned int irq_nr)
67 unsigned char current_mask, new_mask;
69 local_irq_save(flags);
70 irq_nr &= (NR_IRQS - 1);
71 current_mask = *interrupt_enable;
74 new_mask = ((current_mask) & (~(SUN4C_INT_E1)));
77 new_mask = ((current_mask) & (~(SUN4C_INT_E8)));
80 new_mask = ((current_mask) & (~(SUN4C_INT_E10)));
83 new_mask = ((current_mask) & (~(SUN4C_INT_E14)));
86 local_irq_restore(flags);
89 *interrupt_enable = new_mask;
90 local_irq_restore(flags);
93 static void sun4c_enable_irq(unsigned int irq_nr)
96 unsigned char current_mask, new_mask;
98 local_irq_save(flags);
99 irq_nr &= (NR_IRQS - 1);
100 current_mask = *interrupt_enable;
103 new_mask = ((current_mask) | SUN4C_INT_E1);
106 new_mask = ((current_mask) | SUN4C_INT_E8);
109 new_mask = ((current_mask) | SUN4C_INT_E10);
112 new_mask = ((current_mask) | SUN4C_INT_E14);
115 local_irq_restore(flags);
118 *interrupt_enable = new_mask;
119 local_irq_restore(flags);
122 #define TIMER_IRQ 10 /* Also at level 14, but we ignore that one. */
123 #define PROFILE_IRQ 14 /* Level14 ticker.. used by OBP for polling */
125 volatile struct sun4c_timer_info *sun4c_timers;
127 static void sun4c_clear_clock_irq(void)
129 volatile unsigned int clear_intr;
131 clear_intr = sun4c_timers->timer_limit10;
134 static void sun4c_clear_profile_irq(int cpu)
136 /* Errm.. not sure how to do this.. */
139 static void sun4c_load_profile_irq(int cpu, unsigned int limit)
141 /* Errm.. not sure how to do this.. */
144 static void __init sun4c_init_timers(irq_handler_t counter_fn)
148 /* Map the Timer chip, this is implemented in hardware inside
149 * the cache chip on the sun4c.
151 sun4c_timers = ioremap(SUN_TIMER_PHYSADDR,
152 sizeof(struct sun4c_timer_info));
154 /* Have the level 10 timer tick at 100HZ. We don't touch the
155 * level 14 timer limit since we are letting the prom handle
156 * them until we have a real console driver so L1-A works.
158 sun4c_timers->timer_limit10 = (((1000000/HZ) + 1) << 10);
159 master_l10_counter = &sun4c_timers->cur_count10;
160 master_l10_limit = &sun4c_timers->timer_limit10;
162 irq = request_irq(TIMER_IRQ,
164 (IRQF_DISABLED | SA_STATIC_ALLOC),
167 prom_printf("time_init: unable to attach IRQ%d\n",TIMER_IRQ);
171 claim_ticker14(NULL, PROFILE_IRQ, 0);
175 static void sun4c_nop(void) {}
178 void __init sun4c_init_IRQ(void)
180 struct linux_prom_registers int_regs[2];
182 struct resource phyres;
184 ie_node = prom_searchsiblings (prom_getchild(prom_root_node),
187 panic("Cannot find /interrupt-enable node");
189 /* Depending on the "address" property is bad news... */
190 interrupt_enable = NULL;
191 if (prom_getproperty(ie_node, "reg", (char *) int_regs,
192 sizeof(int_regs)) != -1) {
193 memset(&phyres, 0, sizeof(struct resource));
194 phyres.flags = int_regs[0].which_io;
195 phyres.start = int_regs[0].phys_addr;
196 interrupt_enable = (char *) of_ioremap(&phyres, 0,
197 int_regs[0].reg_size, "sun4c_intr");
199 if (!interrupt_enable)
200 panic("Cannot map interrupt_enable");
202 BTFIXUPSET_CALL(enable_irq, sun4c_enable_irq, BTFIXUPCALL_NORM);
203 BTFIXUPSET_CALL(disable_irq, sun4c_disable_irq, BTFIXUPCALL_NORM);
204 BTFIXUPSET_CALL(enable_pil_irq, sun4c_enable_irq, BTFIXUPCALL_NORM);
205 BTFIXUPSET_CALL(disable_pil_irq, sun4c_disable_irq, BTFIXUPCALL_NORM);
206 BTFIXUPSET_CALL(clear_clock_irq, sun4c_clear_clock_irq, BTFIXUPCALL_NORM);
207 BTFIXUPSET_CALL(clear_profile_irq, sun4c_clear_profile_irq, BTFIXUPCALL_NOP);
208 BTFIXUPSET_CALL(load_profile_irq, sun4c_load_profile_irq, BTFIXUPCALL_NOP);
209 sparc_init_timers = sun4c_init_timers;
211 BTFIXUPSET_CALL(set_cpu_int, sun4c_nop, BTFIXUPCALL_NOP);
212 BTFIXUPSET_CALL(clear_cpu_int, sun4c_nop, BTFIXUPCALL_NOP);
213 BTFIXUPSET_CALL(set_irq_udt, sun4c_nop, BTFIXUPCALL_NOP);
215 *interrupt_enable = (SUN4C_INT_ENABLE);
216 /* Cannot enable interrupts until OBP ticker is disabled. */