1 menu "Memory management options"
7 bool "Support for memory management hardware"
11 Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
12 boot on these systems, this option must not be set.
14 On other systems (such as the SH-3 and 4) where an MMU exists,
15 turning this off will boot the kernel on these machines with the
16 MMU implicitly switched off.
20 default "0x80000000" if MMU && SUPERH32
21 default "0x20000000" if MMU && SUPERH64
24 config FORCE_MAX_ZONEORDER
25 int "Maximum zone order"
26 range 9 64 if PAGE_SIZE_16KB
27 default "9" if PAGE_SIZE_16KB
28 range 7 64 if PAGE_SIZE_64KB
29 default "7" if PAGE_SIZE_64KB
34 The kernel memory allocator divides physically contiguous memory
35 blocks into "zones", where each zone is a power of two number of
36 pages. This option selects the largest power of two that the kernel
37 keeps in the memory allocator. If you need to allocate very large
38 blocks of physically contiguous memory, then you may need to
41 This config option is actually maximum order plus one. For example,
42 a value of 11 means that the largest free memory block is 2^10 pages.
44 The page size is not necessarily 4KB. Keep this in mind when
45 choosing a value for this option.
48 hex "Physical memory start address"
51 Computers built with Hitachi SuperH processors always
52 map the ROM starting at address zero. But the processor
53 does not specify the range that RAM takes.
55 The physical memory (RAM) start address will be automatically
56 set to 08000000. Other platforms, such as the Solution Engine
57 boards typically map RAM at 0C000000.
59 Tweak this only when porting to a new machine which does not
60 already have a defconfig. Changing it from the known correct
61 value on any of the known systems will only lead to disaster.
64 hex "Physical memory size"
67 This sets the default memory size assumed by your SH kernel. It can
68 be overridden as normal by the 'mem=' argument on the kernel command
69 line. If unsure, consult your board specifications or just leave it
70 as 0x04000000 which was the default value before this became
73 # Physical addressing modes
84 bool "Support 32-bit physical addressing through PMB"
85 depends on MMU && EXPERIMENTAL && CPU_SH4A && !CPU_SH4AL_DSP
88 If you say Y here, physical addressing will be extended to
89 32-bits through the SH-4A PMB. If this is not set, legacy
90 29-bit physical addressing will be used.
93 bool "Support legacy boot mappings for PMB"
97 If this option is enabled, fixed PMB mappings are inherited
98 from the boot loader, and the kernel does not attempt dynamic
99 management. This is the closest to legacy 29-bit physical mode,
100 and allows systems to support up to 512MiB of system memory.
104 depends on (CPU_SHX2 || CPU_SHX3) && MMU
107 bool "Support vsyscall page"
108 depends on MMU && (CPU_SH3 || CPU_SH4)
111 This will enable support for the kernel mapping a vDSO page
112 in process space, and subsequently handing down the entry point
113 to the libc through the ELF auxiliary vector.
115 From the kernel side this is used for the signal trampoline.
116 For systems with an MMU that can afford to give up a page,
117 (the default value) say Y.
120 bool "Non Uniform Memory Access (NUMA) Support"
121 depends on MMU && SYS_SUPPORTS_NUMA && EXPERIMENTAL
124 Some SH systems have many various memories scattered around
125 the address space, each with varying latencies. This enables
126 support for these blocks by binding them to nodes and allowing
127 memory policies to be used for prioritizing and controlling
128 allocation behaviour.
132 default "3" if CPU_SUBTYPE_SHX3
134 depends on NEED_MULTIPLE_NODES
136 config ARCH_FLATMEM_ENABLE
140 config ARCH_SPARSEMEM_ENABLE
142 select SPARSEMEM_STATIC
144 config ARCH_SPARSEMEM_DEFAULT
147 config MAX_ACTIVE_REGIONS
149 default "6" if (CPU_SUBTYPE_SHX3 && SPARSEMEM)
150 default "2" if SPARSEMEM && (CPU_SUBTYPE_SH7722 || \
154 config ARCH_POPULATES_NODE_MAP
157 config ARCH_SELECT_MEMORY_MODEL
160 config ARCH_ENABLE_MEMORY_HOTPLUG
162 depends on SPARSEMEM && MMU
164 config ARCH_ENABLE_MEMORY_HOTREMOVE
166 depends on SPARSEMEM && MMU
168 config ARCH_MEMORY_PROBE
170 depends on MEMORY_HOTPLUG
174 depends on X2TLB || SUPERH64
177 prompt "Kernel page size"
178 default PAGE_SIZE_4KB
183 This is the default page size used by all SuperH CPUs.
187 depends on !MMU || X2TLB
189 This enables 8kB pages as supported by SH-X2 and later MMUs.
191 config PAGE_SIZE_16KB
195 This enables 16kB pages on MMU-less SH systems.
197 config PAGE_SIZE_64KB
199 depends on !MMU || CPU_SH4 || CPU_SH5
201 This enables support for 64kB pages, possible on all SH-4
207 prompt "HugeTLB page size"
208 depends on HUGETLB_PAGE
209 default HUGETLB_PAGE_SIZE_1MB if PAGE_SIZE_64KB
210 default HUGETLB_PAGE_SIZE_64K
212 config HUGETLB_PAGE_SIZE_64K
214 depends on !PAGE_SIZE_64KB
216 config HUGETLB_PAGE_SIZE_256K
220 config HUGETLB_PAGE_SIZE_1MB
223 config HUGETLB_PAGE_SIZE_4MB
227 config HUGETLB_PAGE_SIZE_64MB
231 config HUGETLB_PAGE_SIZE_512MB
240 bool "Multi-core scheduler support"
244 Multi-core scheduler support improves the CPU scheduler's decision
245 making when dealing with multi-core CPU chips at a cost of slightly
246 increased overhead in some places. If unsure say N here.
250 menu "Cache configuration"
252 config SH7705_CACHE_32KB
253 bool "Enable 32KB cache size for SH7705"
254 depends on CPU_SUBTYPE_SH7705
259 default CACHE_WRITEBACK if CPU_SH2A || CPU_SH3 || CPU_SH4 || CPU_SH5
260 default CACHE_WRITETHROUGH if (CPU_SH2 && !CPU_SH2A)
262 config CACHE_WRITEBACK
265 config CACHE_WRITETHROUGH
268 Selecting this option will configure the caches in write-through
269 mode, as opposed to the default write-back configuration.
271 Since there's sill some aliasing issues on SH-4, this option will
272 unfortunately still require the majority of flushing functions to
273 be implemented to deal with aliasing.