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   1 /*
   2  * 'traps.c' handles hardware traps and faults after we have saved some
   3  * state in 'entry.S'.
   4  *
   5  *  SuperH version: Copyright (C) 1999 Niibe Yutaka
   6  *                  Copyright (C) 2000 Philipp Rumpf
   7  *                  Copyright (C) 2000 David Howells
   8  *                  Copyright (C) 2002 - 2007 Paul Mundt
   9  *
  10  * This file is subject to the terms and conditions of the GNU General Public
  11  * License.  See the file "COPYING" in the main directory of this archive
  12  * for more details.
  13  */
  14 #include <linux/kernel.h>
  15 #include <linux/ptrace.h>
  16 #include <linux/init.h>
  17 #include <linux/spinlock.h>
  18 #include <linux/module.h>
  19 #include <linux/kallsyms.h>
  20 #include <linux/io.h>
  21 #include <linux/bug.h>
  22 #include <linux/debug_locks.h>
  23 #include <linux/kdebug.h>
  24 #include <linux/kexec.h>
  25 #include <linux/limits.h>
  26 #include <asm/system.h>
  27 #include <asm/uaccess.h>
  28 #include <asm/fpu.h>
  29
  30 #ifdef CONFIG_SH_KGDB
  31 #include <asm/kgdb.h>
  32 #define CHK_REMOTE_DEBUG(regs)                  \
  33 {                                               \
  34         if (kgdb_debug_hook && !user_mode(regs))\
  35                 (*kgdb_debug_hook)(regs);       \
  36 }
  37 #else
  38 #define CHK_REMOTE_DEBUG(regs)
  39 #endif
  40
  41 #ifdef CONFIG_CPU_SH2
  42 # define TRAP_RESERVED_INST     4
  43 # define TRAP_ILLEGAL_SLOT_INST 6
  44 # define TRAP_ADDRESS_ERROR     9
  45 # ifdef CONFIG_CPU_SH2A
  46 #  define TRAP_DIVZERO_ERROR    17
  47 #  define TRAP_DIVOVF_ERROR     18
  48 # endif
  49 #else
  50 #define TRAP_RESERVED_INST      12
  51 #define TRAP_ILLEGAL_SLOT_INST  13
  52 #endif
  53
  54 static void dump_mem(const char *str, unsigned long bottom, unsigned long top)
  55 {
  56         unsigned long p;
  57         int i;
  58
  59         printk("%s(0x%08lx to 0x%08lx)\n", str, bottom, top);
  60
  61         for (p = bottom & ~31; p < top; ) {
  62                 printk("%04lx: ", p & 0xffff);
  63
  64                 for (i = 0; i < 8; i++, p += 4) {
  65                         unsigned int val;
  66
  67                         if (p < bottom || p >= top)
  68                                 printk("         ");
  69                         else {
  70                                 if (__get_user(val, (unsigned int __user *)p)) {
  71                                         printk("\n");
  72                                         return;
  73                                 }
  74                                 printk("%08x ", val);
  75                         }
  76                 }
  77                 printk("\n");
  78         }
  79 }
  80
  81 static DEFINE_SPINLOCK(die_lock);
  82
  83 void die(const char * str, struct pt_regs * regs, long err)
  84 {
  85         static int die_counter;
  86
  87         oops_enter();
  88
  89         console_verbose();
  90         spin_lock_irq(&die_lock);
  91         bust_spinlocks(1);
  92
  93         printk("%s: %04lx [#%d]\n", str, err & 0xffff, ++die_counter);
  94
  95         CHK_REMOTE_DEBUG(regs);
  96         print_modules();
  97         show_regs(regs);
  98
  99         printk("Process: %s (pid: %d, stack limit = %p)\n", current->comm,
 100                         task_pid_nr(current), task_stack_page(current) + 1);
 101
 102         if (!user_mode(regs) || in_interrupt())
 103                 dump_mem("Stack: ", regs->regs[15], THREAD_SIZE +
 104                          (unsigned long)task_stack_page(current));
 105
 106         bust_spinlocks(0);
 107         add_taint(TAINT_DIE);
 108         spin_unlock_irq(&die_lock);
 109
 110         if (kexec_should_crash(current))
 111                 crash_kexec(regs);
 112
 113         if (in_interrupt())
 114                 panic("Fatal exception in interrupt");
 115
 116         if (panic_on_oops)
 117                 panic("Fatal exception");
 118
 119         oops_exit();
 120         do_exit(SIGSEGV);
 121 }
 122
 123 static inline void die_if_kernel(const char *str, struct pt_regs *regs,
 124                                  long err)
 125 {
 126         if (!user_mode(regs))
 127                 die(str, regs, err);
 128 }
 129
 130 /*
 131  * try and fix up kernelspace address errors
 132  * - userspace errors just cause EFAULT to be returned, resulting in SEGV
 133  * - kernel/userspace interfaces cause a jump to an appropriate handler
 134  * - other kernel errors are bad
 135  * - return 0 if fixed-up, -EFAULT if non-fatal (to the kernel) fault
 136  */
 137 static int die_if_no_fixup(const char * str, struct pt_regs * regs, long err)
 138 {
 139         if (!user_mode(regs)) {
 140                 const struct exception_table_entry *fixup;
 141                 fixup = search_exception_tables(regs->pc);
 142                 if (fixup) {
 143                         regs->pc = fixup->fixup;
 144                         return 0;
 145                 }
 146                 die(str, regs, err);
 147         }
 148         return -EFAULT;
 149 }
 150
 151 static inline void sign_extend(unsigned int count, unsigned char *dst)
 152 {
 153 #ifdef __LITTLE_ENDIAN__
 154         if ((count == 1) && dst[0] & 0x80) {
 155                 dst[1] = 0xff;
 156                 dst[2] = 0xff;
 157                 dst[3] = 0xff;
 158         }
 159         if ((count == 2) && dst[1] & 0x80) {
 160                 dst[2] = 0xff;
 161                 dst[3] = 0xff;
 162         }
 163 #else
 164         if ((count == 1) && dst[3] & 0x80) {
 165                 dst[2] = 0xff;
 166                 dst[1] = 0xff;
 167                 dst[0] = 0xff;
 168         }
 169         if ((count == 2) && dst[2] & 0x80) {
 170                 dst[1] = 0xff;
 171                 dst[0] = 0xff;
 172         }
 173 #endif
 174 }
 175
 176 static struct mem_access user_mem_access = {
 177         copy_from_user,
 178         copy_to_user,
 179 };
 180
 181 /*
 182  * handle an instruction that does an unaligned memory access by emulating the
 183  * desired behaviour
 184  * - note that PC _may not_ point to the faulting instruction
 185  *   (if that instruction is in a branch delay slot)
 186  * - return 0 if emulation okay, -EFAULT on existential error
 187  */
 188 static int handle_unaligned_ins(opcode_t instruction, struct pt_regs *regs,
 189                                 struct mem_access *ma)
 190 {
 191         int ret, index, count;
 192         unsigned long *rm, *rn;
 193         unsigned char *src, *dst;
 194
 195         index = (instruction>>8)&15;    /* 0x0F00 */
 196         rn = &regs->regs[index];
 197
 198         index = (instruction>>4)&15;    /* 0x00F0 */
 199         rm = &regs->regs[index];
 200
 201         count = 1<<(instruction&3);
 202
 203         ret = -EFAULT;
 204         switch (instruction>>12) {
 205         case 0: /* mov.[bwl] to/from memory via r0+rn */
 206                 if (instruction & 8) {
 207                         /* from memory */
 208                         src = (unsigned char*) *rm;
 209                         src += regs->regs[0];
 210                         dst = (unsigned char*) rn;
 211                         *(unsigned long*)dst = 0;
 212
 213 #if !defined(__LITTLE_ENDIAN__)
 214                         dst += 4-count;
 215 #endif
 216                         if (ma->from(dst, src, count))
 217                                 goto fetch_fault;
 218
 219                         sign_extend(count, dst);
 220                 } else {
 221                         /* to memory */
 222                         src = (unsigned char*) rm;
 223 #if !defined(__LITTLE_ENDIAN__)
 224                         src += 4-count;
 225 #endif
 226                         dst = (unsigned char*) *rn;
 227                         dst += regs->regs[0];
 228
 229                         if (ma->to(dst, src, count))
 230                                 goto fetch_fault;
 231                 }
 232                 ret = 0;
 233                 break;
 234
 235         case 1: /* mov.l Rm,@(disp,Rn) */
 236                 src = (unsigned char*) rm;
 237                 dst = (unsigned char*) *rn;
 238                 dst += (instruction&0x000F)<<2;
 239
 240                 if (ma->to(dst, src, 4))
 241                         goto fetch_fault;
 242                 ret = 0;
 243                 break;
 244
 245         case 2: /* mov.[bwl] to memory, possibly with pre-decrement */
 246                 if (instruction & 4)
 247                         *rn -= count;
 248                 src = (unsigned char*) rm;
 249                 dst = (unsigned char*) *rn;
 250 #if !defined(__LITTLE_ENDIAN__)
 251                 src += 4-count;
 252 #endif
 253                 if (ma->to(dst, src, count))
 254                         goto fetch_fault;
 255                 ret = 0;
 256                 break;
 257
 258         case 5: /* mov.l @(disp,Rm),Rn */
 259                 src = (unsigned char*) *rm;
 260                 src += (instruction&0x000F)<<2;
 261                 dst = (unsigned char*) rn;
 262                 *(unsigned long*)dst = 0;
 263
 264                 if (ma->from(dst, src, 4))
 265                         goto fetch_fault;
 266                 ret = 0;
 267                 break;
 268
 269         case 6: /* mov.[bwl] from memory, possibly with post-increment */
 270                 src = (unsigned char*) *rm;
 271                 if (instruction & 4)
 272                         *rm += count;
 273                 dst = (unsigned char*) rn;
 274                 *(unsigned long*)dst = 0;
 275
 276 #if !defined(__LITTLE_ENDIAN__)
 277                 dst += 4-count;
 278 #endif
 279                 if (ma->from(dst, src, count))
 280                         goto fetch_fault;
 281                 sign_extend(count, dst);
 282                 ret = 0;
 283                 break;
 284
 285         case 8:
 286                 switch ((instruction&0xFF00)>>8) {
 287                 case 0x81: /* mov.w R0,@(disp,Rn) */
 288                         src = (unsigned char*) &regs->regs[0];
 289 #if !defined(__LITTLE_ENDIAN__)
 290                         src += 2;
 291 #endif
 292                         dst = (unsigned char*) *rm; /* called Rn in the spec */
 293                         dst += (instruction&0x000F)<<1;
 294
 295                         if (ma->to(dst, src, 2))
 296                                 goto fetch_fault;
 297                         ret = 0;
 298                         break;
 299
 300                 case 0x85: /* mov.w @(disp,Rm),R0 */
 301                         src = (unsigned char*) *rm;
 302                         src += (instruction&0x000F)<<1;
 303                         dst = (unsigned char*) &regs->regs[0];
 304                         *(unsigned long*)dst = 0;
 305
 306 #if !defined(__LITTLE_ENDIAN__)
 307                         dst += 2;
 308 #endif
 309                         if (ma->from(dst, src, 2))
 310                                 goto fetch_fault;
 311                         sign_extend(2, dst);
 312                         ret = 0;
 313                         break;
 314                 }
 315                 break;
 316         }
 317         return ret;
 318
 319  fetch_fault:
 320         /* Argh. Address not only misaligned but also non-existent.
 321          * Raise an EFAULT and see if it's trapped
 322          */
 323         return die_if_no_fixup("Fault in unaligned fixup", regs, 0);
 324 }
 325
 326 /*
 327  * emulate the instruction in the delay slot
 328  * - fetches the instruction from PC+2
 329  */
 330 static inline int handle_delayslot(struct pt_regs *regs,
 331                                    opcode_t old_instruction,
 332                                    struct mem_access *ma)
 333 {
 334         opcode_t instruction;
 335         void *addr = (void *)(regs->pc + instruction_size(old_instruction));
 336
 337         if (copy_from_user(&instruction, addr, sizeof(instruction))) {
 338                 /* the instruction-fetch faulted */
 339                 if (user_mode(regs))
 340                         return -EFAULT;
 341
 342                 /* kernel */
 343                 die("delay-slot-insn faulting in handle_unaligned_delayslot",
 344                     regs, 0);
 345         }
 346
 347         return handle_unaligned_ins(instruction, regs, ma);
 348 }
 349
 350 /*
 351  * handle an instruction that does an unaligned memory access
 352  * - have to be careful of branch delay-slot instructions that fault
 353  *  SH3:
 354  *   - if the branch would be taken PC points to the branch
 355  *   - if the branch would not be taken, PC points to delay-slot
 356  *  SH4:
 357  *   - PC always points to delayed branch
 358  * - return 0 if handled, -EFAULT if failed (may not return if in kernel)
 359  */
 360
 361 /* Macros to determine offset from current PC for branch instructions */
 362 /* Explicit type coercion is used to force sign extension where needed */
 363 #define SH_PC_8BIT_OFFSET(instr) ((((signed char)(instr))*2) + 4)
 364 #define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4)
 365
 366 /*
 367  * XXX: SH-2A needs this too, but it needs an overhaul thanks to mixed 32-bit
 368  * opcodes..
 369  */
 370
 371 static int handle_unaligned_notify_count = 10;
 372
 373 int handle_unaligned_access(opcode_t instruction, struct pt_regs *regs,
 374                             struct mem_access *ma)
 375 {
 376         u_int rm;
 377         int ret, index;
 378
 379         index = (instruction>>8)&15;    /* 0x0F00 */
 380         rm = regs->regs[index];
 381
 382         /* shout about the first ten userspace fixups */
 383         if (user_mode(regs) && handle_unaligned_notify_count>0) {
 384                 handle_unaligned_notify_count--;
 385
 386                 printk(KERN_NOTICE "Fixing up unaligned userspace access "
 387                        "in \"%s\" pid=%d pc=0x%p ins=0x%04hx\n",
 388                        current->comm, task_pid_nr(current),
 389                        (void *)regs->pc, instruction);
 390         }
 391
 392         ret = -EFAULT;
 393         switch (instruction&0xF000) {
 394         case 0x0000:
 395                 if (instruction==0x000B) {
 396                         /* rts */
 397                         ret = handle_delayslot(regs, instruction, ma);
 398                         if (ret==0)
 399                                 regs->pc = regs->pr;
 400                 }
 401                 else if ((instruction&0x00FF)==0x0023) {
 402                         /* braf @Rm */
 403                         ret = handle_delayslot(regs, instruction, ma);
 404                         if (ret==0)
 405                                 regs->pc += rm + 4;
 406                 }
 407                 else if ((instruction&0x00FF)==0x0003) {
 408                         /* bsrf @Rm */
 409                         ret = handle_delayslot(regs, instruction, ma);
 410                         if (ret==0) {
 411                                 regs->pr = regs->pc + 4;
 412                                 regs->pc += rm + 4;
 413                         }
 414                 }
 415                 else {
 416                         /* mov.[bwl] to/from memory via r0+rn */
 417                         goto simple;
 418                 }
 419                 break;
 420
 421         case 0x1000: /* mov.l Rm,@(disp,Rn) */
 422                 goto simple;
 423
 424         case 0x2000: /* mov.[bwl] to memory, possibly with pre-decrement */
 425                 goto simple;
 426
 427         case 0x4000:
 428                 if ((instruction&0x00FF)==0x002B) {
 429                         /* jmp @Rm */
 430                         ret = handle_delayslot(regs, instruction, ma);
 431                         if (ret==0)
 432                                 regs->pc = rm;
 433                 }
 434                 else if ((instruction&0x00FF)==0x000B) {
 435                         /* jsr @Rm */
 436                         ret = handle_delayslot(regs, instruction, ma);
 437                         if (ret==0) {
 438                                 regs->pr = regs->pc + 4;
 439                                 regs->pc = rm;
 440                         }
 441                 }
 442                 else {
 443                         /* mov.[bwl] to/from memory via r0+rn */
 444                         goto simple;
 445                 }
 446                 break;
 447
 448         case 0x5000: /* mov.l @(disp,Rm),Rn */
 449                 goto simple;
 450
 451         case 0x6000: /* mov.[bwl] from memory, possibly with post-increment */
 452                 goto simple;
 453
 454         case 0x8000: /* bf lab, bf/s lab, bt lab, bt/s lab */
 455                 switch (instruction&0x0F00) {
 456                 case 0x0100: /* mov.w R0,@(disp,Rm) */
 457                         goto simple;
 458                 case 0x0500: /* mov.w @(disp,Rm),R0 */
 459                         goto simple;
 460                 case 0x0B00: /* bf   lab - no delayslot*/
 461                         break;
 462                 case 0x0F00: /* bf/s lab */
 463                         ret = handle_delayslot(regs, instruction, ma);
 464                         if (ret==0) {
 465 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
 466                                 if ((regs->sr & 0x00000001) != 0)
 467                                         regs->pc += 4; /* next after slot */
 468                                 else
 469 #endif
 470                                         regs->pc += SH_PC_8BIT_OFFSET(instruction);
 471                         }
 472                         break;
 473                 case 0x0900: /* bt   lab - no delayslot */
 474                         break;
 475                 case 0x0D00: /* bt/s lab */
 476                         ret = handle_delayslot(regs, instruction, ma);
 477                         if (ret==0) {
 478 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
 479                                 if ((regs->sr & 0x00000001) == 0)
 480                                         regs->pc += 4; /* next after slot */
 481                                 else
 482 #endif
 483                                         regs->pc += SH_PC_8BIT_OFFSET(instruction);
 484                         }
 485                         break;
 486                 }
 487                 break;
 488
 489         case 0xA000: /* bra label */
 490                 ret = handle_delayslot(regs, instruction, ma);
 491                 if (ret==0)
 492                         regs->pc += SH_PC_12BIT_OFFSET(instruction);
 493                 break;
 494
 495         case 0xB000: /* bsr label */
 496                 ret = handle_delayslot(regs, instruction, ma);
 497                 if (ret==0) {
 498                         regs->pr = regs->pc + 4;
 499                         regs->pc += SH_PC_12BIT_OFFSET(instruction);
 500                 }
 501                 break;
 502         }
 503         return ret;
 504
 505         /* handle non-delay-slot instruction */
 506  simple:
 507         ret = handle_unaligned_ins(instruction, regs, ma);
 508         if (ret==0)
 509                 regs->pc += instruction_size(instruction);
 510         return ret;
 511 }
 512
 513 #ifdef CONFIG_CPU_HAS_SR_RB
 514 #define lookup_exception_vector(x)      \
 515         __asm__ __volatile__ ("stc r2_bank, %0\n\t" : "=r" ((x)))
 516 #else
 517 #define lookup_exception_vector(x)      \
 518         __asm__ __volatile__ ("mov r4, %0\n\t" : "=r" ((x)))
 519 #endif
 520
 521 /*
 522  * Handle various address error exceptions:
 523  *  - instruction address error:
 524  *       misaligned PC
 525  *       PC >= 0x80000000 in user mode
 526  *  - data address error (read and write)
 527  *       misaligned data access
 528  *       access to >= 0x80000000 is user mode
 529  * Unfortuntaly we can't distinguish between instruction address error
 530  * and data address errors caused by read accesses.
 531  */
 532 asmlinkage void do_address_error(struct pt_regs *regs,
 533                                  unsigned long writeaccess,
 534                                  unsigned long address)
 535 {
 536         unsigned long error_code = 0;
 537         mm_segment_t oldfs;
 538         siginfo_t info;
 539         opcode_t instruction;
 540         int tmp;
 541
 542         /* Intentional ifdef */
 543 #ifdef CONFIG_CPU_HAS_SR_RB
 544         lookup_exception_vector(error_code);
 545 #endif
 546
 547         oldfs = get_fs();
 548
 549         if (user_mode(regs)) {
 550                 int si_code = BUS_ADRERR;
 551
 552                 local_irq_enable();
 553
 554                 /* bad PC is not something we can fix */
 555                 if (regs->pc & 1) {
 556                         si_code = BUS_ADRALN;
 557                         goto uspace_segv;
 558                 }
 559
 560                 set_fs(USER_DS);
 561                 if (copy_from_user(&instruction, (void *)(regs->pc),
 562                                    sizeof(instruction))) {
 563                         /* Argh. Fault on the instruction itself.
 564                            This should never happen non-SMP
 565                         */
 566                         set_fs(oldfs);
 567                         goto uspace_segv;
 568                 }
 569
 570                 tmp = handle_unaligned_access(instruction, regs,
 571                                               &user_mem_access);
 572                 set_fs(oldfs);
 573
 574                 if (tmp==0)
 575                         return; /* sorted */
 576 uspace_segv:
 577                 printk(KERN_NOTICE "Sending SIGBUS to \"%s\" due to unaligned "
 578                        "access (PC %lx PR %lx)\n", current->comm, regs->pc,
 579                        regs->pr);
 580
 581                 info.si_signo = SIGBUS;
 582                 info.si_errno = 0;
 583                 info.si_code = si_code;
 584                 info.si_addr = (void __user *)address;
 585                 force_sig_info(SIGBUS, &info, current);
 586         } else {
 587                 if (regs->pc & 1)
 588                         die("unaligned program counter", regs, error_code);
 589
 590                 set_fs(KERNEL_DS);
 591                 if (copy_from_user(&instruction, (void *)(regs->pc),
 592                                    sizeof(instruction))) {
 593                         /* Argh. Fault on the instruction itself.
 594                            This should never happen non-SMP
 595                         */
 596                         set_fs(oldfs);
 597                         die("insn faulting in do_address_error", regs, 0);
 598                 }
 599
 600                 handle_unaligned_access(instruction, regs, &user_mem_access);
 601                 set_fs(oldfs);
 602         }
 603 }
 604
 605 #ifdef CONFIG_SH_DSP
 606 /*
 607  *      SH-DSP support gerg@snapgear.com.
 608  */
 609 int is_dsp_inst(struct pt_regs *regs)
 610 {
 611         unsigned short inst = 0;
 612
 613         /*
 614          * Safe guard if DSP mode is already enabled or we're lacking
 615          * the DSP altogether.
 616          */
 617         if (!(current_cpu_data.flags & CPU_HAS_DSP) || (regs->sr & SR_DSP))
 618                 return 0;
 619
 620         get_user(inst, ((unsigned short *) regs->pc));
 621
 622         inst &= 0xf000;
 623
 624         /* Check for any type of DSP or support instruction */
 625         if ((inst == 0xf000) || (inst == 0x4000))
 626                 return 1;
 627
 628         return 0;
 629 }
 630 #else
 631 #define is_dsp_inst(regs)       (0)
 632 #endif /* CONFIG_SH_DSP */
 633
 634 #ifdef CONFIG_CPU_SH2A
 635 asmlinkage void do_divide_error(unsigned long r4, unsigned long r5,
 636                                 unsigned long r6, unsigned long r7,
 637                                 struct pt_regs __regs)
 638 {
 639         siginfo_t info;
 640
 641         switch (r4) {
 642         case TRAP_DIVZERO_ERROR:
 643                 info.si_code = FPE_INTDIV;
 644                 break;
 645         case TRAP_DIVOVF_ERROR:
 646                 info.si_code = FPE_INTOVF;
 647                 break;
 648         }
 649
 650         force_sig_info(SIGFPE, &info, current);
 651 }
 652 #endif
 653
 654 asmlinkage void do_reserved_inst(unsigned long r4, unsigned long r5,
 655                                 unsigned long r6, unsigned long r7,
 656                                 struct pt_regs __regs)
 657 {
 658         struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
 659         unsigned long error_code;
 660         struct task_struct *tsk = current;
 661
 662 #ifdef CONFIG_SH_FPU_EMU
 663         unsigned short inst = 0;
 664         int err;
 665
 666         get_user(inst, (unsigned short*)regs->pc);
 667
 668         err = do_fpu_inst(inst, regs);
 669         if (!err) {
 670                 regs->pc += instruction_size(inst);
 671                 return;
 672         }
 673         /* not a FPU inst. */
 674 #endif
 675
 676 #ifdef CONFIG_SH_DSP
 677         /* Check if it's a DSP instruction */
 678         if (is_dsp_inst(regs)) {
 679                 /* Enable DSP mode, and restart instruction. */
 680                 regs->sr |= SR_DSP;
 681                 return;
 682         }
 683 #endif
 684
 685         lookup_exception_vector(error_code);
 686
 687         local_irq_enable();
 688         CHK_REMOTE_DEBUG(regs);
 689         force_sig(SIGILL, tsk);
 690         die_if_no_fixup("reserved instruction", regs, error_code);
 691 }
 692
 693 #ifdef CONFIG_SH_FPU_EMU
 694 static int emulate_branch(unsigned short inst, struct pt_regs* regs)
 695 {
 696         /*
 697          * bfs: 8fxx: PC+=d*2+4;
 698          * bts: 8dxx: PC+=d*2+4;
 699          * bra: axxx: PC+=D*2+4;
 700          * bsr: bxxx: PC+=D*2+4  after PR=PC+4;
 701          * braf:0x23: PC+=Rn*2+4;
 702          * bsrf:0x03: PC+=Rn*2+4 after PR=PC+4;
 703          * jmp: 4x2b: PC=Rn;
 704          * jsr: 4x0b: PC=Rn      after PR=PC+4;
 705          * rts: 000b: PC=PR;
 706          */
 707         if ((inst & 0xfd00) == 0x8d00) {
 708                 regs->pc += SH_PC_8BIT_OFFSET(inst);
 709                 return 0;
 710         }
 711
 712         if ((inst & 0xe000) == 0xa000) {
 713                 regs->pc += SH_PC_12BIT_OFFSET(inst);
 714                 return 0;
 715         }
 716
 717         if ((inst & 0xf0df) == 0x0003) {
 718                 regs->pc += regs->regs[(inst & 0x0f00) >> 8] + 4;
 719                 return 0;
 720         }
 721
 722         if ((inst & 0xf0df) == 0x400b) {
 723                 regs->pc = regs->regs[(inst & 0x0f00) >> 8];
 724                 return 0;
 725         }
 726
 727         if ((inst & 0xffff) == 0x000b) {
 728                 regs->pc = regs->pr;
 729                 return 0;
 730         }
 731
 732         return 1;
 733 }
 734 #endif
 735
 736 asmlinkage void do_illegal_slot_inst(unsigned long r4, unsigned long r5,
 737                                 unsigned long r6, unsigned long r7,
 738                                 struct pt_regs __regs)
 739 {
 740         struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
 741         unsigned long error_code;
 742         struct task_struct *tsk = current;
 743 #ifdef CONFIG_SH_FPU_EMU
 744         unsigned short inst = 0;
 745
 746         get_user(inst, (unsigned short *)regs->pc + 1);
 747         if (!do_fpu_inst(inst, regs)) {
 748                 get_user(inst, (unsigned short *)regs->pc);
 749                 if (!emulate_branch(inst, regs))
 750                         return;
 751                 /* fault in branch.*/
 752         }
 753         /* not a FPU inst. */
 754 #endif
 755
 756         lookup_exception_vector(error_code);
 757
 758         local_irq_enable();
 759         CHK_REMOTE_DEBUG(regs);
 760         force_sig(SIGILL, tsk);
 761         die_if_no_fixup("illegal slot instruction", regs, error_code);
 762 }
 763
 764 asmlinkage void do_exception_error(unsigned long r4, unsigned long r5,
 765                                    unsigned long r6, unsigned long r7,
 766                                    struct pt_regs __regs)
 767 {
 768         struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
 769         long ex;
 770
 771         lookup_exception_vector(ex);
 772         die_if_kernel("exception", regs, ex);
 773 }
 774
 775 #if defined(CONFIG_SH_STANDARD_BIOS)
 776 void *gdb_vbr_vector;
 777
 778 static inline void __init gdb_vbr_init(void)
 779 {
 780         register unsigned long vbr;
 781
 782         /*
 783          * Read the old value of the VBR register to initialise
 784          * the vector through which debug and BIOS traps are
 785          * delegated by the Linux trap handler.
 786          */
 787         asm volatile("stc vbr, %0" : "=r" (vbr));
 788
 789         gdb_vbr_vector = (void *)(vbr + 0x100);
 790         printk("Setting GDB trap vector to 0x%08lx\n",
 791                (unsigned long)gdb_vbr_vector);
 792 }
 793 #endif
 794
 795 void __cpuinit per_cpu_trap_init(void)
 796 {
 797         extern void *vbr_base;
 798
 799 #ifdef CONFIG_SH_STANDARD_BIOS
 800         if (raw_smp_processor_id() == 0)
 801                 gdb_vbr_init();
 802 #endif
 803
 804         /* NOTE: The VBR value should be at P1
 805            (or P2, virtural "fixed" address space).
 806            It's definitely should not in physical address.  */
 807
 808         asm volatile("ldc       %0, vbr"
 809                      : /* no output */
 810                      : "r" (&vbr_base)
 811                      : "memory");
 812 }
 813
 814 void *set_exception_table_vec(unsigned int vec, void *handler)
 815 {
 816         extern void *exception_handling_table[];
 817         void *old_handler;
 818
 819         old_handler = exception_handling_table[vec];
 820         exception_handling_table[vec] = handler;
 821         return old_handler;
 822 }
 823
 824 void __init trap_init(void)
 825 {
 826         set_exception_table_vec(TRAP_RESERVED_INST, do_reserved_inst);
 827         set_exception_table_vec(TRAP_ILLEGAL_SLOT_INST, do_illegal_slot_inst);
 828
 829 #if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_FPU) || \
 830     defined(CONFIG_SH_FPU_EMU)
 831         /*
 832          * For SH-4 lacking an FPU, treat floating point instructions as
 833          * reserved. They'll be handled in the math-emu case, or faulted on
 834          * otherwise.
 835          */
 836         set_exception_table_evt(0x800, do_reserved_inst);
 837         set_exception_table_evt(0x820, do_illegal_slot_inst);
 838 #elif defined(CONFIG_SH_FPU)
 839 #ifdef CONFIG_CPU_SUBTYPE_SHX3
 840         set_exception_table_evt(0xd80, fpu_state_restore_trap_handler);
 841         set_exception_table_evt(0xda0, fpu_state_restore_trap_handler);
 842 #else
 843         set_exception_table_evt(0x800, fpu_state_restore_trap_handler);
 844         set_exception_table_evt(0x820, fpu_state_restore_trap_handler);
 845 #endif
 846 #endif
 847
 848 #ifdef CONFIG_CPU_SH2
 849         set_exception_table_vec(TRAP_ADDRESS_ERROR, address_error_trap_handler);
 850 #endif
 851 #ifdef CONFIG_CPU_SH2A
 852         set_exception_table_vec(TRAP_DIVZERO_ERROR, do_divide_error);
 853         set_exception_table_vec(TRAP_DIVOVF_ERROR, do_divide_error);
 854 #endif
 855
 856         /* Setup VBR for boot cpu */
 857         per_cpu_trap_init();
 858 }
 859
 860 void show_trace(struct task_struct *tsk, unsigned long *sp,
 861                 struct pt_regs *regs)
 862 {
 863         unsigned long addr;
 864
 865         if (regs && user_mode(regs))
 866                 return;
 867
 868         printk("\nCall trace: ");
 869 #ifdef CONFIG_KALLSYMS
 870         printk("\n");
 871 #endif
 872
 873         while (!kstack_end(sp)) {
 874                 addr = *sp++;
 875                 if (kernel_text_address(addr))
 876                         print_ip_sym(addr);
 877         }
 878
 879         printk("\n");
 880
 881         if (!tsk)
 882                 tsk = current;
 883
 884         debug_show_held_locks(tsk);
 885 }
 886
 887 void show_stack(struct task_struct *tsk, unsigned long *sp)
 888 {
 889         unsigned long stack;
 890
 891         if (!tsk)
 892                 tsk = current;
 893         if (tsk == current)
 894                 sp = (unsigned long *)current_stack_pointer;
 895         else
 896                 sp = (unsigned long *)tsk->thread.sp;
 897
 898         stack = (unsigned long)sp;
 899         dump_mem("Stack: ", stack, THREAD_SIZE +
 900                  (unsigned long)task_stack_page(tsk));
 901         show_trace(tsk, sp, NULL);
 902 }
 903
 904 void dump_stack(void)
 905 {
 906         show_stack(NULL, NULL);
 907 }
 908 EXPORT_SYMBOL(dump_stack);