SAFE public projects git trees. - safe/jmp/linux-2.6/blob - arch/sh/kernel/traps_32.c

   1 /*
   2  * 'traps.c' handles hardware traps and faults after we have saved some
   3  * state in 'entry.S'.
   4  *
   5  *  SuperH version: Copyright (C) 1999 Niibe Yutaka
   6  *                  Copyright (C) 2000 Philipp Rumpf
   7  *                  Copyright (C) 2000 David Howells
   8  *                  Copyright (C) 2002 - 2007 Paul Mundt
   9  *
  10  * This file is subject to the terms and conditions of the GNU General Public
  11  * License.  See the file "COPYING" in the main directory of this archive
  12  * for more details.
  13  */
  14 #include <linux/kernel.h>
  15 #include <linux/ptrace.h>
  16 #include <linux/hardirq.h>
  17 #include <linux/init.h>
  18 #include <linux/spinlock.h>
  19 #include <linux/module.h>
  20 #include <linux/kallsyms.h>
  21 #include <linux/io.h>
  22 #include <linux/bug.h>
  23 #include <linux/debug_locks.h>
  24 #include <linux/kdebug.h>
  25 #include <linux/kexec.h>
  26 #include <linux/limits.h>
  27 #include <asm/system.h>
  28 #include <asm/uaccess.h>
  29 #include <asm/fpu.h>
  30 #include <asm/kprobes.h>
  31
  32 #ifdef CONFIG_CPU_SH2
  33 # define TRAP_RESERVED_INST     4
  34 # define TRAP_ILLEGAL_SLOT_INST 6
  35 # define TRAP_ADDRESS_ERROR     9
  36 # ifdef CONFIG_CPU_SH2A
  37 #  define TRAP_UBC              12
  38 #  define TRAP_FPU_ERROR        13
  39 #  define TRAP_DIVZERO_ERROR    17
  40 #  define TRAP_DIVOVF_ERROR     18
  41 # endif
  42 #else
  43 #define TRAP_RESERVED_INST      12
  44 #define TRAP_ILLEGAL_SLOT_INST  13
  45 #endif
  46
  47 static void dump_mem(const char *str, unsigned long bottom, unsigned long top)
  48 {
  49         unsigned long p;
  50         int i;
  51
  52         printk("%s(0x%08lx to 0x%08lx)\n", str, bottom, top);
  53
  54         for (p = bottom & ~31; p < top; ) {
  55                 printk("%04lx: ", p & 0xffff);
  56
  57                 for (i = 0; i < 8; i++, p += 4) {
  58                         unsigned int val;
  59
  60                         if (p < bottom || p >= top)
  61                                 printk("         ");
  62                         else {
  63                                 if (__get_user(val, (unsigned int __user *)p)) {
  64                                         printk("\n");
  65                                         return;
  66                                 }
  67                                 printk("%08x ", val);
  68                         }
  69                 }
  70                 printk("\n");
  71         }
  72 }
  73
  74 static DEFINE_SPINLOCK(die_lock);
  75
  76 void die(const char * str, struct pt_regs * regs, long err)
  77 {
  78         static int die_counter;
  79
  80         oops_enter();
  81
  82         console_verbose();
  83         spin_lock_irq(&die_lock);
  84         bust_spinlocks(1);
  85
  86         printk("%s: %04lx [#%d]\n", str, err & 0xffff, ++die_counter);
  87
  88         print_modules();
  89         show_regs(regs);
  90
  91         printk("Process: %s (pid: %d, stack limit = %p)\n", current->comm,
  92                         task_pid_nr(current), task_stack_page(current) + 1);
  93
  94         if (!user_mode(regs) || in_interrupt())
  95                 dump_mem("Stack: ", regs->regs[15], THREAD_SIZE +
  96                          (unsigned long)task_stack_page(current));
  97
  98         notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV);
  99
 100         bust_spinlocks(0);
 101         add_taint(TAINT_DIE);
 102         spin_unlock_irq(&die_lock);
 103
 104         if (kexec_should_crash(current))
 105                 crash_kexec(regs);
 106
 107         if (in_interrupt())
 108                 panic("Fatal exception in interrupt");
 109
 110         if (panic_on_oops)
 111                 panic("Fatal exception");
 112
 113         oops_exit();
 114         do_exit(SIGSEGV);
 115 }
 116
 117 static inline void die_if_kernel(const char *str, struct pt_regs *regs,
 118                                  long err)
 119 {
 120         if (!user_mode(regs))
 121                 die(str, regs, err);
 122 }
 123
 124 /*
 125  * try and fix up kernelspace address errors
 126  * - userspace errors just cause EFAULT to be returned, resulting in SEGV
 127  * - kernel/userspace interfaces cause a jump to an appropriate handler
 128  * - other kernel errors are bad
 129  */
 130 static void die_if_no_fixup(const char * str, struct pt_regs * regs, long err)
 131 {
 132         if (!user_mode(regs)) {
 133                 const struct exception_table_entry *fixup;
 134                 fixup = search_exception_tables(regs->pc);
 135                 if (fixup) {
 136                         regs->pc = fixup->fixup;
 137                         return;
 138                 }
 139
 140                 die(str, regs, err);
 141         }
 142 }
 143
 144 static inline void sign_extend(unsigned int count, unsigned char *dst)
 145 {
 146 #ifdef __LITTLE_ENDIAN__
 147         if ((count == 1) && dst[0] & 0x80) {
 148                 dst[1] = 0xff;
 149                 dst[2] = 0xff;
 150                 dst[3] = 0xff;
 151         }
 152         if ((count == 2) && dst[1] & 0x80) {
 153                 dst[2] = 0xff;
 154                 dst[3] = 0xff;
 155         }
 156 #else
 157         if ((count == 1) && dst[3] & 0x80) {
 158                 dst[2] = 0xff;
 159                 dst[1] = 0xff;
 160                 dst[0] = 0xff;
 161         }
 162         if ((count == 2) && dst[2] & 0x80) {
 163                 dst[1] = 0xff;
 164                 dst[0] = 0xff;
 165         }
 166 #endif
 167 }
 168
 169 static struct mem_access user_mem_access = {
 170         copy_from_user,
 171         copy_to_user,
 172 };
 173
 174 /*
 175  * handle an instruction that does an unaligned memory access by emulating the
 176  * desired behaviour
 177  * - note that PC _may not_ point to the faulting instruction
 178  *   (if that instruction is in a branch delay slot)
 179  * - return 0 if emulation okay, -EFAULT on existential error
 180  */
 181 static int handle_unaligned_ins(insn_size_t instruction, struct pt_regs *regs,
 182                                 struct mem_access *ma)
 183 {
 184         int ret, index, count;
 185         unsigned long *rm, *rn;
 186         unsigned char *src, *dst;
 187         unsigned char __user *srcu, *dstu;
 188
 189         index = (instruction>>8)&15;    /* 0x0F00 */
 190         rn = &regs->regs[index];
 191
 192         index = (instruction>>4)&15;    /* 0x00F0 */
 193         rm = &regs->regs[index];
 194
 195         count = 1<<(instruction&3);
 196
 197         ret = -EFAULT;
 198         switch (instruction>>12) {
 199         case 0: /* mov.[bwl] to/from memory via r0+rn */
 200                 if (instruction & 8) {
 201                         /* from memory */
 202                         srcu = (unsigned char __user *)*rm;
 203                         srcu += regs->regs[0];
 204                         dst = (unsigned char *)rn;
 205                         *(unsigned long *)dst = 0;
 206
 207 #if !defined(__LITTLE_ENDIAN__)
 208                         dst += 4-count;
 209 #endif
 210                         if (ma->from(dst, srcu, count))
 211                                 goto fetch_fault;
 212
 213                         sign_extend(count, dst);
 214                 } else {
 215                         /* to memory */
 216                         src = (unsigned char *)rm;
 217 #if !defined(__LITTLE_ENDIAN__)
 218                         src += 4-count;
 219 #endif
 220                         dstu = (unsigned char __user *)*rn;
 221                         dstu += regs->regs[0];
 222
 223                         if (ma->to(dstu, src, count))
 224                                 goto fetch_fault;
 225                 }
 226                 ret = 0;
 227                 break;
 228
 229         case 1: /* mov.l Rm,@(disp,Rn) */
 230                 src = (unsigned char*) rm;
 231                 dstu = (unsigned char __user *)*rn;
 232                 dstu += (instruction&0x000F)<<2;
 233
 234                 if (ma->to(dstu, src, 4))
 235                         goto fetch_fault;
 236                 ret = 0;
 237                 break;
 238
 239         case 2: /* mov.[bwl] to memory, possibly with pre-decrement */
 240                 if (instruction & 4)
 241                         *rn -= count;
 242                 src = (unsigned char*) rm;
 243                 dstu = (unsigned char __user *)*rn;
 244 #if !defined(__LITTLE_ENDIAN__)
 245                 src += 4-count;
 246 #endif
 247                 if (ma->to(dstu, src, count))
 248                         goto fetch_fault;
 249                 ret = 0;
 250                 break;
 251
 252         case 5: /* mov.l @(disp,Rm),Rn */
 253                 srcu = (unsigned char __user *)*rm;
 254                 srcu += (instruction & 0x000F) << 2;
 255                 dst = (unsigned char *)rn;
 256                 *(unsigned long *)dst = 0;
 257
 258                 if (ma->from(dst, srcu, 4))
 259                         goto fetch_fault;
 260                 ret = 0;
 261                 break;
 262
 263         case 6: /* mov.[bwl] from memory, possibly with post-increment */
 264                 srcu = (unsigned char __user *)*rm;
 265                 if (instruction & 4)
 266                         *rm += count;
 267                 dst = (unsigned char*) rn;
 268                 *(unsigned long*)dst = 0;
 269
 270 #if !defined(__LITTLE_ENDIAN__)
 271                 dst += 4-count;
 272 #endif
 273                 if (ma->from(dst, srcu, count))
 274                         goto fetch_fault;
 275                 sign_extend(count, dst);
 276                 ret = 0;
 277                 break;
 278
 279         case 8:
 280                 switch ((instruction&0xFF00)>>8) {
 281                 case 0x81: /* mov.w R0,@(disp,Rn) */
 282                         src = (unsigned char *) &regs->regs[0];
 283 #if !defined(__LITTLE_ENDIAN__)
 284                         src += 2;
 285 #endif
 286                         dstu = (unsigned char __user *)*rm; /* called Rn in the spec */
 287                         dstu += (instruction & 0x000F) << 1;
 288
 289                         if (ma->to(dstu, src, 2))
 290                                 goto fetch_fault;
 291                         ret = 0;
 292                         break;
 293
 294                 case 0x85: /* mov.w @(disp,Rm),R0 */
 295                         srcu = (unsigned char __user *)*rm;
 296                         srcu += (instruction & 0x000F) << 1;
 297                         dst = (unsigned char *) &regs->regs[0];
 298                         *(unsigned long *)dst = 0;
 299
 300 #if !defined(__LITTLE_ENDIAN__)
 301                         dst += 2;
 302 #endif
 303                         if (ma->from(dst, srcu, 2))
 304                                 goto fetch_fault;
 305                         sign_extend(2, dst);
 306                         ret = 0;
 307                         break;
 308                 }
 309                 break;
 310         }
 311         return ret;
 312
 313  fetch_fault:
 314         /* Argh. Address not only misaligned but also non-existent.
 315          * Raise an EFAULT and see if it's trapped
 316          */
 317         die_if_no_fixup("Fault in unaligned fixup", regs, 0);
 318         return -EFAULT;
 319 }
 320
 321 /*
 322  * emulate the instruction in the delay slot
 323  * - fetches the instruction from PC+2
 324  */
 325 static inline int handle_delayslot(struct pt_regs *regs,
 326                                    insn_size_t old_instruction,
 327                                    struct mem_access *ma)
 328 {
 329         insn_size_t instruction;
 330         void __user *addr = (void __user *)(regs->pc +
 331                 instruction_size(old_instruction));
 332
 333         if (copy_from_user(&instruction, addr, sizeof(instruction))) {
 334                 /* the instruction-fetch faulted */
 335                 if (user_mode(regs))
 336                         return -EFAULT;
 337
 338                 /* kernel */
 339                 die("delay-slot-insn faulting in handle_unaligned_delayslot",
 340                     regs, 0);
 341         }
 342
 343         return handle_unaligned_ins(instruction, regs, ma);
 344 }
 345
 346 /*
 347  * handle an instruction that does an unaligned memory access
 348  * - have to be careful of branch delay-slot instructions that fault
 349  *  SH3:
 350  *   - if the branch would be taken PC points to the branch
 351  *   - if the branch would not be taken, PC points to delay-slot
 352  *  SH4:
 353  *   - PC always points to delayed branch
 354  * - return 0 if handled, -EFAULT if failed (may not return if in kernel)
 355  */
 356
 357 /* Macros to determine offset from current PC for branch instructions */
 358 /* Explicit type coercion is used to force sign extension where needed */
 359 #define SH_PC_8BIT_OFFSET(instr) ((((signed char)(instr))*2) + 4)
 360 #define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4)
 361
 362 /*
 363  * XXX: SH-2A needs this too, but it needs an overhaul thanks to mixed 32-bit
 364  * opcodes..
 365  */
 366
 367 static int handle_unaligned_notify_count = 10;
 368
 369 int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs,
 370                             struct mem_access *ma)
 371 {
 372         u_int rm;
 373         int ret, index;
 374
 375         index = (instruction>>8)&15;    /* 0x0F00 */
 376         rm = regs->regs[index];
 377
 378         /* shout about the first ten userspace fixups */
 379         if (user_mode(regs) && handle_unaligned_notify_count>0) {
 380                 handle_unaligned_notify_count--;
 381
 382                 printk(KERN_NOTICE "Fixing up unaligned userspace access "
 383                        "in \"%s\" pid=%d pc=0x%p ins=0x%04hx\n",
 384                        current->comm, task_pid_nr(current),
 385                        (void *)regs->pc, instruction);
 386         }
 387
 388         ret = -EFAULT;
 389         switch (instruction&0xF000) {
 390         case 0x0000:
 391                 if (instruction==0x000B) {
 392                         /* rts */
 393                         ret = handle_delayslot(regs, instruction, ma);
 394                         if (ret==0)
 395                                 regs->pc = regs->pr;
 396                 }
 397                 else if ((instruction&0x00FF)==0x0023) {
 398                         /* braf @Rm */
 399                         ret = handle_delayslot(regs, instruction, ma);
 400                         if (ret==0)
 401                                 regs->pc += rm + 4;
 402                 }
 403                 else if ((instruction&0x00FF)==0x0003) {
 404                         /* bsrf @Rm */
 405                         ret = handle_delayslot(regs, instruction, ma);
 406                         if (ret==0) {
 407                                 regs->pr = regs->pc + 4;
 408                                 regs->pc += rm + 4;
 409                         }
 410                 }
 411                 else {
 412                         /* mov.[bwl] to/from memory via r0+rn */
 413                         goto simple;
 414                 }
 415                 break;
 416
 417         case 0x1000: /* mov.l Rm,@(disp,Rn) */
 418                 goto simple;
 419
 420         case 0x2000: /* mov.[bwl] to memory, possibly with pre-decrement */
 421                 goto simple;
 422
 423         case 0x4000:
 424                 if ((instruction&0x00FF)==0x002B) {
 425                         /* jmp @Rm */
 426                         ret = handle_delayslot(regs, instruction, ma);
 427                         if (ret==0)
 428                                 regs->pc = rm;
 429                 }
 430                 else if ((instruction&0x00FF)==0x000B) {
 431                         /* jsr @Rm */
 432                         ret = handle_delayslot(regs, instruction, ma);
 433                         if (ret==0) {
 434                                 regs->pr = regs->pc + 4;
 435                                 regs->pc = rm;
 436                         }
 437                 }
 438                 else {
 439                         /* mov.[bwl] to/from memory via r0+rn */
 440                         goto simple;
 441                 }
 442                 break;
 443
 444         case 0x5000: /* mov.l @(disp,Rm),Rn */
 445                 goto simple;
 446
 447         case 0x6000: /* mov.[bwl] from memory, possibly with post-increment */
 448                 goto simple;
 449
 450         case 0x8000: /* bf lab, bf/s lab, bt lab, bt/s lab */
 451                 switch (instruction&0x0F00) {
 452                 case 0x0100: /* mov.w R0,@(disp,Rm) */
 453                         goto simple;
 454                 case 0x0500: /* mov.w @(disp,Rm),R0 */
 455                         goto simple;
 456                 case 0x0B00: /* bf   lab - no delayslot*/
 457                         break;
 458                 case 0x0F00: /* bf/s lab */
 459                         ret = handle_delayslot(regs, instruction, ma);
 460                         if (ret==0) {
 461 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
 462                                 if ((regs->sr & 0x00000001) != 0)
 463                                         regs->pc += 4; /* next after slot */
 464                                 else
 465 #endif
 466                                         regs->pc += SH_PC_8BIT_OFFSET(instruction);
 467                         }
 468                         break;
 469                 case 0x0900: /* bt   lab - no delayslot */
 470                         break;
 471                 case 0x0D00: /* bt/s lab */
 472                         ret = handle_delayslot(regs, instruction, ma);
 473                         if (ret==0) {
 474 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
 475                                 if ((regs->sr & 0x00000001) == 0)
 476                                         regs->pc += 4; /* next after slot */
 477                                 else
 478 #endif
 479                                         regs->pc += SH_PC_8BIT_OFFSET(instruction);
 480                         }
 481                         break;
 482                 }
 483                 break;
 484
 485         case 0xA000: /* bra label */
 486                 ret = handle_delayslot(regs, instruction, ma);
 487                 if (ret==0)
 488                         regs->pc += SH_PC_12BIT_OFFSET(instruction);
 489                 break;
 490
 491         case 0xB000: /* bsr label */
 492                 ret = handle_delayslot(regs, instruction, ma);
 493                 if (ret==0) {
 494                         regs->pr = regs->pc + 4;
 495                         regs->pc += SH_PC_12BIT_OFFSET(instruction);
 496                 }
 497                 break;
 498         }
 499         return ret;
 500
 501         /* handle non-delay-slot instruction */
 502  simple:
 503         ret = handle_unaligned_ins(instruction, regs, ma);
 504         if (ret==0)
 505                 regs->pc += instruction_size(instruction);
 506         return ret;
 507 }
 508
 509 /*
 510  * Handle various address error exceptions:
 511  *  - instruction address error:
 512  *       misaligned PC
 513  *       PC >= 0x80000000 in user mode
 514  *  - data address error (read and write)
 515  *       misaligned data access
 516  *       access to >= 0x80000000 is user mode
 517  * Unfortuntaly we can't distinguish between instruction address error
 518  * and data address errors caused by read accesses.
 519  */
 520 asmlinkage void do_address_error(struct pt_regs *regs,
 521                                  unsigned long writeaccess,
 522                                  unsigned long address)
 523 {
 524         unsigned long error_code = 0;
 525         mm_segment_t oldfs;
 526         siginfo_t info;
 527         insn_size_t instruction;
 528         int tmp;
 529
 530         /* Intentional ifdef */
 531 #ifdef CONFIG_CPU_HAS_SR_RB
 532         error_code = lookup_exception_vector();
 533 #endif
 534
 535         oldfs = get_fs();
 536
 537         if (user_mode(regs)) {
 538                 int si_code = BUS_ADRERR;
 539
 540                 local_irq_enable();
 541
 542                 /* bad PC is not something we can fix */
 543                 if (regs->pc & 1) {
 544                         si_code = BUS_ADRALN;
 545                         goto uspace_segv;
 546                 }
 547
 548                 set_fs(USER_DS);
 549                 if (copy_from_user(&instruction, (void __user *)(regs->pc),
 550                                    sizeof(instruction))) {
 551                         /* Argh. Fault on the instruction itself.
 552                            This should never happen non-SMP
 553                         */
 554                         set_fs(oldfs);
 555                         goto uspace_segv;
 556                 }
 557
 558                 tmp = handle_unaligned_access(instruction, regs,
 559                                               &user_mem_access);
 560                 set_fs(oldfs);
 561
 562                 if (tmp==0)
 563                         return; /* sorted */
 564 uspace_segv:
 565                 printk(KERN_NOTICE "Sending SIGBUS to \"%s\" due to unaligned "
 566                        "access (PC %lx PR %lx)\n", current->comm, regs->pc,
 567                        regs->pr);
 568
 569                 info.si_signo = SIGBUS;
 570                 info.si_errno = 0;
 571                 info.si_code = si_code;
 572                 info.si_addr = (void __user *)address;
 573                 force_sig_info(SIGBUS, &info, current);
 574         } else {
 575                 if (regs->pc & 1)
 576                         die("unaligned program counter", regs, error_code);
 577
 578                 set_fs(KERNEL_DS);
 579                 if (copy_from_user(&instruction, (void __user *)(regs->pc),
 580                                    sizeof(instruction))) {
 581                         /* Argh. Fault on the instruction itself.
 582                            This should never happen non-SMP
 583                         */
 584                         set_fs(oldfs);
 585                         die("insn faulting in do_address_error", regs, 0);
 586                 }
 587
 588                 handle_unaligned_access(instruction, regs, &user_mem_access);
 589                 set_fs(oldfs);
 590         }
 591 }
 592
 593 #ifdef CONFIG_SH_DSP
 594 /*
 595  *      SH-DSP support gerg@snapgear.com.
 596  */
 597 int is_dsp_inst(struct pt_regs *regs)
 598 {
 599         unsigned short inst = 0;
 600
 601         /*
 602          * Safe guard if DSP mode is already enabled or we're lacking
 603          * the DSP altogether.
 604          */
 605         if (!(current_cpu_data.flags & CPU_HAS_DSP) || (regs->sr & SR_DSP))
 606                 return 0;
 607
 608         get_user(inst, ((unsigned short *) regs->pc));
 609
 610         inst &= 0xf000;
 611
 612         /* Check for any type of DSP or support instruction */
 613         if ((inst == 0xf000) || (inst == 0x4000))
 614                 return 1;
 615
 616         return 0;
 617 }
 618 #else
 619 #define is_dsp_inst(regs)       (0)
 620 #endif /* CONFIG_SH_DSP */
 621
 622 #ifdef CONFIG_CPU_SH2A
 623 asmlinkage void do_divide_error(unsigned long r4, unsigned long r5,
 624                                 unsigned long r6, unsigned long r7,
 625                                 struct pt_regs __regs)
 626 {
 627         siginfo_t info;
 628
 629         switch (r4) {
 630         case TRAP_DIVZERO_ERROR:
 631                 info.si_code = FPE_INTDIV;
 632                 break;
 633         case TRAP_DIVOVF_ERROR:
 634                 info.si_code = FPE_INTOVF;
 635                 break;
 636         }
 637
 638         force_sig_info(SIGFPE, &info, current);
 639 }
 640 #endif
 641
 642 asmlinkage void do_reserved_inst(unsigned long r4, unsigned long r5,
 643                                 unsigned long r6, unsigned long r7,
 644                                 struct pt_regs __regs)
 645 {
 646         struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
 647         unsigned long error_code;
 648         struct task_struct *tsk = current;
 649
 650 #ifdef CONFIG_SH_FPU_EMU
 651         unsigned short inst = 0;
 652         int err;
 653
 654         get_user(inst, (unsigned short*)regs->pc);
 655
 656         err = do_fpu_inst(inst, regs);
 657         if (!err) {
 658                 regs->pc += instruction_size(inst);
 659                 return;
 660         }
 661         /* not a FPU inst. */
 662 #endif
 663
 664 #ifdef CONFIG_SH_DSP
 665         /* Check if it's a DSP instruction */
 666         if (is_dsp_inst(regs)) {
 667                 /* Enable DSP mode, and restart instruction. */
 668                 regs->sr |= SR_DSP;
 669                 /* Save DSP mode */
 670                 tsk->thread.dsp_status.status |= SR_DSP;
 671                 return;
 672         }
 673 #endif
 674
 675         error_code = lookup_exception_vector();
 676
 677         local_irq_enable();
 678         force_sig(SIGILL, tsk);
 679         die_if_no_fixup("reserved instruction", regs, error_code);
 680 }
 681
 682 #ifdef CONFIG_SH_FPU_EMU
 683 static int emulate_branch(unsigned short inst, struct pt_regs *regs)
 684 {
 685         /*
 686          * bfs: 8fxx: PC+=d*2+4;
 687          * bts: 8dxx: PC+=d*2+4;
 688          * bra: axxx: PC+=D*2+4;
 689          * bsr: bxxx: PC+=D*2+4  after PR=PC+4;
 690          * braf:0x23: PC+=Rn*2+4;
 691          * bsrf:0x03: PC+=Rn*2+4 after PR=PC+4;
 692          * jmp: 4x2b: PC=Rn;
 693          * jsr: 4x0b: PC=Rn      after PR=PC+4;
 694          * rts: 000b: PC=PR;
 695          */
 696         if (((inst & 0xf000) == 0xb000)  ||     /* bsr */
 697             ((inst & 0xf0ff) == 0x0003)  ||     /* bsrf */
 698             ((inst & 0xf0ff) == 0x400b))        /* jsr */
 699                 regs->pr = regs->pc + 4;
 700
 701         if ((inst & 0xfd00) == 0x8d00) {        /* bfs, bts */
 702                 regs->pc += SH_PC_8BIT_OFFSET(inst);
 703                 return 0;
 704         }
 705
 706         if ((inst & 0xe000) == 0xa000) {        /* bra, bsr */
 707                 regs->pc += SH_PC_12BIT_OFFSET(inst);
 708                 return 0;
 709         }
 710
 711         if ((inst & 0xf0df) == 0x0003) {        /* braf, bsrf */
 712                 regs->pc += regs->regs[(inst & 0x0f00) >> 8] + 4;
 713                 return 0;
 714         }
 715
 716         if ((inst & 0xf0df) == 0x400b) {        /* jmp, jsr */
 717                 regs->pc = regs->regs[(inst & 0x0f00) >> 8];
 718                 return 0;
 719         }
 720
 721         if ((inst & 0xffff) == 0x000b) {        /* rts */
 722                 regs->pc = regs->pr;
 723                 return 0;
 724         }
 725
 726         return 1;
 727 }
 728 #endif
 729
 730 asmlinkage void do_illegal_slot_inst(unsigned long r4, unsigned long r5,
 731                                 unsigned long r6, unsigned long r7,
 732                                 struct pt_regs __regs)
 733 {
 734         struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
 735         unsigned long inst;
 736         struct task_struct *tsk = current;
 737
 738         if (kprobe_handle_illslot(regs->pc) == 0)
 739                 return;
 740
 741 #ifdef CONFIG_SH_FPU_EMU
 742         get_user(inst, (unsigned short *)regs->pc + 1);
 743         if (!do_fpu_inst(inst, regs)) {
 744                 get_user(inst, (unsigned short *)regs->pc);
 745                 if (!emulate_branch(inst, regs))
 746                         return;
 747                 /* fault in branch.*/
 748         }
 749         /* not a FPU inst. */
 750 #endif
 751
 752         inst = lookup_exception_vector();
 753
 754         local_irq_enable();
 755         force_sig(SIGILL, tsk);
 756         die_if_no_fixup("illegal slot instruction", regs, inst);
 757 }
 758
 759 asmlinkage void do_exception_error(unsigned long r4, unsigned long r5,
 760                                    unsigned long r6, unsigned long r7,
 761                                    struct pt_regs __regs)
 762 {
 763         struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
 764         long ex;
 765
 766         ex = lookup_exception_vector();
 767         die_if_kernel("exception", regs, ex);
 768 }
 769
 770 #if defined(CONFIG_SH_STANDARD_BIOS)
 771 void *gdb_vbr_vector;
 772
 773 static inline void __init gdb_vbr_init(void)
 774 {
 775         register unsigned long vbr;
 776
 777         /*
 778          * Read the old value of the VBR register to initialise
 779          * the vector through which debug and BIOS traps are
 780          * delegated by the Linux trap handler.
 781          */
 782         asm volatile("stc vbr, %0" : "=r" (vbr));
 783
 784         gdb_vbr_vector = (void *)(vbr + 0x100);
 785         printk("Setting GDB trap vector to 0x%08lx\n",
 786                (unsigned long)gdb_vbr_vector);
 787 }
 788 #endif
 789
 790 void __cpuinit per_cpu_trap_init(void)
 791 {
 792         extern void *vbr_base;
 793
 794 #ifdef CONFIG_SH_STANDARD_BIOS
 795         if (raw_smp_processor_id() == 0)
 796                 gdb_vbr_init();
 797 #endif
 798
 799         /* NOTE: The VBR value should be at P1
 800            (or P2, virtural "fixed" address space).
 801            It's definitely should not in physical address.  */
 802
 803         asm volatile("ldc       %0, vbr"
 804                      : /* no output */
 805                      : "r" (&vbr_base)
 806                      : "memory");
 807 }
 808
 809 void *set_exception_table_vec(unsigned int vec, void *handler)
 810 {
 811         extern void *exception_handling_table[];
 812         void *old_handler;
 813
 814         old_handler = exception_handling_table[vec];
 815         exception_handling_table[vec] = handler;
 816         return old_handler;
 817 }
 818
 819 void __init trap_init(void)
 820 {
 821         set_exception_table_vec(TRAP_RESERVED_INST, do_reserved_inst);
 822         set_exception_table_vec(TRAP_ILLEGAL_SLOT_INST, do_illegal_slot_inst);
 823
 824 #if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_FPU) || \
 825     defined(CONFIG_SH_FPU_EMU)
 826         /*
 827          * For SH-4 lacking an FPU, treat floating point instructions as
 828          * reserved. They'll be handled in the math-emu case, or faulted on
 829          * otherwise.
 830          */
 831         set_exception_table_evt(0x800, do_reserved_inst);
 832         set_exception_table_evt(0x820, do_illegal_slot_inst);
 833 #elif defined(CONFIG_SH_FPU)
 834 #ifdef CONFIG_CPU_SUBTYPE_SHX3
 835         set_exception_table_evt(0xd80, fpu_state_restore_trap_handler);
 836         set_exception_table_evt(0xda0, fpu_state_restore_trap_handler);
 837 #else
 838         set_exception_table_evt(0x800, fpu_state_restore_trap_handler);
 839         set_exception_table_evt(0x820, fpu_state_restore_trap_handler);
 840 #endif
 841 #endif
 842
 843 #ifdef CONFIG_CPU_SH2
 844         set_exception_table_vec(TRAP_ADDRESS_ERROR, address_error_trap_handler);
 845 #endif
 846 #ifdef CONFIG_CPU_SH2A
 847         set_exception_table_vec(TRAP_DIVZERO_ERROR, do_divide_error);
 848         set_exception_table_vec(TRAP_DIVOVF_ERROR, do_divide_error);
 849 #ifdef CONFIG_SH_FPU
 850         set_exception_table_vec(TRAP_FPU_ERROR, fpu_error_trap_handler);
 851 #endif
 852 #endif
 853
 854 #ifdef TRAP_UBC
 855         set_exception_table_vec(TRAP_UBC, break_point_trap);
 856 #endif
 857
 858         /* Setup VBR for boot cpu */
 859         per_cpu_trap_init();
 860 }
 861
 862 void show_stack(struct task_struct *tsk, unsigned long *sp)
 863 {
 864         unsigned long stack;
 865
 866         if (!tsk)
 867                 tsk = current;
 868         if (tsk == current)
 869                 sp = (unsigned long *)current_stack_pointer;
 870         else
 871                 sp = (unsigned long *)tsk->thread.sp;
 872
 873         stack = (unsigned long)sp;
 874         dump_mem("Stack: ", stack, THREAD_SIZE +
 875                  (unsigned long)task_stack_page(tsk));
 876         show_trace(tsk, sp, NULL);
 877 }
 878
 879 void dump_stack(void)
 880 {
 881         show_stack(NULL, NULL);
 882 }
 883 EXPORT_SYMBOL(dump_stack);