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   1 /*
   2  * 'traps.c' handles hardware traps and faults after we have saved some
   3  * state in 'entry.S'.
   4  *
   5  *  SuperH version: Copyright (C) 1999 Niibe Yutaka
   6  *                  Copyright (C) 2000 Philipp Rumpf
   7  *                  Copyright (C) 2000 David Howells
   8  *                  Copyright (C) 2002 - 2007 Paul Mundt
   9  *
  10  * This file is subject to the terms and conditions of the GNU General Public
  11  * License.  See the file "COPYING" in the main directory of this archive
  12  * for more details.
  13  */
  14 #include <linux/kernel.h>
  15 #include <linux/ptrace.h>
  16 #include <linux/hardirq.h>
  17 #include <linux/init.h>
  18 #include <linux/spinlock.h>
  19 #include <linux/module.h>
  20 #include <linux/kallsyms.h>
  21 #include <linux/io.h>
  22 #include <linux/bug.h>
  23 #include <linux/debug_locks.h>
  24 #include <linux/kdebug.h>
  25 #include <linux/kexec.h>
  26 #include <linux/limits.h>
  27 #include <asm/system.h>
  28 #include <asm/uaccess.h>
  29 #include <asm/fpu.h>
  30 #include <asm/kprobes.h>
  31
  32 #ifdef CONFIG_CPU_SH2
  33 # define TRAP_RESERVED_INST     4
  34 # define TRAP_ILLEGAL_SLOT_INST 6
  35 # define TRAP_ADDRESS_ERROR     9
  36 # ifdef CONFIG_CPU_SH2A
  37 #  define TRAP_UBC              12
  38 #  define TRAP_FPU_ERROR        13
  39 #  define TRAP_DIVZERO_ERROR    17
  40 #  define TRAP_DIVOVF_ERROR     18
  41 # endif
  42 #else
  43 #define TRAP_RESERVED_INST      12
  44 #define TRAP_ILLEGAL_SLOT_INST  13
  45 #endif
  46
  47 static void dump_mem(const char *str, unsigned long bottom, unsigned long top)
  48 {
  49         unsigned long p;
  50         int i;
  51
  52         printk("%s(0x%08lx to 0x%08lx)\n", str, bottom, top);
  53
  54         for (p = bottom & ~31; p < top; ) {
  55                 printk("%04lx: ", p & 0xffff);
  56
  57                 for (i = 0; i < 8; i++, p += 4) {
  58                         unsigned int val;
  59
  60                         if (p < bottom || p >= top)
  61                                 printk("         ");
  62                         else {
  63                                 if (__get_user(val, (unsigned int __user *)p)) {
  64                                         printk("\n");
  65                                         return;
  66                                 }
  67                                 printk("%08x ", val);
  68                         }
  69                 }
  70                 printk("\n");
  71         }
  72 }
  73
  74 static DEFINE_SPINLOCK(die_lock);
  75
  76 void die(const char * str, struct pt_regs * regs, long err)
  77 {
  78         static int die_counter;
  79
  80         oops_enter();
  81
  82         console_verbose();
  83         spin_lock_irq(&die_lock);
  84         bust_spinlocks(1);
  85
  86         printk("%s: %04lx [#%d]\n", str, err & 0xffff, ++die_counter);
  87
  88         print_modules();
  89         show_regs(regs);
  90
  91         printk("Process: %s (pid: %d, stack limit = %p)\n", current->comm,
  92                         task_pid_nr(current), task_stack_page(current) + 1);
  93
  94         if (!user_mode(regs) || in_interrupt())
  95                 dump_mem("Stack: ", regs->regs[15], THREAD_SIZE +
  96                          (unsigned long)task_stack_page(current));
  97
  98         notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV);
  99
 100         bust_spinlocks(0);
 101         add_taint(TAINT_DIE);
 102         spin_unlock_irq(&die_lock);
 103
 104         if (kexec_should_crash(current))
 105                 crash_kexec(regs);
 106
 107         if (in_interrupt())
 108                 panic("Fatal exception in interrupt");
 109
 110         if (panic_on_oops)
 111                 panic("Fatal exception");
 112
 113         oops_exit();
 114         do_exit(SIGSEGV);
 115 }
 116
 117 static inline void die_if_kernel(const char *str, struct pt_regs *regs,
 118                                  long err)
 119 {
 120         if (!user_mode(regs))
 121                 die(str, regs, err);
 122 }
 123
 124 /*
 125  * try and fix up kernelspace address errors
 126  * - userspace errors just cause EFAULT to be returned, resulting in SEGV
 127  * - kernel/userspace interfaces cause a jump to an appropriate handler
 128  * - other kernel errors are bad
 129  */
 130 static void die_if_no_fixup(const char * str, struct pt_regs * regs, long err)
 131 {
 132         if (!user_mode(regs)) {
 133                 const struct exception_table_entry *fixup;
 134                 fixup = search_exception_tables(regs->pc);
 135                 if (fixup) {
 136                         regs->pc = fixup->fixup;
 137                         return;
 138                 }
 139
 140                 die(str, regs, err);
 141         }
 142 }
 143
 144 static inline void sign_extend(unsigned int count, unsigned char *dst)
 145 {
 146 #ifdef __LITTLE_ENDIAN__
 147         if ((count == 1) && dst[0] & 0x80) {
 148                 dst[1] = 0xff;
 149                 dst[2] = 0xff;
 150                 dst[3] = 0xff;
 151         }
 152         if ((count == 2) && dst[1] & 0x80) {
 153                 dst[2] = 0xff;
 154                 dst[3] = 0xff;
 155         }
 156 #else
 157         if ((count == 1) && dst[3] & 0x80) {
 158                 dst[2] = 0xff;
 159                 dst[1] = 0xff;
 160                 dst[0] = 0xff;
 161         }
 162         if ((count == 2) && dst[2] & 0x80) {
 163                 dst[1] = 0xff;
 164                 dst[0] = 0xff;
 165         }
 166 #endif
 167 }
 168
 169 static struct mem_access user_mem_access = {
 170         copy_from_user,
 171         copy_to_user,
 172 };
 173
 174 /*
 175  * handle an instruction that does an unaligned memory access by emulating the
 176  * desired behaviour
 177  * - note that PC _may not_ point to the faulting instruction
 178  *   (if that instruction is in a branch delay slot)
 179  * - return 0 if emulation okay, -EFAULT on existential error
 180  */
 181 static int handle_unaligned_ins(insn_size_t instruction, struct pt_regs *regs,
 182                                 struct mem_access *ma)
 183 {
 184         int ret, index, count;
 185         unsigned long *rm, *rn;
 186         unsigned char *src, *dst;
 187         unsigned char __user *srcu, *dstu;
 188
 189         index = (instruction>>8)&15;    /* 0x0F00 */
 190         rn = &regs->regs[index];
 191
 192         index = (instruction>>4)&15;    /* 0x00F0 */
 193         rm = &regs->regs[index];
 194
 195         count = 1<<(instruction&3);
 196
 197         ret = -EFAULT;
 198         switch (instruction>>12) {
 199         case 0: /* mov.[bwl] to/from memory via r0+rn */
 200                 if (instruction & 8) {
 201                         /* from memory */
 202                         srcu = (unsigned char __user *)*rm;
 203                         srcu += regs->regs[0];
 204                         dst = (unsigned char *)rn;
 205                         *(unsigned long *)dst = 0;
 206
 207 #if !defined(__LITTLE_ENDIAN__)
 208                         dst += 4-count;
 209 #endif
 210                         if (ma->from(dst, srcu, count))
 211                                 goto fetch_fault;
 212
 213                         sign_extend(count, dst);
 214                 } else {
 215                         /* to memory */
 216                         src = (unsigned char *)rm;
 217 #if !defined(__LITTLE_ENDIAN__)
 218                         src += 4-count;
 219 #endif
 220                         dstu = (unsigned char __user *)*rn;
 221                         dstu += regs->regs[0];
 222
 223                         if (ma->to(dstu, src, count))
 224                                 goto fetch_fault;
 225                 }
 226                 ret = 0;
 227                 break;
 228
 229         case 1: /* mov.l Rm,@(disp,Rn) */
 230                 src = (unsigned char*) rm;
 231                 dstu = (unsigned char __user *)*rn;
 232                 dstu += (instruction&0x000F)<<2;
 233
 234                 if (ma->to(dstu, src, 4))
 235                         goto fetch_fault;
 236                 ret = 0;
 237                 break;
 238
 239         case 2: /* mov.[bwl] to memory, possibly with pre-decrement */
 240                 if (instruction & 4)
 241                         *rn -= count;
 242                 src = (unsigned char*) rm;
 243                 dstu = (unsigned char __user *)*rn;
 244 #if !defined(__LITTLE_ENDIAN__)
 245                 src += 4-count;
 246 #endif
 247                 if (ma->to(dstu, src, count))
 248                         goto fetch_fault;
 249                 ret = 0;
 250                 break;
 251
 252         case 5: /* mov.l @(disp,Rm),Rn */
 253                 srcu = (unsigned char __user *)*rm;
 254                 srcu += (instruction & 0x000F) << 2;
 255                 dst = (unsigned char *)rn;
 256                 *(unsigned long *)dst = 0;
 257
 258                 if (ma->from(dst, srcu, 4))
 259                         goto fetch_fault;
 260                 ret = 0;
 261                 break;
 262
 263         case 6: /* mov.[bwl] from memory, possibly with post-increment */
 264                 srcu = (unsigned char __user *)*rm;
 265                 if (instruction & 4)
 266                         *rm += count;
 267                 dst = (unsigned char*) rn;
 268                 *(unsigned long*)dst = 0;
 269
 270 #if !defined(__LITTLE_ENDIAN__)
 271                 dst += 4-count;
 272 #endif
 273                 if (ma->from(dst, srcu, count))
 274                         goto fetch_fault;
 275                 sign_extend(count, dst);
 276                 ret = 0;
 277                 break;
 278
 279         case 8:
 280                 switch ((instruction&0xFF00)>>8) {
 281                 case 0x81: /* mov.w R0,@(disp,Rn) */
 282                         src = (unsigned char *) &regs->regs[0];
 283 #if !defined(__LITTLE_ENDIAN__)
 284                         src += 2;
 285 #endif
 286                         dstu = (unsigned char __user *)*rm; /* called Rn in the spec */
 287                         dstu += (instruction & 0x000F) << 1;
 288
 289                         if (ma->to(dstu, src, 2))
 290                                 goto fetch_fault;
 291                         ret = 0;
 292                         break;
 293
 294                 case 0x85: /* mov.w @(disp,Rm),R0 */
 295                         srcu = (unsigned char __user *)*rm;
 296                         srcu += (instruction & 0x000F) << 1;
 297                         dst = (unsigned char *) &regs->regs[0];
 298                         *(unsigned long *)dst = 0;
 299
 300 #if !defined(__LITTLE_ENDIAN__)
 301                         dst += 2;
 302 #endif
 303                         if (ma->from(dst, srcu, 2))
 304                                 goto fetch_fault;
 305                         sign_extend(2, dst);
 306                         ret = 0;
 307                         break;
 308                 }
 309                 break;
 310         }
 311         return ret;
 312
 313  fetch_fault:
 314         /* Argh. Address not only misaligned but also non-existent.
 315          * Raise an EFAULT and see if it's trapped
 316          */
 317         die_if_no_fixup("Fault in unaligned fixup", regs, 0);
 318         return -EFAULT;
 319 }
 320
 321 /*
 322  * emulate the instruction in the delay slot
 323  * - fetches the instruction from PC+2
 324  */
 325 static inline int handle_delayslot(struct pt_regs *regs,
 326                                    insn_size_t old_instruction,
 327                                    struct mem_access *ma)
 328 {
 329         insn_size_t instruction;
 330         void __user *addr = (void __user *)(regs->pc +
 331                 instruction_size(old_instruction));
 332
 333         if (copy_from_user(&instruction, addr, sizeof(instruction))) {
 334                 /* the instruction-fetch faulted */
 335                 if (user_mode(regs))
 336                         return -EFAULT;
 337
 338                 /* kernel */
 339                 die("delay-slot-insn faulting in handle_unaligned_delayslot",
 340                     regs, 0);
 341         }
 342
 343         return handle_unaligned_ins(instruction, regs, ma);
 344 }
 345
 346 /*
 347  * handle an instruction that does an unaligned memory access
 348  * - have to be careful of branch delay-slot instructions that fault
 349  *  SH3:
 350  *   - if the branch would be taken PC points to the branch
 351  *   - if the branch would not be taken, PC points to delay-slot
 352  *  SH4:
 353  *   - PC always points to delayed branch
 354  * - return 0 if handled, -EFAULT if failed (may not return if in kernel)
 355  */
 356
 357 /* Macros to determine offset from current PC for branch instructions */
 358 /* Explicit type coercion is used to force sign extension where needed */
 359 #define SH_PC_8BIT_OFFSET(instr) ((((signed char)(instr))*2) + 4)
 360 #define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4)
 361
 362 int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs,
 363                             struct mem_access *ma)
 364 {
 365         u_int rm;
 366         int ret, index;
 367
 368         index = (instruction>>8)&15;    /* 0x0F00 */
 369         rm = regs->regs[index];
 370
 371         /* shout about fixups */
 372         if (printk_ratelimit())
 373                 printk(KERN_NOTICE "Fixing up unaligned %s access "
 374                        "in \"%s\" pid=%d pc=0x%p ins=0x%04hx\n",
 375                        user_mode(regs) ? "userspace" : "kernel",
 376                        current->comm, task_pid_nr(current),
 377                        (void *)regs->pc, instruction);
 378
 379         ret = -EFAULT;
 380         switch (instruction&0xF000) {
 381         case 0x0000:
 382                 if (instruction==0x000B) {
 383                         /* rts */
 384                         ret = handle_delayslot(regs, instruction, ma);
 385                         if (ret==0)
 386                                 regs->pc = regs->pr;
 387                 }
 388                 else if ((instruction&0x00FF)==0x0023) {
 389                         /* braf @Rm */
 390                         ret = handle_delayslot(regs, instruction, ma);
 391                         if (ret==0)
 392                                 regs->pc += rm + 4;
 393                 }
 394                 else if ((instruction&0x00FF)==0x0003) {
 395                         /* bsrf @Rm */
 396                         ret = handle_delayslot(regs, instruction, ma);
 397                         if (ret==0) {
 398                                 regs->pr = regs->pc + 4;
 399                                 regs->pc += rm + 4;
 400                         }
 401                 }
 402                 else {
 403                         /* mov.[bwl] to/from memory via r0+rn */
 404                         goto simple;
 405                 }
 406                 break;
 407
 408         case 0x1000: /* mov.l Rm,@(disp,Rn) */
 409                 goto simple;
 410
 411         case 0x2000: /* mov.[bwl] to memory, possibly with pre-decrement */
 412                 goto simple;
 413
 414         case 0x4000:
 415                 if ((instruction&0x00FF)==0x002B) {
 416                         /* jmp @Rm */
 417                         ret = handle_delayslot(regs, instruction, ma);
 418                         if (ret==0)
 419                                 regs->pc = rm;
 420                 }
 421                 else if ((instruction&0x00FF)==0x000B) {
 422                         /* jsr @Rm */
 423                         ret = handle_delayslot(regs, instruction, ma);
 424                         if (ret==0) {
 425                                 regs->pr = regs->pc + 4;
 426                                 regs->pc = rm;
 427                         }
 428                 }
 429                 else {
 430                         /* mov.[bwl] to/from memory via r0+rn */
 431                         goto simple;
 432                 }
 433                 break;
 434
 435         case 0x5000: /* mov.l @(disp,Rm),Rn */
 436                 goto simple;
 437
 438         case 0x6000: /* mov.[bwl] from memory, possibly with post-increment */
 439                 goto simple;
 440
 441         case 0x8000: /* bf lab, bf/s lab, bt lab, bt/s lab */
 442                 switch (instruction&0x0F00) {
 443                 case 0x0100: /* mov.w R0,@(disp,Rm) */
 444                         goto simple;
 445                 case 0x0500: /* mov.w @(disp,Rm),R0 */
 446                         goto simple;
 447                 case 0x0B00: /* bf   lab - no delayslot*/
 448                         break;
 449                 case 0x0F00: /* bf/s lab */
 450                         ret = handle_delayslot(regs, instruction, ma);
 451                         if (ret==0) {
 452 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
 453                                 if ((regs->sr & 0x00000001) != 0)
 454                                         regs->pc += 4; /* next after slot */
 455                                 else
 456 #endif
 457                                         regs->pc += SH_PC_8BIT_OFFSET(instruction);
 458                         }
 459                         break;
 460                 case 0x0900: /* bt   lab - no delayslot */
 461                         break;
 462                 case 0x0D00: /* bt/s lab */
 463                         ret = handle_delayslot(regs, instruction, ma);
 464                         if (ret==0) {
 465 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
 466                                 if ((regs->sr & 0x00000001) == 0)
 467                                         regs->pc += 4; /* next after slot */
 468                                 else
 469 #endif
 470                                         regs->pc += SH_PC_8BIT_OFFSET(instruction);
 471                         }
 472                         break;
 473                 }
 474                 break;
 475
 476         case 0xA000: /* bra label */
 477                 ret = handle_delayslot(regs, instruction, ma);
 478                 if (ret==0)
 479                         regs->pc += SH_PC_12BIT_OFFSET(instruction);
 480                 break;
 481
 482         case 0xB000: /* bsr label */
 483                 ret = handle_delayslot(regs, instruction, ma);
 484                 if (ret==0) {
 485                         regs->pr = regs->pc + 4;
 486                         regs->pc += SH_PC_12BIT_OFFSET(instruction);
 487                 }
 488                 break;
 489         }
 490         return ret;
 491
 492         /* handle non-delay-slot instruction */
 493  simple:
 494         ret = handle_unaligned_ins(instruction, regs, ma);
 495         if (ret==0)
 496                 regs->pc += instruction_size(instruction);
 497         return ret;
 498 }
 499
 500 /*
 501  * Handle various address error exceptions:
 502  *  - instruction address error:
 503  *       misaligned PC
 504  *       PC >= 0x80000000 in user mode
 505  *  - data address error (read and write)
 506  *       misaligned data access
 507  *       access to >= 0x80000000 is user mode
 508  * Unfortuntaly we can't distinguish between instruction address error
 509  * and data address errors caused by read accesses.
 510  */
 511 asmlinkage void do_address_error(struct pt_regs *regs,
 512                                  unsigned long writeaccess,
 513                                  unsigned long address)
 514 {
 515         unsigned long error_code = 0;
 516         mm_segment_t oldfs;
 517         siginfo_t info;
 518         insn_size_t instruction;
 519         int tmp;
 520
 521         /* Intentional ifdef */
 522 #ifdef CONFIG_CPU_HAS_SR_RB
 523         error_code = lookup_exception_vector();
 524 #endif
 525
 526         oldfs = get_fs();
 527
 528         if (user_mode(regs)) {
 529                 int si_code = BUS_ADRERR;
 530
 531                 local_irq_enable();
 532
 533                 /* bad PC is not something we can fix */
 534                 if (regs->pc & 1) {
 535                         si_code = BUS_ADRALN;
 536                         goto uspace_segv;
 537                 }
 538
 539                 set_fs(USER_DS);
 540                 if (copy_from_user(&instruction, (void __user *)(regs->pc),
 541                                    sizeof(instruction))) {
 542                         /* Argh. Fault on the instruction itself.
 543                            This should never happen non-SMP
 544                         */
 545                         set_fs(oldfs);
 546                         goto uspace_segv;
 547                 }
 548
 549                 tmp = handle_unaligned_access(instruction, regs,
 550                                               &user_mem_access);
 551                 set_fs(oldfs);
 552
 553                 if (tmp==0)
 554                         return; /* sorted */
 555 uspace_segv:
 556                 printk(KERN_NOTICE "Sending SIGBUS to \"%s\" due to unaligned "
 557                        "access (PC %lx PR %lx)\n", current->comm, regs->pc,
 558                        regs->pr);
 559
 560                 info.si_signo = SIGBUS;
 561                 info.si_errno = 0;
 562                 info.si_code = si_code;
 563                 info.si_addr = (void __user *)address;
 564                 force_sig_info(SIGBUS, &info, current);
 565         } else {
 566                 if (regs->pc & 1)
 567                         die("unaligned program counter", regs, error_code);
 568
 569                 set_fs(KERNEL_DS);
 570                 if (copy_from_user(&instruction, (void __user *)(regs->pc),
 571                                    sizeof(instruction))) {
 572                         /* Argh. Fault on the instruction itself.
 573                            This should never happen non-SMP
 574                         */
 575                         set_fs(oldfs);
 576                         die("insn faulting in do_address_error", regs, 0);
 577                 }
 578
 579                 handle_unaligned_access(instruction, regs, &user_mem_access);
 580                 set_fs(oldfs);
 581         }
 582 }
 583
 584 #ifdef CONFIG_SH_DSP
 585 /*
 586  *      SH-DSP support gerg@snapgear.com.
 587  */
 588 int is_dsp_inst(struct pt_regs *regs)
 589 {
 590         unsigned short inst = 0;
 591
 592         /*
 593          * Safe guard if DSP mode is already enabled or we're lacking
 594          * the DSP altogether.
 595          */
 596         if (!(current_cpu_data.flags & CPU_HAS_DSP) || (regs->sr & SR_DSP))
 597                 return 0;
 598
 599         get_user(inst, ((unsigned short *) regs->pc));
 600
 601         inst &= 0xf000;
 602
 603         /* Check for any type of DSP or support instruction */
 604         if ((inst == 0xf000) || (inst == 0x4000))
 605                 return 1;
 606
 607         return 0;
 608 }
 609 #else
 610 #define is_dsp_inst(regs)       (0)
 611 #endif /* CONFIG_SH_DSP */
 612
 613 #ifdef CONFIG_CPU_SH2A
 614 asmlinkage void do_divide_error(unsigned long r4, unsigned long r5,
 615                                 unsigned long r6, unsigned long r7,
 616                                 struct pt_regs __regs)
 617 {
 618         siginfo_t info;
 619
 620         switch (r4) {
 621         case TRAP_DIVZERO_ERROR:
 622                 info.si_code = FPE_INTDIV;
 623                 break;
 624         case TRAP_DIVOVF_ERROR:
 625                 info.si_code = FPE_INTOVF;
 626                 break;
 627         }
 628
 629         force_sig_info(SIGFPE, &info, current);
 630 }
 631 #endif
 632
 633 asmlinkage void do_reserved_inst(unsigned long r4, unsigned long r5,
 634                                 unsigned long r6, unsigned long r7,
 635                                 struct pt_regs __regs)
 636 {
 637         struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
 638         unsigned long error_code;
 639         struct task_struct *tsk = current;
 640
 641 #ifdef CONFIG_SH_FPU_EMU
 642         unsigned short inst = 0;
 643         int err;
 644
 645         get_user(inst, (unsigned short*)regs->pc);
 646
 647         err = do_fpu_inst(inst, regs);
 648         if (!err) {
 649                 regs->pc += instruction_size(inst);
 650                 return;
 651         }
 652         /* not a FPU inst. */
 653 #endif
 654
 655 #ifdef CONFIG_SH_DSP
 656         /* Check if it's a DSP instruction */
 657         if (is_dsp_inst(regs)) {
 658                 /* Enable DSP mode, and restart instruction. */
 659                 regs->sr |= SR_DSP;
 660                 /* Save DSP mode */
 661                 tsk->thread.dsp_status.status |= SR_DSP;
 662                 return;
 663         }
 664 #endif
 665
 666         error_code = lookup_exception_vector();
 667
 668         local_irq_enable();
 669         force_sig(SIGILL, tsk);
 670         die_if_no_fixup("reserved instruction", regs, error_code);
 671 }
 672
 673 #ifdef CONFIG_SH_FPU_EMU
 674 static int emulate_branch(unsigned short inst, struct pt_regs *regs)
 675 {
 676         /*
 677          * bfs: 8fxx: PC+=d*2+4;
 678          * bts: 8dxx: PC+=d*2+4;
 679          * bra: axxx: PC+=D*2+4;
 680          * bsr: bxxx: PC+=D*2+4  after PR=PC+4;
 681          * braf:0x23: PC+=Rn*2+4;
 682          * bsrf:0x03: PC+=Rn*2+4 after PR=PC+4;
 683          * jmp: 4x2b: PC=Rn;
 684          * jsr: 4x0b: PC=Rn      after PR=PC+4;
 685          * rts: 000b: PC=PR;
 686          */
 687         if (((inst & 0xf000) == 0xb000)  ||     /* bsr */
 688             ((inst & 0xf0ff) == 0x0003)  ||     /* bsrf */
 689             ((inst & 0xf0ff) == 0x400b))        /* jsr */
 690                 regs->pr = regs->pc + 4;
 691
 692         if ((inst & 0xfd00) == 0x8d00) {        /* bfs, bts */
 693                 regs->pc += SH_PC_8BIT_OFFSET(inst);
 694                 return 0;
 695         }
 696
 697         if ((inst & 0xe000) == 0xa000) {        /* bra, bsr */
 698                 regs->pc += SH_PC_12BIT_OFFSET(inst);
 699                 return 0;
 700         }
 701
 702         if ((inst & 0xf0df) == 0x0003) {        /* braf, bsrf */
 703                 regs->pc += regs->regs[(inst & 0x0f00) >> 8] + 4;
 704                 return 0;
 705         }
 706
 707         if ((inst & 0xf0df) == 0x400b) {        /* jmp, jsr */
 708                 regs->pc = regs->regs[(inst & 0x0f00) >> 8];
 709                 return 0;
 710         }
 711
 712         if ((inst & 0xffff) == 0x000b) {        /* rts */
 713                 regs->pc = regs->pr;
 714                 return 0;
 715         }
 716
 717         return 1;
 718 }
 719 #endif
 720
 721 asmlinkage void do_illegal_slot_inst(unsigned long r4, unsigned long r5,
 722                                 unsigned long r6, unsigned long r7,
 723                                 struct pt_regs __regs)
 724 {
 725         struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
 726         unsigned long inst;
 727         struct task_struct *tsk = current;
 728
 729         if (kprobe_handle_illslot(regs->pc) == 0)
 730                 return;
 731
 732 #ifdef CONFIG_SH_FPU_EMU
 733         get_user(inst, (unsigned short *)regs->pc + 1);
 734         if (!do_fpu_inst(inst, regs)) {
 735                 get_user(inst, (unsigned short *)regs->pc);
 736                 if (!emulate_branch(inst, regs))
 737                         return;
 738                 /* fault in branch.*/
 739         }
 740         /* not a FPU inst. */
 741 #endif
 742
 743         inst = lookup_exception_vector();
 744
 745         local_irq_enable();
 746         force_sig(SIGILL, tsk);
 747         die_if_no_fixup("illegal slot instruction", regs, inst);
 748 }
 749
 750 asmlinkage void do_exception_error(unsigned long r4, unsigned long r5,
 751                                    unsigned long r6, unsigned long r7,
 752                                    struct pt_regs __regs)
 753 {
 754         struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
 755         long ex;
 756
 757         ex = lookup_exception_vector();
 758         die_if_kernel("exception", regs, ex);
 759 }
 760
 761 #if defined(CONFIG_SH_STANDARD_BIOS)
 762 void *gdb_vbr_vector;
 763
 764 static inline void __init gdb_vbr_init(void)
 765 {
 766         register unsigned long vbr;
 767
 768         /*
 769          * Read the old value of the VBR register to initialise
 770          * the vector through which debug and BIOS traps are
 771          * delegated by the Linux trap handler.
 772          */
 773         asm volatile("stc vbr, %0" : "=r" (vbr));
 774
 775         gdb_vbr_vector = (void *)(vbr + 0x100);
 776         printk("Setting GDB trap vector to 0x%08lx\n",
 777                (unsigned long)gdb_vbr_vector);
 778 }
 779 #endif
 780
 781 void __cpuinit per_cpu_trap_init(void)
 782 {
 783         extern void *vbr_base;
 784
 785 #ifdef CONFIG_SH_STANDARD_BIOS
 786         if (raw_smp_processor_id() == 0)
 787                 gdb_vbr_init();
 788 #endif
 789
 790         /* NOTE: The VBR value should be at P1
 791            (or P2, virtural "fixed" address space).
 792            It's definitely should not in physical address.  */
 793
 794         asm volatile("ldc       %0, vbr"
 795                      : /* no output */
 796                      : "r" (&vbr_base)
 797                      : "memory");
 798 }
 799
 800 void *set_exception_table_vec(unsigned int vec, void *handler)
 801 {
 802         extern void *exception_handling_table[];
 803         void *old_handler;
 804
 805         old_handler = exception_handling_table[vec];
 806         exception_handling_table[vec] = handler;
 807         return old_handler;
 808 }
 809
 810 void __init trap_init(void)
 811 {
 812         set_exception_table_vec(TRAP_RESERVED_INST, do_reserved_inst);
 813         set_exception_table_vec(TRAP_ILLEGAL_SLOT_INST, do_illegal_slot_inst);
 814
 815 #if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_FPU) || \
 816     defined(CONFIG_SH_FPU_EMU)
 817         /*
 818          * For SH-4 lacking an FPU, treat floating point instructions as
 819          * reserved. They'll be handled in the math-emu case, or faulted on
 820          * otherwise.
 821          */
 822         set_exception_table_evt(0x800, do_reserved_inst);
 823         set_exception_table_evt(0x820, do_illegal_slot_inst);
 824 #elif defined(CONFIG_SH_FPU)
 825 #ifdef CONFIG_CPU_SUBTYPE_SHX3
 826         set_exception_table_evt(0xd80, fpu_state_restore_trap_handler);
 827         set_exception_table_evt(0xda0, fpu_state_restore_trap_handler);
 828 #else
 829         set_exception_table_evt(0x800, fpu_state_restore_trap_handler);
 830         set_exception_table_evt(0x820, fpu_state_restore_trap_handler);
 831 #endif
 832 #endif
 833
 834 #ifdef CONFIG_CPU_SH2
 835         set_exception_table_vec(TRAP_ADDRESS_ERROR, address_error_trap_handler);
 836 #endif
 837 #ifdef CONFIG_CPU_SH2A
 838         set_exception_table_vec(TRAP_DIVZERO_ERROR, do_divide_error);
 839         set_exception_table_vec(TRAP_DIVOVF_ERROR, do_divide_error);
 840 #ifdef CONFIG_SH_FPU
 841         set_exception_table_vec(TRAP_FPU_ERROR, fpu_error_trap_handler);
 842 #endif
 843 #endif
 844
 845 #ifdef TRAP_UBC
 846         set_exception_table_vec(TRAP_UBC, break_point_trap);
 847 #endif
 848
 849         /* Setup VBR for boot cpu */
 850         per_cpu_trap_init();
 851 }
 852
 853 void show_stack(struct task_struct *tsk, unsigned long *sp)
 854 {
 855         unsigned long stack;
 856
 857         if (!tsk)
 858                 tsk = current;
 859         if (tsk == current)
 860                 sp = (unsigned long *)current_stack_pointer;
 861         else
 862                 sp = (unsigned long *)tsk->thread.sp;
 863
 864         stack = (unsigned long)sp;
 865         dump_mem("Stack: ", stack, THREAD_SIZE +
 866                  (unsigned long)task_stack_page(tsk));
 867         show_trace(tsk, sp, NULL);
 868 }
 869
 870 void dump_stack(void)
 871 {
 872         show_stack(NULL, NULL);
 873 }
 874 EXPORT_SYMBOL(dump_stack);