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   1 /*
   2  * 'traps.c' handles hardware traps and faults after we have saved some
   3  * state in 'entry.S'.
   4  *
   5  *  SuperH version: Copyright (C) 1999 Niibe Yutaka
   6  *                  Copyright (C) 2000 Philipp Rumpf
   7  *                  Copyright (C) 2000 David Howells
   8  *                  Copyright (C) 2002 - 2007 Paul Mundt
   9  *
  10  * This file is subject to the terms and conditions of the GNU General Public
  11  * License.  See the file "COPYING" in the main directory of this archive
  12  * for more details.
  13  */
  14 #include <linux/kernel.h>
  15 #include <linux/ptrace.h>
  16 #include <linux/init.h>
  17 #include <linux/spinlock.h>
  18 #include <linux/module.h>
  19 #include <linux/kallsyms.h>
  20 #include <linux/io.h>
  21 #include <linux/bug.h>
  22 #include <linux/debug_locks.h>
  23 #include <linux/kdebug.h>
  24 #include <linux/kexec.h>
  25 #include <linux/limits.h>
  26 #include <asm/system.h>
  27 #include <asm/uaccess.h>
  28 #include <asm/fpu.h>
  29
  30 #ifdef CONFIG_SH_KGDB
  31 #include <asm/kgdb.h>
  32 #define CHK_REMOTE_DEBUG(regs)                  \
  33 {                                               \
  34         if (kgdb_debug_hook && !user_mode(regs))\
  35                 (*kgdb_debug_hook)(regs);       \
  36 }
  37 #else
  38 #define CHK_REMOTE_DEBUG(regs)
  39 #endif
  40
  41 #ifdef CONFIG_CPU_SH2
  42 # define TRAP_RESERVED_INST     4
  43 # define TRAP_ILLEGAL_SLOT_INST 6
  44 # define TRAP_ADDRESS_ERROR     9
  45 # ifdef CONFIG_CPU_SH2A
  46 #  define TRAP_FPU_ERROR        13
  47 #  define TRAP_DIVZERO_ERROR    17
  48 #  define TRAP_DIVOVF_ERROR     18
  49 # endif
  50 #else
  51 #define TRAP_RESERVED_INST      12
  52 #define TRAP_ILLEGAL_SLOT_INST  13
  53 #endif
  54
  55 static void dump_mem(const char *str, unsigned long bottom, unsigned long top)
  56 {
  57         unsigned long p;
  58         int i;
  59
  60         printk("%s(0x%08lx to 0x%08lx)\n", str, bottom, top);
  61
  62         for (p = bottom & ~31; p < top; ) {
  63                 printk("%04lx: ", p & 0xffff);
  64
  65                 for (i = 0; i < 8; i++, p += 4) {
  66                         unsigned int val;
  67
  68                         if (p < bottom || p >= top)
  69                                 printk("         ");
  70                         else {
  71                                 if (__get_user(val, (unsigned int __user *)p)) {
  72                                         printk("\n");
  73                                         return;
  74                                 }
  75                                 printk("%08x ", val);
  76                         }
  77                 }
  78                 printk("\n");
  79         }
  80 }
  81
  82 static DEFINE_SPINLOCK(die_lock);
  83
  84 void die(const char * str, struct pt_regs * regs, long err)
  85 {
  86         static int die_counter;
  87
  88         oops_enter();
  89
  90         console_verbose();
  91         spin_lock_irq(&die_lock);
  92         bust_spinlocks(1);
  93
  94         printk("%s: %04lx [#%d]\n", str, err & 0xffff, ++die_counter);
  95
  96         CHK_REMOTE_DEBUG(regs);
  97         print_modules();
  98         show_regs(regs);
  99
 100         printk("Process: %s (pid: %d, stack limit = %p)\n", current->comm,
 101                         task_pid_nr(current), task_stack_page(current) + 1);
 102
 103         if (!user_mode(regs) || in_interrupt())
 104                 dump_mem("Stack: ", regs->regs[15], THREAD_SIZE +
 105                          (unsigned long)task_stack_page(current));
 106
 107         bust_spinlocks(0);
 108         add_taint(TAINT_DIE);
 109         spin_unlock_irq(&die_lock);
 110
 111         if (kexec_should_crash(current))
 112                 crash_kexec(regs);
 113
 114         if (in_interrupt())
 115                 panic("Fatal exception in interrupt");
 116
 117         if (panic_on_oops)
 118                 panic("Fatal exception");
 119
 120         oops_exit();
 121         do_exit(SIGSEGV);
 122 }
 123
 124 static inline void die_if_kernel(const char *str, struct pt_regs *regs,
 125                                  long err)
 126 {
 127         if (!user_mode(regs))
 128                 die(str, regs, err);
 129 }
 130
 131 /*
 132  * try and fix up kernelspace address errors
 133  * - userspace errors just cause EFAULT to be returned, resulting in SEGV
 134  * - kernel/userspace interfaces cause a jump to an appropriate handler
 135  * - other kernel errors are bad
 136  * - return 0 if fixed-up, -EFAULT if non-fatal (to the kernel) fault
 137  */
 138 static int die_if_no_fixup(const char * str, struct pt_regs * regs, long err)
 139 {
 140         if (!user_mode(regs)) {
 141                 const struct exception_table_entry *fixup;
 142                 fixup = search_exception_tables(regs->pc);
 143                 if (fixup) {
 144                         regs->pc = fixup->fixup;
 145                         return 0;
 146                 }
 147                 die(str, regs, err);
 148         }
 149         return -EFAULT;
 150 }
 151
 152 static inline void sign_extend(unsigned int count, unsigned char *dst)
 153 {
 154 #ifdef __LITTLE_ENDIAN__
 155         if ((count == 1) && dst[0] & 0x80) {
 156                 dst[1] = 0xff;
 157                 dst[2] = 0xff;
 158                 dst[3] = 0xff;
 159         }
 160         if ((count == 2) && dst[1] & 0x80) {
 161                 dst[2] = 0xff;
 162                 dst[3] = 0xff;
 163         }
 164 #else
 165         if ((count == 1) && dst[3] & 0x80) {
 166                 dst[2] = 0xff;
 167                 dst[1] = 0xff;
 168                 dst[0] = 0xff;
 169         }
 170         if ((count == 2) && dst[2] & 0x80) {
 171                 dst[1] = 0xff;
 172                 dst[0] = 0xff;
 173         }
 174 #endif
 175 }
 176
 177 static struct mem_access user_mem_access = {
 178         copy_from_user,
 179         copy_to_user,
 180 };
 181
 182 /*
 183  * handle an instruction that does an unaligned memory access by emulating the
 184  * desired behaviour
 185  * - note that PC _may not_ point to the faulting instruction
 186  *   (if that instruction is in a branch delay slot)
 187  * - return 0 if emulation okay, -EFAULT on existential error
 188  */
 189 static int handle_unaligned_ins(opcode_t instruction, struct pt_regs *regs,
 190                                 struct mem_access *ma)
 191 {
 192         int ret, index, count;
 193         unsigned long *rm, *rn;
 194         unsigned char *src, *dst;
 195
 196         index = (instruction>>8)&15;    /* 0x0F00 */
 197         rn = &regs->regs[index];
 198
 199         index = (instruction>>4)&15;    /* 0x00F0 */
 200         rm = &regs->regs[index];
 201
 202         count = 1<<(instruction&3);
 203
 204         ret = -EFAULT;
 205         switch (instruction>>12) {
 206         case 0: /* mov.[bwl] to/from memory via r0+rn */
 207                 if (instruction & 8) {
 208                         /* from memory */
 209                         src = (unsigned char*) *rm;
 210                         src += regs->regs[0];
 211                         dst = (unsigned char*) rn;
 212                         *(unsigned long*)dst = 0;
 213
 214 #if !defined(__LITTLE_ENDIAN__)
 215                         dst += 4-count;
 216 #endif
 217                         if (ma->from(dst, src, count))
 218                                 goto fetch_fault;
 219
 220                         sign_extend(count, dst);
 221                 } else {
 222                         /* to memory */
 223                         src = (unsigned char*) rm;
 224 #if !defined(__LITTLE_ENDIAN__)
 225                         src += 4-count;
 226 #endif
 227                         dst = (unsigned char*) *rn;
 228                         dst += regs->regs[0];
 229
 230                         if (ma->to(dst, src, count))
 231                                 goto fetch_fault;
 232                 }
 233                 ret = 0;
 234                 break;
 235
 236         case 1: /* mov.l Rm,@(disp,Rn) */
 237                 src = (unsigned char*) rm;
 238                 dst = (unsigned char*) *rn;
 239                 dst += (instruction&0x000F)<<2;
 240
 241                 if (ma->to(dst, src, 4))
 242                         goto fetch_fault;
 243                 ret = 0;
 244                 break;
 245
 246         case 2: /* mov.[bwl] to memory, possibly with pre-decrement */
 247                 if (instruction & 4)
 248                         *rn -= count;
 249                 src = (unsigned char*) rm;
 250                 dst = (unsigned char*) *rn;
 251 #if !defined(__LITTLE_ENDIAN__)
 252                 src += 4-count;
 253 #endif
 254                 if (ma->to(dst, src, count))
 255                         goto fetch_fault;
 256                 ret = 0;
 257                 break;
 258
 259         case 5: /* mov.l @(disp,Rm),Rn */
 260                 src = (unsigned char*) *rm;
 261                 src += (instruction&0x000F)<<2;
 262                 dst = (unsigned char*) rn;
 263                 *(unsigned long*)dst = 0;
 264
 265                 if (ma->from(dst, src, 4))
 266                         goto fetch_fault;
 267                 ret = 0;
 268                 break;
 269
 270         case 6: /* mov.[bwl] from memory, possibly with post-increment */
 271                 src = (unsigned char*) *rm;
 272                 if (instruction & 4)
 273                         *rm += count;
 274                 dst = (unsigned char*) rn;
 275                 *(unsigned long*)dst = 0;
 276
 277 #if !defined(__LITTLE_ENDIAN__)
 278                 dst += 4-count;
 279 #endif
 280                 if (ma->from(dst, src, count))
 281                         goto fetch_fault;
 282                 sign_extend(count, dst);
 283                 ret = 0;
 284                 break;
 285
 286         case 8:
 287                 switch ((instruction&0xFF00)>>8) {
 288                 case 0x81: /* mov.w R0,@(disp,Rn) */
 289                         src = (unsigned char*) &regs->regs[0];
 290 #if !defined(__LITTLE_ENDIAN__)
 291                         src += 2;
 292 #endif
 293                         dst = (unsigned char*) *rm; /* called Rn in the spec */
 294                         dst += (instruction&0x000F)<<1;
 295
 296                         if (ma->to(dst, src, 2))
 297                                 goto fetch_fault;
 298                         ret = 0;
 299                         break;
 300
 301                 case 0x85: /* mov.w @(disp,Rm),R0 */
 302                         src = (unsigned char*) *rm;
 303                         src += (instruction&0x000F)<<1;
 304                         dst = (unsigned char*) &regs->regs[0];
 305                         *(unsigned long*)dst = 0;
 306
 307 #if !defined(__LITTLE_ENDIAN__)
 308                         dst += 2;
 309 #endif
 310                         if (ma->from(dst, src, 2))
 311                                 goto fetch_fault;
 312                         sign_extend(2, dst);
 313                         ret = 0;
 314                         break;
 315                 }
 316                 break;
 317         }
 318         return ret;
 319
 320  fetch_fault:
 321         /* Argh. Address not only misaligned but also non-existent.
 322          * Raise an EFAULT and see if it's trapped
 323          */
 324         return die_if_no_fixup("Fault in unaligned fixup", regs, 0);
 325 }
 326
 327 /*
 328  * emulate the instruction in the delay slot
 329  * - fetches the instruction from PC+2
 330  */
 331 static inline int handle_delayslot(struct pt_regs *regs,
 332                                    opcode_t old_instruction,
 333                                    struct mem_access *ma)
 334 {
 335         opcode_t instruction;
 336         void *addr = (void *)(regs->pc + instruction_size(old_instruction));
 337
 338         if (copy_from_user(&instruction, addr, sizeof(instruction))) {
 339                 /* the instruction-fetch faulted */
 340                 if (user_mode(regs))
 341                         return -EFAULT;
 342
 343                 /* kernel */
 344                 die("delay-slot-insn faulting in handle_unaligned_delayslot",
 345                     regs, 0);
 346         }
 347
 348         return handle_unaligned_ins(instruction, regs, ma);
 349 }
 350
 351 /*
 352  * handle an instruction that does an unaligned memory access
 353  * - have to be careful of branch delay-slot instructions that fault
 354  *  SH3:
 355  *   - if the branch would be taken PC points to the branch
 356  *   - if the branch would not be taken, PC points to delay-slot
 357  *  SH4:
 358  *   - PC always points to delayed branch
 359  * - return 0 if handled, -EFAULT if failed (may not return if in kernel)
 360  */
 361
 362 /* Macros to determine offset from current PC for branch instructions */
 363 /* Explicit type coercion is used to force sign extension where needed */
 364 #define SH_PC_8BIT_OFFSET(instr) ((((signed char)(instr))*2) + 4)
 365 #define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4)
 366
 367 /*
 368  * XXX: SH-2A needs this too, but it needs an overhaul thanks to mixed 32-bit
 369  * opcodes..
 370  */
 371
 372 static int handle_unaligned_notify_count = 10;
 373
 374 int handle_unaligned_access(opcode_t instruction, struct pt_regs *regs,
 375                             struct mem_access *ma)
 376 {
 377         u_int rm;
 378         int ret, index;
 379
 380         index = (instruction>>8)&15;    /* 0x0F00 */
 381         rm = regs->regs[index];
 382
 383         /* shout about the first ten userspace fixups */
 384         if (user_mode(regs) && handle_unaligned_notify_count>0) {
 385                 handle_unaligned_notify_count--;
 386
 387                 printk(KERN_NOTICE "Fixing up unaligned userspace access "
 388                        "in \"%s\" pid=%d pc=0x%p ins=0x%04hx\n",
 389                        current->comm, task_pid_nr(current),
 390                        (void *)regs->pc, instruction);
 391         }
 392
 393         ret = -EFAULT;
 394         switch (instruction&0xF000) {
 395         case 0x0000:
 396                 if (instruction==0x000B) {
 397                         /* rts */
 398                         ret = handle_delayslot(regs, instruction, ma);
 399                         if (ret==0)
 400                                 regs->pc = regs->pr;
 401                 }
 402                 else if ((instruction&0x00FF)==0x0023) {
 403                         /* braf @Rm */
 404                         ret = handle_delayslot(regs, instruction, ma);
 405                         if (ret==0)
 406                                 regs->pc += rm + 4;
 407                 }
 408                 else if ((instruction&0x00FF)==0x0003) {
 409                         /* bsrf @Rm */
 410                         ret = handle_delayslot(regs, instruction, ma);
 411                         if (ret==0) {
 412                                 regs->pr = regs->pc + 4;
 413                                 regs->pc += rm + 4;
 414                         }
 415                 }
 416                 else {
 417                         /* mov.[bwl] to/from memory via r0+rn */
 418                         goto simple;
 419                 }
 420                 break;
 421
 422         case 0x1000: /* mov.l Rm,@(disp,Rn) */
 423                 goto simple;
 424
 425         case 0x2000: /* mov.[bwl] to memory, possibly with pre-decrement */
 426                 goto simple;
 427
 428         case 0x4000:
 429                 if ((instruction&0x00FF)==0x002B) {
 430                         /* jmp @Rm */
 431                         ret = handle_delayslot(regs, instruction, ma);
 432                         if (ret==0)
 433                                 regs->pc = rm;
 434                 }
 435                 else if ((instruction&0x00FF)==0x000B) {
 436                         /* jsr @Rm */
 437                         ret = handle_delayslot(regs, instruction, ma);
 438                         if (ret==0) {
 439                                 regs->pr = regs->pc + 4;
 440                                 regs->pc = rm;
 441                         }
 442                 }
 443                 else {
 444                         /* mov.[bwl] to/from memory via r0+rn */
 445                         goto simple;
 446                 }
 447                 break;
 448
 449         case 0x5000: /* mov.l @(disp,Rm),Rn */
 450                 goto simple;
 451
 452         case 0x6000: /* mov.[bwl] from memory, possibly with post-increment */
 453                 goto simple;
 454
 455         case 0x8000: /* bf lab, bf/s lab, bt lab, bt/s lab */
 456                 switch (instruction&0x0F00) {
 457                 case 0x0100: /* mov.w R0,@(disp,Rm) */
 458                         goto simple;
 459                 case 0x0500: /* mov.w @(disp,Rm),R0 */
 460                         goto simple;
 461                 case 0x0B00: /* bf   lab - no delayslot*/
 462                         break;
 463                 case 0x0F00: /* bf/s lab */
 464                         ret = handle_delayslot(regs, instruction, ma);
 465                         if (ret==0) {
 466 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
 467                                 if ((regs->sr & 0x00000001) != 0)
 468                                         regs->pc += 4; /* next after slot */
 469                                 else
 470 #endif
 471                                         regs->pc += SH_PC_8BIT_OFFSET(instruction);
 472                         }
 473                         break;
 474                 case 0x0900: /* bt   lab - no delayslot */
 475                         break;
 476                 case 0x0D00: /* bt/s lab */
 477                         ret = handle_delayslot(regs, instruction, ma);
 478                         if (ret==0) {
 479 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
 480                                 if ((regs->sr & 0x00000001) == 0)
 481                                         regs->pc += 4; /* next after slot */
 482                                 else
 483 #endif
 484                                         regs->pc += SH_PC_8BIT_OFFSET(instruction);
 485                         }
 486                         break;
 487                 }
 488                 break;
 489
 490         case 0xA000: /* bra label */
 491                 ret = handle_delayslot(regs, instruction, ma);
 492                 if (ret==0)
 493                         regs->pc += SH_PC_12BIT_OFFSET(instruction);
 494                 break;
 495
 496         case 0xB000: /* bsr label */
 497                 ret = handle_delayslot(regs, instruction, ma);
 498                 if (ret==0) {
 499                         regs->pr = regs->pc + 4;
 500                         regs->pc += SH_PC_12BIT_OFFSET(instruction);
 501                 }
 502                 break;
 503         }
 504         return ret;
 505
 506         /* handle non-delay-slot instruction */
 507  simple:
 508         ret = handle_unaligned_ins(instruction, regs, ma);
 509         if (ret==0)
 510                 regs->pc += instruction_size(instruction);
 511         return ret;
 512 }
 513
 514 #ifdef CONFIG_CPU_HAS_SR_RB
 515 #define lookup_exception_vector(x)      \
 516         __asm__ __volatile__ ("stc r2_bank, %0\n\t" : "=r" ((x)))
 517 #else
 518 #define lookup_exception_vector(x)      \
 519         __asm__ __volatile__ ("mov r4, %0\n\t" : "=r" ((x)))
 520 #endif
 521
 522 /*
 523  * Handle various address error exceptions:
 524  *  - instruction address error:
 525  *       misaligned PC
 526  *       PC >= 0x80000000 in user mode
 527  *  - data address error (read and write)
 528  *       misaligned data access
 529  *       access to >= 0x80000000 is user mode
 530  * Unfortuntaly we can't distinguish between instruction address error
 531  * and data address errors caused by read accesses.
 532  */
 533 asmlinkage void do_address_error(struct pt_regs *regs,
 534                                  unsigned long writeaccess,
 535                                  unsigned long address)
 536 {
 537         unsigned long error_code = 0;
 538         mm_segment_t oldfs;
 539         siginfo_t info;
 540         opcode_t instruction;
 541         int tmp;
 542
 543         /* Intentional ifdef */
 544 #ifdef CONFIG_CPU_HAS_SR_RB
 545         lookup_exception_vector(error_code);
 546 #endif
 547
 548         oldfs = get_fs();
 549
 550         if (user_mode(regs)) {
 551                 int si_code = BUS_ADRERR;
 552
 553                 local_irq_enable();
 554
 555                 /* bad PC is not something we can fix */
 556                 if (regs->pc & 1) {
 557                         si_code = BUS_ADRALN;
 558                         goto uspace_segv;
 559                 }
 560
 561                 set_fs(USER_DS);
 562                 if (copy_from_user(&instruction, (void *)(regs->pc),
 563                                    sizeof(instruction))) {
 564                         /* Argh. Fault on the instruction itself.
 565                            This should never happen non-SMP
 566                         */
 567                         set_fs(oldfs);
 568                         goto uspace_segv;
 569                 }
 570
 571                 tmp = handle_unaligned_access(instruction, regs,
 572                                               &user_mem_access);
 573                 set_fs(oldfs);
 574
 575                 if (tmp==0)
 576                         return; /* sorted */
 577 uspace_segv:
 578                 printk(KERN_NOTICE "Sending SIGBUS to \"%s\" due to unaligned "
 579                        "access (PC %lx PR %lx)\n", current->comm, regs->pc,
 580                        regs->pr);
 581
 582                 info.si_signo = SIGBUS;
 583                 info.si_errno = 0;
 584                 info.si_code = si_code;
 585                 info.si_addr = (void __user *)address;
 586                 force_sig_info(SIGBUS, &info, current);
 587         } else {
 588                 if (regs->pc & 1)
 589                         die("unaligned program counter", regs, error_code);
 590
 591                 set_fs(KERNEL_DS);
 592                 if (copy_from_user(&instruction, (void *)(regs->pc),
 593                                    sizeof(instruction))) {
 594                         /* Argh. Fault on the instruction itself.
 595                            This should never happen non-SMP
 596                         */
 597                         set_fs(oldfs);
 598                         die("insn faulting in do_address_error", regs, 0);
 599                 }
 600
 601                 handle_unaligned_access(instruction, regs, &user_mem_access);
 602                 set_fs(oldfs);
 603         }
 604 }
 605
 606 #ifdef CONFIG_SH_DSP
 607 /*
 608  *      SH-DSP support gerg@snapgear.com.
 609  */
 610 int is_dsp_inst(struct pt_regs *regs)
 611 {
 612         unsigned short inst = 0;
 613
 614         /*
 615          * Safe guard if DSP mode is already enabled or we're lacking
 616          * the DSP altogether.
 617          */
 618         if (!(current_cpu_data.flags & CPU_HAS_DSP) || (regs->sr & SR_DSP))
 619                 return 0;
 620
 621         get_user(inst, ((unsigned short *) regs->pc));
 622
 623         inst &= 0xf000;
 624
 625         /* Check for any type of DSP or support instruction */
 626         if ((inst == 0xf000) || (inst == 0x4000))
 627                 return 1;
 628
 629         return 0;
 630 }
 631 #else
 632 #define is_dsp_inst(regs)       (0)
 633 #endif /* CONFIG_SH_DSP */
 634
 635 #ifdef CONFIG_CPU_SH2A
 636 asmlinkage void do_divide_error(unsigned long r4, unsigned long r5,
 637                                 unsigned long r6, unsigned long r7,
 638                                 struct pt_regs __regs)
 639 {
 640         siginfo_t info;
 641
 642         switch (r4) {
 643         case TRAP_DIVZERO_ERROR:
 644                 info.si_code = FPE_INTDIV;
 645                 break;
 646         case TRAP_DIVOVF_ERROR:
 647                 info.si_code = FPE_INTOVF;
 648                 break;
 649         }
 650
 651         force_sig_info(SIGFPE, &info, current);
 652 }
 653 #endif
 654
 655 asmlinkage void do_reserved_inst(unsigned long r4, unsigned long r5,
 656                                 unsigned long r6, unsigned long r7,
 657                                 struct pt_regs __regs)
 658 {
 659         struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
 660         unsigned long error_code;
 661         struct task_struct *tsk = current;
 662
 663 #ifdef CONFIG_SH_FPU_EMU
 664         unsigned short inst = 0;
 665         int err;
 666
 667         get_user(inst, (unsigned short*)regs->pc);
 668
 669         err = do_fpu_inst(inst, regs);
 670         if (!err) {
 671                 regs->pc += instruction_size(inst);
 672                 return;
 673         }
 674         /* not a FPU inst. */
 675 #endif
 676
 677 #ifdef CONFIG_SH_DSP
 678         /* Check if it's a DSP instruction */
 679         if (is_dsp_inst(regs)) {
 680                 /* Enable DSP mode, and restart instruction. */
 681                 regs->sr |= SR_DSP;
 682                 return;
 683         }
 684 #endif
 685
 686         lookup_exception_vector(error_code);
 687
 688         local_irq_enable();
 689         CHK_REMOTE_DEBUG(regs);
 690         force_sig(SIGILL, tsk);
 691         die_if_no_fixup("reserved instruction", regs, error_code);
 692 }
 693
 694 #ifdef CONFIG_SH_FPU_EMU
 695 static int emulate_branch(unsigned short inst, struct pt_regs* regs)
 696 {
 697         /*
 698          * bfs: 8fxx: PC+=d*2+4;
 699          * bts: 8dxx: PC+=d*2+4;
 700          * bra: axxx: PC+=D*2+4;
 701          * bsr: bxxx: PC+=D*2+4  after PR=PC+4;
 702          * braf:0x23: PC+=Rn*2+4;
 703          * bsrf:0x03: PC+=Rn*2+4 after PR=PC+4;
 704          * jmp: 4x2b: PC=Rn;
 705          * jsr: 4x0b: PC=Rn      after PR=PC+4;
 706          * rts: 000b: PC=PR;
 707          */
 708         if ((inst & 0xfd00) == 0x8d00) {
 709                 regs->pc += SH_PC_8BIT_OFFSET(inst);
 710                 return 0;
 711         }
 712
 713         if ((inst & 0xe000) == 0xa000) {
 714                 regs->pc += SH_PC_12BIT_OFFSET(inst);
 715                 return 0;
 716         }
 717
 718         if ((inst & 0xf0df) == 0x0003) {
 719                 regs->pc += regs->regs[(inst & 0x0f00) >> 8] + 4;
 720                 return 0;
 721         }
 722
 723         if ((inst & 0xf0df) == 0x400b) {
 724                 regs->pc = regs->regs[(inst & 0x0f00) >> 8];
 725                 return 0;
 726         }
 727
 728         if ((inst & 0xffff) == 0x000b) {
 729                 regs->pc = regs->pr;
 730                 return 0;
 731         }
 732
 733         return 1;
 734 }
 735 #endif
 736
 737 asmlinkage void do_illegal_slot_inst(unsigned long r4, unsigned long r5,
 738                                 unsigned long r6, unsigned long r7,
 739                                 struct pt_regs __regs)
 740 {
 741         struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
 742         unsigned long error_code;
 743         struct task_struct *tsk = current;
 744 #ifdef CONFIG_SH_FPU_EMU
 745         unsigned short inst = 0;
 746
 747         get_user(inst, (unsigned short *)regs->pc + 1);
 748         if (!do_fpu_inst(inst, regs)) {
 749                 get_user(inst, (unsigned short *)regs->pc);
 750                 if (!emulate_branch(inst, regs))
 751                         return;
 752                 /* fault in branch.*/
 753         }
 754         /* not a FPU inst. */
 755 #endif
 756
 757         lookup_exception_vector(error_code);
 758
 759         local_irq_enable();
 760         CHK_REMOTE_DEBUG(regs);
 761         force_sig(SIGILL, tsk);
 762         die_if_no_fixup("illegal slot instruction", regs, error_code);
 763 }
 764
 765 asmlinkage void do_exception_error(unsigned long r4, unsigned long r5,
 766                                    unsigned long r6, unsigned long r7,
 767                                    struct pt_regs __regs)
 768 {
 769         struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
 770         long ex;
 771
 772         lookup_exception_vector(ex);
 773         die_if_kernel("exception", regs, ex);
 774 }
 775
 776 #if defined(CONFIG_SH_STANDARD_BIOS)
 777 void *gdb_vbr_vector;
 778
 779 static inline void __init gdb_vbr_init(void)
 780 {
 781         register unsigned long vbr;
 782
 783         /*
 784          * Read the old value of the VBR register to initialise
 785          * the vector through which debug and BIOS traps are
 786          * delegated by the Linux trap handler.
 787          */
 788         asm volatile("stc vbr, %0" : "=r" (vbr));
 789
 790         gdb_vbr_vector = (void *)(vbr + 0x100);
 791         printk("Setting GDB trap vector to 0x%08lx\n",
 792                (unsigned long)gdb_vbr_vector);
 793 }
 794 #endif
 795
 796 void __cpuinit per_cpu_trap_init(void)
 797 {
 798         extern void *vbr_base;
 799
 800 #ifdef CONFIG_SH_STANDARD_BIOS
 801         if (raw_smp_processor_id() == 0)
 802                 gdb_vbr_init();
 803 #endif
 804
 805         /* NOTE: The VBR value should be at P1
 806            (or P2, virtural "fixed" address space).
 807            It's definitely should not in physical address.  */
 808
 809         asm volatile("ldc       %0, vbr"
 810                      : /* no output */
 811                      : "r" (&vbr_base)
 812                      : "memory");
 813 }
 814
 815 void *set_exception_table_vec(unsigned int vec, void *handler)
 816 {
 817         extern void *exception_handling_table[];
 818         void *old_handler;
 819
 820         old_handler = exception_handling_table[vec];
 821         exception_handling_table[vec] = handler;
 822         return old_handler;
 823 }
 824
 825 void __init trap_init(void)
 826 {
 827         set_exception_table_vec(TRAP_RESERVED_INST, do_reserved_inst);
 828         set_exception_table_vec(TRAP_ILLEGAL_SLOT_INST, do_illegal_slot_inst);
 829
 830 #if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_FPU) || \
 831     defined(CONFIG_SH_FPU_EMU)
 832         /*
 833          * For SH-4 lacking an FPU, treat floating point instructions as
 834          * reserved. They'll be handled in the math-emu case, or faulted on
 835          * otherwise.
 836          */
 837         set_exception_table_evt(0x800, do_reserved_inst);
 838         set_exception_table_evt(0x820, do_illegal_slot_inst);
 839 #elif defined(CONFIG_SH_FPU)
 840 #ifdef CONFIG_CPU_SUBTYPE_SHX3
 841         set_exception_table_evt(0xd80, fpu_state_restore_trap_handler);
 842         set_exception_table_evt(0xda0, fpu_state_restore_trap_handler);
 843 #else
 844         set_exception_table_evt(0x800, fpu_state_restore_trap_handler);
 845         set_exception_table_evt(0x820, fpu_state_restore_trap_handler);
 846 #endif
 847 #endif
 848
 849 #ifdef CONFIG_CPU_SH2
 850         set_exception_table_vec(TRAP_ADDRESS_ERROR, address_error_trap_handler);
 851 #endif
 852 #ifdef CONFIG_CPU_SH2A
 853         set_exception_table_vec(TRAP_DIVZERO_ERROR, do_divide_error);
 854         set_exception_table_vec(TRAP_DIVOVF_ERROR, do_divide_error);
 855 #ifdef CONFIG_SH_FPU
 856         set_exception_table_vec(TRAP_FPU_ERROR, fpu_error_trap_handler);
 857 #endif
 858 #endif
 859
 860         /* Setup VBR for boot cpu */
 861         per_cpu_trap_init();
 862 }
 863
 864 void show_trace(struct task_struct *tsk, unsigned long *sp,
 865                 struct pt_regs *regs)
 866 {
 867         unsigned long addr;
 868
 869         if (regs && user_mode(regs))
 870                 return;
 871
 872         printk("\nCall trace: ");
 873 #ifdef CONFIG_KALLSYMS
 874         printk("\n");
 875 #endif
 876
 877         while (!kstack_end(sp)) {
 878                 addr = *sp++;
 879                 if (kernel_text_address(addr))
 880                         print_ip_sym(addr);
 881         }
 882
 883         printk("\n");
 884
 885         if (!tsk)
 886                 tsk = current;
 887
 888         debug_show_held_locks(tsk);
 889 }
 890
 891 void show_stack(struct task_struct *tsk, unsigned long *sp)
 892 {
 893         unsigned long stack;
 894
 895         if (!tsk)
 896                 tsk = current;
 897         if (tsk == current)
 898                 sp = (unsigned long *)current_stack_pointer;
 899         else
 900                 sp = (unsigned long *)tsk->thread.sp;
 901
 902         stack = (unsigned long)sp;
 903         dump_mem("Stack: ", stack, THREAD_SIZE +
 904                  (unsigned long)task_stack_page(tsk));
 905         show_trace(tsk, sp, NULL);
 906 }
 907
 908 void dump_stack(void)
 909 {
 910         show_stack(NULL, NULL);
 911 }
 912 EXPORT_SYMBOL(dump_stack);