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   1 /*
   2  * 'traps.c' handles hardware traps and faults after we have saved some
   3  * state in 'entry.S'.
   4  *
   5  *  SuperH version: Copyright (C) 1999 Niibe Yutaka
   6  *                  Copyright (C) 2000 Philipp Rumpf
   7  *                  Copyright (C) 2000 David Howells
   8  *                  Copyright (C) 2002 - 2007 Paul Mundt
   9  *
  10  * This file is subject to the terms and conditions of the GNU General Public
  11  * License.  See the file "COPYING" in the main directory of this archive
  12  * for more details.
  13  */
  14 #include <linux/kernel.h>
  15 #include <linux/ptrace.h>
  16 #include <linux/init.h>
  17 #include <linux/spinlock.h>
  18 #include <linux/module.h>
  19 #include <linux/kallsyms.h>
  20 #include <linux/io.h>
  21 #include <linux/bug.h>
  22 #include <linux/debug_locks.h>
  23 #include <linux/kdebug.h>
  24 #include <linux/kexec.h>
  25 #include <linux/limits.h>
  26 #include <asm/system.h>
  27 #include <asm/uaccess.h>
  28
  29 #ifdef CONFIG_SH_KGDB
  30 #include <asm/kgdb.h>
  31 #define CHK_REMOTE_DEBUG(regs)                  \
  32 {                                               \
  33         if (kgdb_debug_hook && !user_mode(regs))\
  34                 (*kgdb_debug_hook)(regs);       \
  35 }
  36 #else
  37 #define CHK_REMOTE_DEBUG(regs)
  38 #endif
  39
  40 #ifdef CONFIG_CPU_SH2
  41 # define TRAP_RESERVED_INST     4
  42 # define TRAP_ILLEGAL_SLOT_INST 6
  43 # define TRAP_ADDRESS_ERROR     9
  44 # ifdef CONFIG_CPU_SH2A
  45 #  define TRAP_DIVZERO_ERROR    17
  46 #  define TRAP_DIVOVF_ERROR     18
  47 # endif
  48 #else
  49 #define TRAP_RESERVED_INST      12
  50 #define TRAP_ILLEGAL_SLOT_INST  13
  51 #endif
  52
  53 static void dump_mem(const char *str, unsigned long bottom, unsigned long top)
  54 {
  55         unsigned long p;
  56         int i;
  57
  58         printk("%s(0x%08lx to 0x%08lx)\n", str, bottom, top);
  59
  60         for (p = bottom & ~31; p < top; ) {
  61                 printk("%04lx: ", p & 0xffff);
  62
  63                 for (i = 0; i < 8; i++, p += 4) {
  64                         unsigned int val;
  65
  66                         if (p < bottom || p >= top)
  67                                 printk("         ");
  68                         else {
  69                                 if (__get_user(val, (unsigned int __user *)p)) {
  70                                         printk("\n");
  71                                         return;
  72                                 }
  73                                 printk("%08x ", val);
  74                         }
  75                 }
  76                 printk("\n");
  77         }
  78 }
  79
  80 static DEFINE_SPINLOCK(die_lock);
  81
  82 void die(const char * str, struct pt_regs * regs, long err)
  83 {
  84         static int die_counter;
  85
  86         oops_enter();
  87
  88         console_verbose();
  89         spin_lock_irq(&die_lock);
  90         bust_spinlocks(1);
  91
  92         printk("%s: %04lx [#%d]\n", str, err & 0xffff, ++die_counter);
  93
  94         CHK_REMOTE_DEBUG(regs);
  95         print_modules();
  96         show_regs(regs);
  97
  98         printk("Process: %s (pid: %d, stack limit = %p)\n", current->comm,
  99                         task_pid_nr(current), task_stack_page(current) + 1);
 100
 101         if (!user_mode(regs) || in_interrupt())
 102                 dump_mem("Stack: ", regs->regs[15], THREAD_SIZE +
 103                          (unsigned long)task_stack_page(current));
 104
 105         bust_spinlocks(0);
 106         add_taint(TAINT_DIE);
 107         spin_unlock_irq(&die_lock);
 108
 109         if (kexec_should_crash(current))
 110                 crash_kexec(regs);
 111
 112         if (in_interrupt())
 113                 panic("Fatal exception in interrupt");
 114
 115         if (panic_on_oops)
 116                 panic("Fatal exception");
 117
 118         oops_exit();
 119         do_exit(SIGSEGV);
 120 }
 121
 122 static inline void die_if_kernel(const char *str, struct pt_regs *regs,
 123                                  long err)
 124 {
 125         if (!user_mode(regs))
 126                 die(str, regs, err);
 127 }
 128
 129 /*
 130  * try and fix up kernelspace address errors
 131  * - userspace errors just cause EFAULT to be returned, resulting in SEGV
 132  * - kernel/userspace interfaces cause a jump to an appropriate handler
 133  * - other kernel errors are bad
 134  * - return 0 if fixed-up, -EFAULT if non-fatal (to the kernel) fault
 135  */
 136 static int die_if_no_fixup(const char * str, struct pt_regs * regs, long err)
 137 {
 138         if (!user_mode(regs)) {
 139                 const struct exception_table_entry *fixup;
 140                 fixup = search_exception_tables(regs->pc);
 141                 if (fixup) {
 142                         regs->pc = fixup->fixup;
 143                         return 0;
 144                 }
 145                 die(str, regs, err);
 146         }
 147         return -EFAULT;
 148 }
 149
 150 static inline void sign_extend(unsigned int count, unsigned char *dst)
 151 {
 152 #ifdef __LITTLE_ENDIAN__
 153         if ((count == 1) && dst[0] & 0x80) {
 154                 dst[1] = 0xff;
 155                 dst[2] = 0xff;
 156                 dst[3] = 0xff;
 157         }
 158         if ((count == 2) && dst[1] & 0x80) {
 159                 dst[2] = 0xff;
 160                 dst[3] = 0xff;
 161         }
 162 #else
 163         if ((count == 1) && dst[3] & 0x80) {
 164                 dst[2] = 0xff;
 165                 dst[1] = 0xff;
 166                 dst[0] = 0xff;
 167         }
 168         if ((count == 2) && dst[2] & 0x80) {
 169                 dst[1] = 0xff;
 170                 dst[0] = 0xff;
 171         }
 172 #endif
 173 }
 174
 175 /*
 176  * handle an instruction that does an unaligned memory access by emulating the
 177  * desired behaviour
 178  * - note that PC _may not_ point to the faulting instruction
 179  *   (if that instruction is in a branch delay slot)
 180  * - return 0 if emulation okay, -EFAULT on existential error
 181  */
 182 static int handle_unaligned_ins(opcode_t instruction, struct pt_regs *regs)
 183 {
 184         int ret, index, count;
 185         unsigned long *rm, *rn;
 186         unsigned char *src, *dst;
 187
 188         index = (instruction>>8)&15;    /* 0x0F00 */
 189         rn = &regs->regs[index];
 190
 191         index = (instruction>>4)&15;    /* 0x00F0 */
 192         rm = &regs->regs[index];
 193
 194         count = 1<<(instruction&3);
 195
 196         ret = -EFAULT;
 197         switch (instruction>>12) {
 198         case 0: /* mov.[bwl] to/from memory via r0+rn */
 199                 if (instruction & 8) {
 200                         /* from memory */
 201                         src = (unsigned char*) *rm;
 202                         src += regs->regs[0];
 203                         dst = (unsigned char*) rn;
 204                         *(unsigned long*)dst = 0;
 205
 206 #if !defined(__LITTLE_ENDIAN__)
 207                         dst += 4-count;
 208 #endif
 209                         if (copy_from_user(dst, src, count))
 210                                 goto fetch_fault;
 211
 212                         sign_extend(count, dst);
 213                 } else {
 214                         /* to memory */
 215                         src = (unsigned char*) rm;
 216 #if !defined(__LITTLE_ENDIAN__)
 217                         src += 4-count;
 218 #endif
 219                         dst = (unsigned char*) *rn;
 220                         dst += regs->regs[0];
 221
 222                         if (copy_to_user(dst, src, count))
 223                                 goto fetch_fault;
 224                 }
 225                 ret = 0;
 226                 break;
 227
 228         case 1: /* mov.l Rm,@(disp,Rn) */
 229                 src = (unsigned char*) rm;
 230                 dst = (unsigned char*) *rn;
 231                 dst += (instruction&0x000F)<<2;
 232
 233                 if (copy_to_user(dst,src,4))
 234                         goto fetch_fault;
 235                 ret = 0;
 236                 break;
 237
 238         case 2: /* mov.[bwl] to memory, possibly with pre-decrement */
 239                 if (instruction & 4)
 240                         *rn -= count;
 241                 src = (unsigned char*) rm;
 242                 dst = (unsigned char*) *rn;
 243 #if !defined(__LITTLE_ENDIAN__)
 244                 src += 4-count;
 245 #endif
 246                 if (copy_to_user(dst, src, count))
 247                         goto fetch_fault;
 248                 ret = 0;
 249                 break;
 250
 251         case 5: /* mov.l @(disp,Rm),Rn */
 252                 src = (unsigned char*) *rm;
 253                 src += (instruction&0x000F)<<2;
 254                 dst = (unsigned char*) rn;
 255                 *(unsigned long*)dst = 0;
 256
 257                 if (copy_from_user(dst,src,4))
 258                         goto fetch_fault;
 259                 ret = 0;
 260                 break;
 261
 262         case 6: /* mov.[bwl] from memory, possibly with post-increment */
 263                 src = (unsigned char*) *rm;
 264                 if (instruction & 4)
 265                         *rm += count;
 266                 dst = (unsigned char*) rn;
 267                 *(unsigned long*)dst = 0;
 268
 269 #if !defined(__LITTLE_ENDIAN__)
 270                 dst += 4-count;
 271 #endif
 272                 if (copy_from_user(dst, src, count))
 273                         goto fetch_fault;
 274                 sign_extend(count, dst);
 275                 ret = 0;
 276                 break;
 277
 278         case 8:
 279                 switch ((instruction&0xFF00)>>8) {
 280                 case 0x81: /* mov.w R0,@(disp,Rn) */
 281                         src = (unsigned char*) &regs->regs[0];
 282 #if !defined(__LITTLE_ENDIAN__)
 283                         src += 2;
 284 #endif
 285                         dst = (unsigned char*) *rm; /* called Rn in the spec */
 286                         dst += (instruction&0x000F)<<1;
 287
 288                         if (copy_to_user(dst, src, 2))
 289                                 goto fetch_fault;
 290                         ret = 0;
 291                         break;
 292
 293                 case 0x85: /* mov.w @(disp,Rm),R0 */
 294                         src = (unsigned char*) *rm;
 295                         src += (instruction&0x000F)<<1;
 296                         dst = (unsigned char*) &regs->regs[0];
 297                         *(unsigned long*)dst = 0;
 298
 299 #if !defined(__LITTLE_ENDIAN__)
 300                         dst += 2;
 301 #endif
 302                         if (copy_from_user(dst, src, 2))
 303                                 goto fetch_fault;
 304                         sign_extend(2, dst);
 305                         ret = 0;
 306                         break;
 307                 }
 308                 break;
 309         }
 310         return ret;
 311
 312  fetch_fault:
 313         /* Argh. Address not only misaligned but also non-existent.
 314          * Raise an EFAULT and see if it's trapped
 315          */
 316         return die_if_no_fixup("Fault in unaligned fixup", regs, 0);
 317 }
 318
 319 /*
 320  * emulate the instruction in the delay slot
 321  * - fetches the instruction from PC+2
 322  */
 323 static inline int handle_unaligned_delayslot(struct pt_regs *regs,
 324                                              opcode_t old_instruction)
 325 {
 326         opcode_t instruction;
 327         void *addr = (void *)(regs->pc + instruction_size(old_instruction));
 328
 329         if (copy_from_user(&instruction, addr, sizeof(instruction))) {
 330                 /* the instruction-fetch faulted */
 331                 if (user_mode(regs))
 332                         return -EFAULT;
 333
 334                 /* kernel */
 335                 die("delay-slot-insn faulting in handle_unaligned_delayslot",
 336                     regs, 0);
 337         }
 338
 339         return handle_unaligned_ins(instruction, regs);
 340 }
 341
 342 /*
 343  * handle an instruction that does an unaligned memory access
 344  * - have to be careful of branch delay-slot instructions that fault
 345  *  SH3:
 346  *   - if the branch would be taken PC points to the branch
 347  *   - if the branch would not be taken, PC points to delay-slot
 348  *  SH4:
 349  *   - PC always points to delayed branch
 350  * - return 0 if handled, -EFAULT if failed (may not return if in kernel)
 351  */
 352
 353 /* Macros to determine offset from current PC for branch instructions */
 354 /* Explicit type coercion is used to force sign extension where needed */
 355 #define SH_PC_8BIT_OFFSET(instr) ((((signed char)(instr))*2) + 4)
 356 #define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4)
 357
 358 /*
 359  * XXX: SH-2A needs this too, but it needs an overhaul thanks to mixed 32-bit
 360  * opcodes..
 361  */
 362
 363 static int handle_unaligned_notify_count = 10;
 364
 365 static int handle_unaligned_access(opcode_t instruction, struct pt_regs *regs)
 366 {
 367         u_int rm;
 368         int ret, index;
 369
 370         index = (instruction>>8)&15;    /* 0x0F00 */
 371         rm = regs->regs[index];
 372
 373         /* shout about the first ten userspace fixups */
 374         if (user_mode(regs) && handle_unaligned_notify_count>0) {
 375                 handle_unaligned_notify_count--;
 376
 377                 printk(KERN_NOTICE "Fixing up unaligned userspace access "
 378                        "in \"%s\" pid=%d pc=0x%p ins=0x%04hx\n",
 379                        current->comm, task_pid_nr(current),
 380                        (void *)regs->pc, instruction);
 381         }
 382
 383         ret = -EFAULT;
 384         switch (instruction&0xF000) {
 385         case 0x0000:
 386                 if (instruction==0x000B) {
 387                         /* rts */
 388                         ret = handle_unaligned_delayslot(regs, instruction);
 389                         if (ret==0)
 390                                 regs->pc = regs->pr;
 391                 }
 392                 else if ((instruction&0x00FF)==0x0023) {
 393                         /* braf @Rm */
 394                         ret = handle_unaligned_delayslot(regs, instruction);
 395                         if (ret==0)
 396                                 regs->pc += rm + 4;
 397                 }
 398                 else if ((instruction&0x00FF)==0x0003) {
 399                         /* bsrf @Rm */
 400                         ret = handle_unaligned_delayslot(regs, instruction);
 401                         if (ret==0) {
 402                                 regs->pr = regs->pc + 4;
 403                                 regs->pc += rm + 4;
 404                         }
 405                 }
 406                 else {
 407                         /* mov.[bwl] to/from memory via r0+rn */
 408                         goto simple;
 409                 }
 410                 break;
 411
 412         case 0x1000: /* mov.l Rm,@(disp,Rn) */
 413                 goto simple;
 414
 415         case 0x2000: /* mov.[bwl] to memory, possibly with pre-decrement */
 416                 goto simple;
 417
 418         case 0x4000:
 419                 if ((instruction&0x00FF)==0x002B) {
 420                         /* jmp @Rm */
 421                         ret = handle_unaligned_delayslot(regs, instruction);
 422                         if (ret==0)
 423                                 regs->pc = rm;
 424                 }
 425                 else if ((instruction&0x00FF)==0x000B) {
 426                         /* jsr @Rm */
 427                         ret = handle_unaligned_delayslot(regs, instruction);
 428                         if (ret==0) {
 429                                 regs->pr = regs->pc + 4;
 430                                 regs->pc = rm;
 431                         }
 432                 }
 433                 else {
 434                         /* mov.[bwl] to/from memory via r0+rn */
 435                         goto simple;
 436                 }
 437                 break;
 438
 439         case 0x5000: /* mov.l @(disp,Rm),Rn */
 440                 goto simple;
 441
 442         case 0x6000: /* mov.[bwl] from memory, possibly with post-increment */
 443                 goto simple;
 444
 445         case 0x8000: /* bf lab, bf/s lab, bt lab, bt/s lab */
 446                 switch (instruction&0x0F00) {
 447                 case 0x0100: /* mov.w R0,@(disp,Rm) */
 448                         goto simple;
 449                 case 0x0500: /* mov.w @(disp,Rm),R0 */
 450                         goto simple;
 451                 case 0x0B00: /* bf   lab - no delayslot*/
 452                         break;
 453                 case 0x0F00: /* bf/s lab */
 454                         ret = handle_unaligned_delayslot(regs, instruction);
 455                         if (ret==0) {
 456 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
 457                                 if ((regs->sr & 0x00000001) != 0)
 458                                         regs->pc += 4; /* next after slot */
 459                                 else
 460 #endif
 461                                         regs->pc += SH_PC_8BIT_OFFSET(instruction);
 462                         }
 463                         break;
 464                 case 0x0900: /* bt   lab - no delayslot */
 465                         break;
 466                 case 0x0D00: /* bt/s lab */
 467                         ret = handle_unaligned_delayslot(regs, instruction);
 468                         if (ret==0) {
 469 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
 470                                 if ((regs->sr & 0x00000001) == 0)
 471                                         regs->pc += 4; /* next after slot */
 472                                 else
 473 #endif
 474                                         regs->pc += SH_PC_8BIT_OFFSET(instruction);
 475                         }
 476                         break;
 477                 }
 478                 break;
 479
 480         case 0xA000: /* bra label */
 481                 ret = handle_unaligned_delayslot(regs, instruction);
 482                 if (ret==0)
 483                         regs->pc += SH_PC_12BIT_OFFSET(instruction);
 484                 break;
 485
 486         case 0xB000: /* bsr label */
 487                 ret = handle_unaligned_delayslot(regs, instruction);
 488                 if (ret==0) {
 489                         regs->pr = regs->pc + 4;
 490                         regs->pc += SH_PC_12BIT_OFFSET(instruction);
 491                 }
 492                 break;
 493         }
 494         return ret;
 495
 496         /* handle non-delay-slot instruction */
 497  simple:
 498         ret = handle_unaligned_ins(instruction, regs);
 499         if (ret==0)
 500                 regs->pc += instruction_size(instruction);
 501         return ret;
 502 }
 503
 504 #ifdef CONFIG_CPU_HAS_SR_RB
 505 #define lookup_exception_vector(x)      \
 506         __asm__ __volatile__ ("stc r2_bank, %0\n\t" : "=r" ((x)))
 507 #else
 508 #define lookup_exception_vector(x)      \
 509         __asm__ __volatile__ ("mov r4, %0\n\t" : "=r" ((x)))
 510 #endif
 511
 512 /*
 513  * Handle various address error exceptions:
 514  *  - instruction address error:
 515  *       misaligned PC
 516  *       PC >= 0x80000000 in user mode
 517  *  - data address error (read and write)
 518  *       misaligned data access
 519  *       access to >= 0x80000000 is user mode
 520  * Unfortuntaly we can't distinguish between instruction address error
 521  * and data address errors caused by read accesses.
 522  */
 523 asmlinkage void do_address_error(struct pt_regs *regs,
 524                                  unsigned long writeaccess,
 525                                  unsigned long address)
 526 {
 527         unsigned long error_code = 0;
 528         mm_segment_t oldfs;
 529         siginfo_t info;
 530         opcode_t instruction;
 531         int tmp;
 532
 533         /* Intentional ifdef */
 534 #ifdef CONFIG_CPU_HAS_SR_RB
 535         lookup_exception_vector(error_code);
 536 #endif
 537
 538         oldfs = get_fs();
 539
 540         if (user_mode(regs)) {
 541                 int si_code = BUS_ADRERR;
 542
 543                 local_irq_enable();
 544
 545                 /* bad PC is not something we can fix */
 546                 if (regs->pc & 1) {
 547                         si_code = BUS_ADRALN;
 548                         goto uspace_segv;
 549                 }
 550
 551                 set_fs(USER_DS);
 552                 if (copy_from_user(&instruction, (void *)(regs->pc),
 553                                    sizeof(instruction))) {
 554                         /* Argh. Fault on the instruction itself.
 555                            This should never happen non-SMP
 556                         */
 557                         set_fs(oldfs);
 558                         goto uspace_segv;
 559                 }
 560
 561                 tmp = handle_unaligned_access(instruction, regs);
 562                 set_fs(oldfs);
 563
 564                 if (tmp==0)
 565                         return; /* sorted */
 566 uspace_segv:
 567                 printk(KERN_NOTICE "Sending SIGBUS to \"%s\" due to unaligned "
 568                        "access (PC %lx PR %lx)\n", current->comm, regs->pc,
 569                        regs->pr);
 570
 571                 info.si_signo = SIGBUS;
 572                 info.si_errno = 0;
 573                 info.si_code = si_code;
 574                 info.si_addr = (void __user *)address;
 575                 force_sig_info(SIGBUS, &info, current);
 576         } else {
 577                 if (regs->pc & 1)
 578                         die("unaligned program counter", regs, error_code);
 579
 580                 set_fs(KERNEL_DS);
 581                 if (copy_from_user(&instruction, (void *)(regs->pc),
 582                                    sizeof(instruction))) {
 583                         /* Argh. Fault on the instruction itself.
 584                            This should never happen non-SMP
 585                         */
 586                         set_fs(oldfs);
 587                         die("insn faulting in do_address_error", regs, 0);
 588                 }
 589
 590                 handle_unaligned_access(instruction, regs);
 591                 set_fs(oldfs);
 592         }
 593 }
 594
 595 #ifdef CONFIG_SH_DSP
 596 /*
 597  *      SH-DSP support gerg@snapgear.com.
 598  */
 599 int is_dsp_inst(struct pt_regs *regs)
 600 {
 601         unsigned short inst = 0;
 602
 603         /*
 604          * Safe guard if DSP mode is already enabled or we're lacking
 605          * the DSP altogether.
 606          */
 607         if (!(current_cpu_data.flags & CPU_HAS_DSP) || (regs->sr & SR_DSP))
 608                 return 0;
 609
 610         get_user(inst, ((unsigned short *) regs->pc));
 611
 612         inst &= 0xf000;
 613
 614         /* Check for any type of DSP or support instruction */
 615         if ((inst == 0xf000) || (inst == 0x4000))
 616                 return 1;
 617
 618         return 0;
 619 }
 620 #else
 621 #define is_dsp_inst(regs)       (0)
 622 #endif /* CONFIG_SH_DSP */
 623
 624 #ifdef CONFIG_CPU_SH2A
 625 asmlinkage void do_divide_error(unsigned long r4, unsigned long r5,
 626                                 unsigned long r6, unsigned long r7,
 627                                 struct pt_regs __regs)
 628 {
 629         siginfo_t info;
 630
 631         switch (r4) {
 632         case TRAP_DIVZERO_ERROR:
 633                 info.si_code = FPE_INTDIV;
 634                 break;
 635         case TRAP_DIVOVF_ERROR:
 636                 info.si_code = FPE_INTOVF;
 637                 break;
 638         }
 639
 640         force_sig_info(SIGFPE, &info, current);
 641 }
 642 #endif
 643
 644 asmlinkage void do_reserved_inst(unsigned long r4, unsigned long r5,
 645                                 unsigned long r6, unsigned long r7,
 646                                 struct pt_regs __regs)
 647 {
 648         struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
 649         unsigned long error_code;
 650         struct task_struct *tsk = current;
 651
 652 #ifdef CONFIG_SH_FPU_EMU
 653         unsigned short inst = 0;
 654         int err;
 655
 656         get_user(inst, (unsigned short*)regs->pc);
 657
 658         err = do_fpu_inst(inst, regs);
 659         if (!err) {
 660                 regs->pc += instruction_size(inst);
 661                 return;
 662         }
 663         /* not a FPU inst. */
 664 #endif
 665
 666 #ifdef CONFIG_SH_DSP
 667         /* Check if it's a DSP instruction */
 668         if (is_dsp_inst(regs)) {
 669                 /* Enable DSP mode, and restart instruction. */
 670                 regs->sr |= SR_DSP;
 671                 return;
 672         }
 673 #endif
 674
 675         lookup_exception_vector(error_code);
 676
 677         local_irq_enable();
 678         CHK_REMOTE_DEBUG(regs);
 679         force_sig(SIGILL, tsk);
 680         die_if_no_fixup("reserved instruction", regs, error_code);
 681 }
 682
 683 #ifdef CONFIG_SH_FPU_EMU
 684 static int emulate_branch(unsigned short inst, struct pt_regs* regs)
 685 {
 686         /*
 687          * bfs: 8fxx: PC+=d*2+4;
 688          * bts: 8dxx: PC+=d*2+4;
 689          * bra: axxx: PC+=D*2+4;
 690          * bsr: bxxx: PC+=D*2+4  after PR=PC+4;
 691          * braf:0x23: PC+=Rn*2+4;
 692          * bsrf:0x03: PC+=Rn*2+4 after PR=PC+4;
 693          * jmp: 4x2b: PC=Rn;
 694          * jsr: 4x0b: PC=Rn      after PR=PC+4;
 695          * rts: 000b: PC=PR;
 696          */
 697         if ((inst & 0xfd00) == 0x8d00) {
 698                 regs->pc += SH_PC_8BIT_OFFSET(inst);
 699                 return 0;
 700         }
 701
 702         if ((inst & 0xe000) == 0xa000) {
 703                 regs->pc += SH_PC_12BIT_OFFSET(inst);
 704                 return 0;
 705         }
 706
 707         if ((inst & 0xf0df) == 0x0003) {
 708                 regs->pc += regs->regs[(inst & 0x0f00) >> 8] + 4;
 709                 return 0;
 710         }
 711
 712         if ((inst & 0xf0df) == 0x400b) {
 713                 regs->pc = regs->regs[(inst & 0x0f00) >> 8];
 714                 return 0;
 715         }
 716
 717         if ((inst & 0xffff) == 0x000b) {
 718                 regs->pc = regs->pr;
 719                 return 0;
 720         }
 721
 722         return 1;
 723 }
 724 #endif
 725
 726 asmlinkage void do_illegal_slot_inst(unsigned long r4, unsigned long r5,
 727                                 unsigned long r6, unsigned long r7,
 728                                 struct pt_regs __regs)
 729 {
 730         struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
 731         unsigned long error_code;
 732         struct task_struct *tsk = current;
 733 #ifdef CONFIG_SH_FPU_EMU
 734         unsigned short inst = 0;
 735
 736         get_user(inst, (unsigned short *)regs->pc + 1);
 737         if (!do_fpu_inst(inst, regs)) {
 738                 get_user(inst, (unsigned short *)regs->pc);
 739                 if (!emulate_branch(inst, regs))
 740                         return;
 741                 /* fault in branch.*/
 742         }
 743         /* not a FPU inst. */
 744 #endif
 745
 746         lookup_exception_vector(error_code);
 747
 748         local_irq_enable();
 749         CHK_REMOTE_DEBUG(regs);
 750         force_sig(SIGILL, tsk);
 751         die_if_no_fixup("illegal slot instruction", regs, error_code);
 752 }
 753
 754 asmlinkage void do_exception_error(unsigned long r4, unsigned long r5,
 755                                    unsigned long r6, unsigned long r7,
 756                                    struct pt_regs __regs)
 757 {
 758         struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
 759         long ex;
 760
 761         lookup_exception_vector(ex);
 762         die_if_kernel("exception", regs, ex);
 763 }
 764
 765 #if defined(CONFIG_SH_STANDARD_BIOS)
 766 void *gdb_vbr_vector;
 767
 768 static inline void __init gdb_vbr_init(void)
 769 {
 770         register unsigned long vbr;
 771
 772         /*
 773          * Read the old value of the VBR register to initialise
 774          * the vector through which debug and BIOS traps are
 775          * delegated by the Linux trap handler.
 776          */
 777         asm volatile("stc vbr, %0" : "=r" (vbr));
 778
 779         gdb_vbr_vector = (void *)(vbr + 0x100);
 780         printk("Setting GDB trap vector to 0x%08lx\n",
 781                (unsigned long)gdb_vbr_vector);
 782 }
 783 #endif
 784
 785 void __cpuinit per_cpu_trap_init(void)
 786 {
 787         extern void *vbr_base;
 788
 789 #ifdef CONFIG_SH_STANDARD_BIOS
 790         if (raw_smp_processor_id() == 0)
 791                 gdb_vbr_init();
 792 #endif
 793
 794         /* NOTE: The VBR value should be at P1
 795            (or P2, virtural "fixed" address space).
 796            It's definitely should not in physical address.  */
 797
 798         asm volatile("ldc       %0, vbr"
 799                      : /* no output */
 800                      : "r" (&vbr_base)
 801                      : "memory");
 802 }
 803
 804 void *set_exception_table_vec(unsigned int vec, void *handler)
 805 {
 806         extern void *exception_handling_table[];
 807         void *old_handler;
 808
 809         old_handler = exception_handling_table[vec];
 810         exception_handling_table[vec] = handler;
 811         return old_handler;
 812 }
 813
 814 void __init trap_init(void)
 815 {
 816         set_exception_table_vec(TRAP_RESERVED_INST, do_reserved_inst);
 817         set_exception_table_vec(TRAP_ILLEGAL_SLOT_INST, do_illegal_slot_inst);
 818
 819 #if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_FPU) || \
 820     defined(CONFIG_SH_FPU_EMU)
 821         /*
 822          * For SH-4 lacking an FPU, treat floating point instructions as
 823          * reserved. They'll be handled in the math-emu case, or faulted on
 824          * otherwise.
 825          */
 826         set_exception_table_evt(0x800, do_reserved_inst);
 827         set_exception_table_evt(0x820, do_illegal_slot_inst);
 828 #elif defined(CONFIG_SH_FPU)
 829 #ifdef CONFIG_CPU_SUBTYPE_SHX3
 830         set_exception_table_evt(0xd80, fpu_state_restore_trap_handler);
 831         set_exception_table_evt(0xda0, fpu_state_restore_trap_handler);
 832 #else
 833         set_exception_table_evt(0x800, fpu_state_restore_trap_handler);
 834         set_exception_table_evt(0x820, fpu_state_restore_trap_handler);
 835 #endif
 836 #endif
 837
 838 #ifdef CONFIG_CPU_SH2
 839         set_exception_table_vec(TRAP_ADDRESS_ERROR, address_error_trap_handler);
 840 #endif
 841 #ifdef CONFIG_CPU_SH2A
 842         set_exception_table_vec(TRAP_DIVZERO_ERROR, do_divide_error);
 843         set_exception_table_vec(TRAP_DIVOVF_ERROR, do_divide_error);
 844 #endif
 845
 846         /* Setup VBR for boot cpu */
 847         per_cpu_trap_init();
 848 }
 849
 850 void show_trace(struct task_struct *tsk, unsigned long *sp,
 851                 struct pt_regs *regs)
 852 {
 853         unsigned long addr;
 854
 855         if (regs && user_mode(regs))
 856                 return;
 857
 858         printk("\nCall trace: ");
 859 #ifdef CONFIG_KALLSYMS
 860         printk("\n");
 861 #endif
 862
 863         while (!kstack_end(sp)) {
 864                 addr = *sp++;
 865                 if (kernel_text_address(addr))
 866                         print_ip_sym(addr);
 867         }
 868
 869         printk("\n");
 870
 871         if (!tsk)
 872                 tsk = current;
 873
 874         debug_show_held_locks(tsk);
 875 }
 876
 877 void show_stack(struct task_struct *tsk, unsigned long *sp)
 878 {
 879         unsigned long stack;
 880
 881         if (!tsk)
 882                 tsk = current;
 883         if (tsk == current)
 884                 sp = (unsigned long *)current_stack_pointer;
 885         else
 886                 sp = (unsigned long *)tsk->thread.sp;
 887
 888         stack = (unsigned long)sp;
 889         dump_mem("Stack: ", stack, THREAD_SIZE +
 890                  (unsigned long)task_stack_page(tsk));
 891         show_trace(tsk, sp, NULL);
 892 }
 893
 894 void dump_stack(void)
 895 {
 896         show_stack(NULL, NULL);
 897 }
 898 EXPORT_SYMBOL(dump_stack);