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   1 /*
   2  * SH7785 Setup
   3  *
   4  *  Copyright (C) 2007  Paul Mundt
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10 #include <linux/platform_device.h>
  11 #include <linux/init.h>
  12 #include <linux/serial.h>
  13 #include <linux/serial_sci.h>
  14 #include <linux/io.h>
  15 #include <linux/mm.h>
  16 #include <linux/sh_timer.h>
  17 #include <asm/dma-sh.h>
  18 #include <asm/mmzone.h>
  19
  20 static struct plat_sci_port scif0_platform_data = {
  21         .mapbase        = 0xffea0000,
  22         .flags          = UPF_BOOT_AUTOCONF,
  23         .type           = PORT_SCIF,
  24         .irqs           = { 40, 40, 40, 40 },
  25         .clk            = "scif_fck",
  26 };
  27
  28 static struct platform_device scif0_device = {
  29         .name           = "sh-sci",
  30         .id             = 0,
  31         .dev            = {
  32                 .platform_data  = &scif0_platform_data,
  33         },
  34 };
  35
  36 static struct plat_sci_port scif1_platform_data = {
  37         .mapbase        = 0xffeb0000,
  38         .flags          = UPF_BOOT_AUTOCONF,
  39         .type           = PORT_SCIF,
  40         .irqs           = { 44, 44, 44, 44 },
  41         .clk            = "scif_fck",
  42 };
  43
  44 static struct platform_device scif1_device = {
  45         .name           = "sh-sci",
  46         .id             = 1,
  47         .dev            = {
  48                 .platform_data  = &scif1_platform_data,
  49         },
  50 };
  51
  52 static struct plat_sci_port scif2_platform_data = {
  53         .mapbase        = 0xffec0000,
  54         .flags          = UPF_BOOT_AUTOCONF,
  55         .type           = PORT_SCIF,
  56         .irqs           = { 60, 60, 60, 60 },
  57         .clk            = "scif_fck",
  58 };
  59
  60 static struct platform_device scif2_device = {
  61         .name           = "sh-sci",
  62         .id             = 2,
  63         .dev            = {
  64                 .platform_data  = &scif2_platform_data,
  65         },
  66 };
  67
  68 static struct plat_sci_port scif3_platform_data = {
  69         .mapbase        = 0xffed0000,
  70         .flags          = UPF_BOOT_AUTOCONF,
  71         .type           = PORT_SCIF,
  72         .irqs           = { 61, 61, 61, 61 },
  73         .clk            = "scif_fck",
  74 };
  75
  76 static struct platform_device scif3_device = {
  77         .name           = "sh-sci",
  78         .id             = 3,
  79         .dev            = {
  80                 .platform_data  = &scif3_platform_data,
  81         },
  82 };
  83
  84 static struct plat_sci_port scif4_platform_data = {
  85         .mapbase        = 0xffee0000,
  86         .flags          = UPF_BOOT_AUTOCONF,
  87         .type           = PORT_SCIF,
  88         .irqs           = { 62, 62, 62, 62 },
  89         .clk            = "scif_fck",
  90 };
  91
  92 static struct platform_device scif4_device = {
  93         .name           = "sh-sci",
  94         .id             = 4,
  95         .dev            = {
  96                 .platform_data  = &scif4_platform_data,
  97         },
  98 };
  99
 100 static struct plat_sci_port scif5_platform_data = {
 101         .mapbase        = 0xffef0000,
 102         .flags          = UPF_BOOT_AUTOCONF,
 103         .type           = PORT_SCIF,
 104         .irqs           = { 63, 63, 63, 63 },
 105         .clk            = "scif_fck",
 106 };
 107
 108 static struct platform_device scif5_device = {
 109         .name           = "sh-sci",
 110         .id             = 5,
 111         .dev            = {
 112                 .platform_data  = &scif5_platform_data,
 113         },
 114 };
 115
 116 static struct sh_timer_config tmu0_platform_data = {
 117         .name = "TMU0",
 118         .channel_offset = 0x04,
 119         .timer_bit = 0,
 120         .clk = "tmu012_fck",
 121         .clockevent_rating = 200,
 122 };
 123
 124 static struct resource tmu0_resources[] = {
 125         [0] = {
 126                 .name   = "TMU0",
 127                 .start  = 0xffd80008,
 128                 .end    = 0xffd80013,
 129                 .flags  = IORESOURCE_MEM,
 130         },
 131         [1] = {
 132                 .start  = 28,
 133                 .flags  = IORESOURCE_IRQ,
 134         },
 135 };
 136
 137 static struct platform_device tmu0_device = {
 138         .name           = "sh_tmu",
 139         .id             = 0,
 140         .dev = {
 141                 .platform_data  = &tmu0_platform_data,
 142         },
 143         .resource       = tmu0_resources,
 144         .num_resources  = ARRAY_SIZE(tmu0_resources),
 145 };
 146
 147 static struct sh_timer_config tmu1_platform_data = {
 148         .name = "TMU1",
 149         .channel_offset = 0x10,
 150         .timer_bit = 1,
 151         .clk = "tmu012_fck",
 152         .clocksource_rating = 200,
 153 };
 154
 155 static struct resource tmu1_resources[] = {
 156         [0] = {
 157                 .name   = "TMU1",
 158                 .start  = 0xffd80014,
 159                 .end    = 0xffd8001f,
 160                 .flags  = IORESOURCE_MEM,
 161         },
 162         [1] = {
 163                 .start  = 29,
 164                 .flags  = IORESOURCE_IRQ,
 165         },
 166 };
 167
 168 static struct platform_device tmu1_device = {
 169         .name           = "sh_tmu",
 170         .id             = 1,
 171         .dev = {
 172                 .platform_data  = &tmu1_platform_data,
 173         },
 174         .resource       = tmu1_resources,
 175         .num_resources  = ARRAY_SIZE(tmu1_resources),
 176 };
 177
 178 static struct sh_timer_config tmu2_platform_data = {
 179         .name = "TMU2",
 180         .channel_offset = 0x1c,
 181         .timer_bit = 2,
 182         .clk = "tmu012_fck",
 183 };
 184
 185 static struct resource tmu2_resources[] = {
 186         [0] = {
 187                 .name   = "TMU2",
 188                 .start  = 0xffd80020,
 189                 .end    = 0xffd8002f,
 190                 .flags  = IORESOURCE_MEM,
 191         },
 192         [1] = {
 193                 .start  = 30,
 194                 .flags  = IORESOURCE_IRQ,
 195         },
 196 };
 197
 198 static struct platform_device tmu2_device = {
 199         .name           = "sh_tmu",
 200         .id             = 2,
 201         .dev = {
 202                 .platform_data  = &tmu2_platform_data,
 203         },
 204         .resource       = tmu2_resources,
 205         .num_resources  = ARRAY_SIZE(tmu2_resources),
 206 };
 207
 208 static struct sh_timer_config tmu3_platform_data = {
 209         .name = "TMU3",
 210         .channel_offset = 0x04,
 211         .timer_bit = 0,
 212         .clk = "tmu345_fck",
 213 };
 214
 215 static struct resource tmu3_resources[] = {
 216         [0] = {
 217                 .name   = "TMU3",
 218                 .start  = 0xffdc0008,
 219                 .end    = 0xffdc0013,
 220                 .flags  = IORESOURCE_MEM,
 221         },
 222         [1] = {
 223                 .start  = 96,
 224                 .flags  = IORESOURCE_IRQ,
 225         },
 226 };
 227
 228 static struct platform_device tmu3_device = {
 229         .name           = "sh_tmu",
 230         .id             = 3,
 231         .dev = {
 232                 .platform_data  = &tmu3_platform_data,
 233         },
 234         .resource       = tmu3_resources,
 235         .num_resources  = ARRAY_SIZE(tmu3_resources),
 236 };
 237
 238 static struct sh_timer_config tmu4_platform_data = {
 239         .name = "TMU4",
 240         .channel_offset = 0x10,
 241         .timer_bit = 1,
 242         .clk = "tmu345_fck",
 243 };
 244
 245 static struct resource tmu4_resources[] = {
 246         [0] = {
 247                 .name   = "TMU4",
 248                 .start  = 0xffdc0014,
 249                 .end    = 0xffdc001f,
 250                 .flags  = IORESOURCE_MEM,
 251         },
 252         [1] = {
 253                 .start  = 97,
 254                 .flags  = IORESOURCE_IRQ,
 255         },
 256 };
 257
 258 static struct platform_device tmu4_device = {
 259         .name           = "sh_tmu",
 260         .id             = 4,
 261         .dev = {
 262                 .platform_data  = &tmu4_platform_data,
 263         },
 264         .resource       = tmu4_resources,
 265         .num_resources  = ARRAY_SIZE(tmu4_resources),
 266 };
 267
 268 static struct sh_timer_config tmu5_platform_data = {
 269         .name = "TMU5",
 270         .channel_offset = 0x1c,
 271         .timer_bit = 2,
 272         .clk = "tmu345_fck",
 273 };
 274
 275 static struct resource tmu5_resources[] = {
 276         [0] = {
 277                 .name   = "TMU5",
 278                 .start  = 0xffdc0020,
 279                 .end    = 0xffdc002b,
 280                 .flags  = IORESOURCE_MEM,
 281         },
 282         [1] = {
 283                 .start  = 98,
 284                 .flags  = IORESOURCE_IRQ,
 285         },
 286 };
 287
 288 static struct platform_device tmu5_device = {
 289         .name           = "sh_tmu",
 290         .id             = 5,
 291         .dev = {
 292                 .platform_data  = &tmu5_platform_data,
 293         },
 294         .resource       = tmu5_resources,
 295         .num_resources  = ARRAY_SIZE(tmu5_resources),
 296 };
 297
 298 static struct sh_dmae_pdata dma_platform_data = {
 299         .mode = (SHDMA_MIX_IRQ | SHDMA_DMAOR1),
 300 };
 301
 302 static struct platform_device dma_device = {
 303         .name           = "sh-dma-engine",
 304         .id             = -1,
 305         .dev            = {
 306                 .platform_data  = &dma_platform_data,
 307         },
 308 };
 309
 310 static struct platform_device *sh7785_devices[] __initdata = {
 311         &scif0_device,
 312         &scif1_device,
 313         &scif2_device,
 314         &scif3_device,
 315         &scif4_device,
 316         &scif5_device,
 317         &tmu0_device,
 318         &tmu1_device,
 319         &tmu2_device,
 320         &tmu3_device,
 321         &tmu4_device,
 322         &tmu5_device,
 323         &dma_device,
 324 };
 325
 326 static int __init sh7785_devices_setup(void)
 327 {
 328         return platform_add_devices(sh7785_devices,
 329                                     ARRAY_SIZE(sh7785_devices));
 330 }
 331 arch_initcall(sh7785_devices_setup);
 332
 333 static struct platform_device *sh7785_early_devices[] __initdata = {
 334         &scif0_device,
 335         &scif1_device,
 336         &scif2_device,
 337         &scif3_device,
 338         &scif4_device,
 339         &scif5_device,
 340         &tmu0_device,
 341         &tmu1_device,
 342         &tmu2_device,
 343         &tmu3_device,
 344         &tmu4_device,
 345         &tmu5_device,
 346 };
 347
 348 void __init plat_early_device_setup(void)
 349 {
 350         early_platform_add_devices(sh7785_early_devices,
 351                                    ARRAY_SIZE(sh7785_early_devices));
 352 }
 353
 354 enum {
 355         UNUSED = 0,
 356
 357         /* interrupt sources */
 358
 359         IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
 360         IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
 361         IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
 362         IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
 363
 364         IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
 365         IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
 366         IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
 367         IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
 368
 369         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 370         WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
 371         HUDI, DMAC0, SCIF0, SCIF1, DMAC1, HSPI,
 372         SCIF2, SCIF3, SCIF4, SCIF5,
 373         PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
 374         SIOF, MMCIF, DU, GDTA,
 375         TMU3, TMU4, TMU5,
 376         SSI0, SSI1,
 377         HAC0, HAC1,
 378         FLCTL, GPIO,
 379
 380         /* interrupt groups */
 381
 382         TMU012, TMU345
 383 };
 384
 385 static struct intc_vect vectors[] __initdata = {
 386         INTC_VECT(WDT, 0x560),
 387         INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
 388         INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
 389         INTC_VECT(HUDI, 0x600),
 390         INTC_VECT(DMAC0, 0x620), INTC_VECT(DMAC0, 0x640),
 391         INTC_VECT(DMAC0, 0x660), INTC_VECT(DMAC0, 0x680),
 392         INTC_VECT(DMAC0, 0x6a0), INTC_VECT(DMAC0, 0x6c0),
 393         INTC_VECT(DMAC0, 0x6e0),
 394         INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
 395         INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
 396         INTC_VECT(SCIF1, 0x780), INTC_VECT(SCIF1, 0x7a0),
 397         INTC_VECT(SCIF1, 0x7c0), INTC_VECT(SCIF1, 0x7e0),
 398         INTC_VECT(DMAC1, 0x880), INTC_VECT(DMAC1, 0x8a0),
 399         INTC_VECT(DMAC1, 0x8c0), INTC_VECT(DMAC1, 0x8e0),
 400         INTC_VECT(DMAC1, 0x900), INTC_VECT(DMAC1, 0x920),
 401         INTC_VECT(DMAC1, 0x940),
 402         INTC_VECT(HSPI, 0x960),
 403         INTC_VECT(SCIF2, 0x980), INTC_VECT(SCIF3, 0x9a0),
 404         INTC_VECT(SCIF4, 0x9c0), INTC_VECT(SCIF5, 0x9e0),
 405         INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
 406         INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
 407         INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
 408         INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
 409         INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
 410         INTC_VECT(SIOF, 0xc00),
 411         INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
 412         INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
 413         INTC_VECT(DU, 0xd80),
 414         INTC_VECT(GDTA, 0xda0), INTC_VECT(GDTA, 0xdc0),
 415         INTC_VECT(GDTA, 0xde0),
 416         INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
 417         INTC_VECT(TMU5, 0xe40),
 418         INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
 419         INTC_VECT(HAC0, 0xec0), INTC_VECT(HAC1, 0xee0),
 420         INTC_VECT(FLCTL, 0xf00), INTC_VECT(FLCTL, 0xf20),
 421         INTC_VECT(FLCTL, 0xf40), INTC_VECT(FLCTL, 0xf60),
 422         INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
 423         INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
 424 };
 425
 426 static struct intc_group groups[] __initdata = {
 427         INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
 428         INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
 429 };
 430
 431 static struct intc_mask_reg mask_registers[] __initdata = {
 432         { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
 433           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 434
 435         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
 436           { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
 437             IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
 438             IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
 439             IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
 440             IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
 441             IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
 442             IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
 443             IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
 444
 445         { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
 446           { 0, 0, 0, GDTA, DU, SSI0, SSI1, GPIO,
 447             FLCTL, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB,
 448             PCIINTA, PCISERR, HAC1, HAC0, DMAC1, DMAC0, HUDI, WDT,
 449             SCIF5, SCIF4, SCIF3, SCIF2, SCIF1, SCIF0, TMU345, TMU012 } },
 450 };
 451
 452 static struct intc_prio_reg prio_registers[] __initdata = {
 453         { 0xffd00010, 0, 32, 4, /* INTPRI */   { IRQ0, IRQ1, IRQ2, IRQ3,
 454                                                  IRQ4, IRQ5, IRQ6, IRQ7 } },
 455         { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
 456                                                  TMU2, TMU2_TICPI } },
 457         { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, } },
 458         { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1,
 459                                                  SCIF2, SCIF3 } },
 460         { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { SCIF4, SCIF5, WDT, } },
 461         { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { HUDI, DMAC0, DMAC1, } },
 462         { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { HAC0, HAC1,
 463                                                  PCISERR, PCIINTA } },
 464         { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { PCIINTB, PCIINTC,
 465                                                  PCIINTD, PCIC5 } },
 466         { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { SIOF, HSPI, MMCIF, } },
 467         { 0xffd40020, 0, 32, 8, /* INT2PRI8 */ { FLCTL, GPIO, SSI0, SSI1, } },
 468         { 0xffd40024, 0, 32, 8, /* INT2PRI9 */ { DU, GDTA, } },
 469 };
 470
 471 static DECLARE_INTC_DESC(intc_desc, "sh7785", vectors, groups,
 472                          mask_registers, prio_registers, NULL);
 473
 474 /* Support for external interrupt pins in IRQ mode */
 475
 476 static struct intc_vect vectors_irq0123[] __initdata = {
 477         INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
 478         INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
 479 };
 480
 481 static struct intc_vect vectors_irq4567[] __initdata = {
 482         INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
 483         INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
 484 };
 485
 486 static struct intc_sense_reg sense_registers[] __initdata = {
 487         { 0xffd0001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
 488                                             IRQ4, IRQ5, IRQ6, IRQ7 } },
 489 };
 490
 491 static struct intc_mask_reg ack_registers[] __initdata = {
 492         { 0xffd00024, 0, 32, /* INTREQ */
 493           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 494 };
 495
 496 static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7785-irq0123",
 497                              vectors_irq0123, NULL, mask_registers,
 498                              prio_registers, sense_registers, ack_registers);
 499
 500 static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7785-irq4567",
 501                              vectors_irq4567, NULL, mask_registers,
 502                              prio_registers, sense_registers, ack_registers);
 503
 504 /* External interrupt pins in IRL mode */
 505
 506 static struct intc_vect vectors_irl0123[] __initdata = {
 507         INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
 508         INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
 509         INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
 510         INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
 511         INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
 512         INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
 513         INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
 514         INTC_VECT(IRL0_HHHL, 0x3c0),
 515 };
 516
 517 static struct intc_vect vectors_irl4567[] __initdata = {
 518         INTC_VECT(IRL4_LLLL, 0xb00), INTC_VECT(IRL4_LLLH, 0xb20),
 519         INTC_VECT(IRL4_LLHL, 0xb40), INTC_VECT(IRL4_LLHH, 0xb60),
 520         INTC_VECT(IRL4_LHLL, 0xb80), INTC_VECT(IRL4_LHLH, 0xba0),
 521         INTC_VECT(IRL4_LHHL, 0xbc0), INTC_VECT(IRL4_LHHH, 0xbe0),
 522         INTC_VECT(IRL4_HLLL, 0xc00), INTC_VECT(IRL4_HLLH, 0xc20),
 523         INTC_VECT(IRL4_HLHL, 0xc40), INTC_VECT(IRL4_HLHH, 0xc60),
 524         INTC_VECT(IRL4_HHLL, 0xc80), INTC_VECT(IRL4_HHLH, 0xca0),
 525         INTC_VECT(IRL4_HHHL, 0xcc0),
 526 };
 527
 528 static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7785-irl0123", vectors_irl0123,
 529                          NULL, mask_registers, NULL, NULL);
 530
 531 static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7785-irl4567", vectors_irl4567,
 532                          NULL, mask_registers, NULL, NULL);
 533
 534 #define INTC_ICR0       0xffd00000
 535 #define INTC_INTMSK0    0xffd00044
 536 #define INTC_INTMSK1    0xffd00048
 537 #define INTC_INTMSK2    0xffd40080
 538 #define INTC_INTMSKCLR1 0xffd00068
 539 #define INTC_INTMSKCLR2 0xffd40084
 540
 541 void __init plat_irq_setup(void)
 542 {
 543         /* disable IRQ3-0 + IRQ7-4 */
 544         __raw_writel(0xff000000, INTC_INTMSK0);
 545
 546         /* disable IRL3-0 + IRL7-4 */
 547         __raw_writel(0xc0000000, INTC_INTMSK1);
 548         __raw_writel(0xfffefffe, INTC_INTMSK2);
 549
 550         /* select IRL mode for IRL3-0 + IRL7-4 */
 551         __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
 552
 553         /* disable holding function, ie enable "SH-4 Mode" */
 554         __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
 555
 556         register_intc_controller(&intc_desc);
 557 }
 558
 559 void __init plat_irq_setup_pins(int mode)
 560 {
 561         switch (mode) {
 562         case IRQ_MODE_IRQ7654:
 563                 /* select IRQ mode for IRL7-4 */
 564                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
 565                 register_intc_controller(&intc_desc_irq4567);
 566                 break;
 567         case IRQ_MODE_IRQ3210:
 568                 /* select IRQ mode for IRL3-0 */
 569                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
 570                 register_intc_controller(&intc_desc_irq0123);
 571                 break;
 572         case IRQ_MODE_IRL7654:
 573                 /* enable IRL7-4 but don't provide any masking */
 574                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
 575                 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
 576                 break;
 577         case IRQ_MODE_IRL3210:
 578                 /* enable IRL0-3 but don't provide any masking */
 579                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
 580                 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
 581                 break;
 582         case IRQ_MODE_IRL7654_MASK:
 583                 /* enable IRL7-4 and mask using cpu intc controller */
 584                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
 585                 register_intc_controller(&intc_desc_irl4567);
 586                 break;
 587         case IRQ_MODE_IRL3210_MASK:
 588                 /* enable IRL0-3 and mask using cpu intc controller */
 589                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
 590                 register_intc_controller(&intc_desc_irl0123);
 591                 break;
 592         default:
 593                 BUG();
 594         }
 595 }
 596
 597 void __init plat_mem_setup(void)
 598 {
 599         /* Register the URAM space as Node 1 */
 600         setup_bootmem_node(1, 0xe55f0000, 0xe5610000);
 601 }