SAFE public projects git trees. - safe/jmp/linux-2.6/blob - arch/sh/kernel/cpu/sh4a/setup-sh7757.c

   1 /*
   2  * SH7757 Setup
   3  *
   4  * Copyright (C) 2009  Renesas Solutions Corp.
   5  *
   6  *  based on setup-sh7785.c : Copyright (C) 2007  Paul Mundt
   7  *
   8  * This file is subject to the terms and conditions of the GNU General Public
   9  * License.  See the file "COPYING" in the main directory of this archive
  10  * for more details.
  11  */
  12 #include <linux/platform_device.h>
  13 #include <linux/init.h>
  14 #include <linux/serial.h>
  15 #include <linux/serial_sci.h>
  16 #include <linux/io.h>
  17 #include <linux/mm.h>
  18 #include <linux/sh_timer.h>
  19
  20 static struct plat_sci_port scif2_platform_data = {
  21         .mapbase        = 0xfe4b0000,           /* SCIF2 */
  22         .flags          = UPF_BOOT_AUTOCONF,
  23         .type           = PORT_SCIF,
  24         .irqs           = { 40, 40, 40, 40 },
  25 };
  26
  27 static struct platform_device scif2_device = {
  28         .name           = "sh-sci",
  29         .id             = 2,
  30         .dev            = {
  31                 .platform_data  = &scif2_platform_data,
  32         },
  33 };
  34
  35 static struct plat_sci_port scif3_platform_data = {
  36         .mapbase        = 0xfe4c0000,           /* SCIF3 */
  37         .flags          = UPF_BOOT_AUTOCONF,
  38         .type           = PORT_SCIF,
  39         .irqs           = { 76, 76, 76, 76 },
  40 };
  41
  42 static struct platform_device scif3_device = {
  43         .name           = "sh-sci",
  44         .id             = 3,
  45         .dev            = {
  46                 .platform_data  = &scif3_platform_data,
  47         },
  48 };
  49
  50 static struct plat_sci_port scif4_platform_data = {
  51         .mapbase        = 0xfe4d0000,           /* SCIF4 */
  52         .flags          = UPF_BOOT_AUTOCONF,
  53         .type           = PORT_SCIF,
  54         .irqs           = { 104, 104, 104, 104 },
  55 };
  56
  57 static struct platform_device scif4_device = {
  58         .name           = "sh-sci",
  59         .id             = 4,
  60         .dev            = {
  61                 .platform_data  = &scif4_platform_data,
  62         },
  63 };
  64
  65 static struct sh_timer_config tmu0_platform_data = {
  66         .channel_offset = 0x04,
  67         .timer_bit = 0,
  68         .clk = "peripheral_clk",
  69         .clockevent_rating = 200,
  70 };
  71
  72 static struct resource tmu0_resources[] = {
  73         [0] = {
  74                 .start  = 0xfe430008,
  75                 .end    = 0xfe430013,
  76                 .flags  = IORESOURCE_MEM,
  77         },
  78         [1] = {
  79                 .start  = 28,
  80                 .flags  = IORESOURCE_IRQ,
  81         },
  82 };
  83
  84 static struct platform_device tmu0_device = {
  85         .name           = "sh_tmu",
  86         .id             = 0,
  87         .dev = {
  88                 .platform_data  = &tmu0_platform_data,
  89         },
  90         .resource       = tmu0_resources,
  91         .num_resources  = ARRAY_SIZE(tmu0_resources),
  92 };
  93
  94 static struct sh_timer_config tmu1_platform_data = {
  95         .channel_offset = 0x10,
  96         .timer_bit = 1,
  97         .clk = "peripheral_clk",
  98         .clocksource_rating = 200,
  99 };
 100
 101 static struct resource tmu1_resources[] = {
 102         [0] = {
 103                 .start  = 0xfe430014,
 104                 .end    = 0xfe43001f,
 105                 .flags  = IORESOURCE_MEM,
 106         },
 107         [1] = {
 108                 .start  = 29,
 109                 .flags  = IORESOURCE_IRQ,
 110         },
 111 };
 112
 113 static struct platform_device tmu1_device = {
 114         .name           = "sh_tmu",
 115         .id             = 1,
 116         .dev = {
 117                 .platform_data  = &tmu1_platform_data,
 118         },
 119         .resource       = tmu1_resources,
 120         .num_resources  = ARRAY_SIZE(tmu1_resources),
 121 };
 122
 123 static struct platform_device *sh7757_devices[] __initdata = {
 124         &scif2_device,
 125         &scif3_device,
 126         &scif4_device,
 127         &tmu0_device,
 128         &tmu1_device,
 129 };
 130
 131 static int __init sh7757_devices_setup(void)
 132 {
 133         return platform_add_devices(sh7757_devices,
 134                                     ARRAY_SIZE(sh7757_devices));
 135 }
 136 arch_initcall(sh7757_devices_setup);
 137
 138 static struct platform_device *sh7757_early_devices[] __initdata = {
 139         &scif2_device,
 140         &scif3_device,
 141         &scif4_device,
 142         &tmu0_device,
 143         &tmu1_device,
 144 };
 145
 146 void __init plat_early_device_setup(void)
 147 {
 148         early_platform_add_devices(sh7757_early_devices,
 149                                    ARRAY_SIZE(sh7757_early_devices));
 150 }
 151
 152 enum {
 153         UNUSED = 0,
 154
 155         /* interrupt sources */
 156
 157         IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
 158         IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
 159         IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
 160         IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
 161
 162         IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
 163         IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
 164         IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
 165         IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
 166         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 167
 168         SDHI,
 169         DVC,
 170         IRQ8, IRQ9, IRQ10,
 171         WDT0,
 172         TMU0, TMU1, TMU2, TMU2_TICPI,
 173         HUDI,
 174
 175         ARC4,
 176         DMAC0,
 177         IRQ11,
 178         SCIF2,
 179         DMAC1_6,
 180         USB0,
 181         IRQ12,
 182         JMC,
 183         SPI1,
 184         IRQ13, IRQ14,
 185         USB1,
 186         TMR01, TMR23, TMR45,
 187         WDT1,
 188         FRT,
 189         LPC,
 190         SCIF0, SCIF1, SCIF3,
 191         PECI0I, PECI1I, PECI2I,
 192         IRQ15,
 193         ETHERC,
 194         SPI0,
 195         ADC1,
 196         DMAC1_8,
 197         SIM,
 198         TMU3, TMU4, TMU5,
 199         ADC0,
 200         SCIF4,
 201         IIC0_0, IIC0_1, IIC0_2, IIC0_3,
 202         IIC1_0, IIC1_1, IIC1_2, IIC1_3,
 203         IIC2_0, IIC2_1, IIC2_2, IIC2_3,
 204         IIC3_0, IIC3_1, IIC3_2, IIC3_3,
 205         IIC4_0, IIC4_1, IIC4_2, IIC4_3,
 206         IIC5_0, IIC5_1, IIC5_2, IIC5_3,
 207         IIC6_0, IIC6_1, IIC6_2, IIC6_3,
 208         IIC7_0, IIC7_1, IIC7_2, IIC7_3,
 209         IIC8_0, IIC8_1, IIC8_2, IIC8_3,
 210         IIC9_0, IIC9_1, IIC9_2, IIC9_3,
 211         PCIINTA,
 212         PCIE,
 213         SGPIO,
 214
 215         /* interrupt groups */
 216
 217         TMU012, TMU345,
 218 };
 219
 220 static struct intc_vect vectors[] __initdata = {
 221         INTC_VECT(SDHI, 0x480), INTC_VECT(SDHI, 0x04a0),
 222         INTC_VECT(SDHI, 0x4c0),
 223         INTC_VECT(DVC, 0x4e0),
 224         INTC_VECT(IRQ8, 0x500), INTC_VECT(IRQ9, 0x520),
 225         INTC_VECT(IRQ10, 0x540),
 226         INTC_VECT(WDT0, 0x560),
 227         INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
 228         INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
 229         INTC_VECT(HUDI, 0x600),
 230         INTC_VECT(ARC4, 0x620),
 231         INTC_VECT(DMAC0, 0x640), INTC_VECT(DMAC0, 0x660),
 232         INTC_VECT(DMAC0, 0x680), INTC_VECT(DMAC0, 0x6a0),
 233         INTC_VECT(DMAC0, 0x6c0),
 234         INTC_VECT(IRQ11, 0x6e0),
 235         INTC_VECT(SCIF2, 0x700), INTC_VECT(SCIF2, 0x720),
 236         INTC_VECT(SCIF2, 0x740), INTC_VECT(SCIF2, 0x760),
 237         INTC_VECT(DMAC0, 0x780), INTC_VECT(DMAC0, 0x7a0),
 238         INTC_VECT(DMAC1_6, 0x7c0), INTC_VECT(DMAC1_6, 0x7e0),
 239         INTC_VECT(USB0, 0x840),
 240         INTC_VECT(IRQ12, 0x880),
 241         INTC_VECT(JMC, 0x8a0),
 242         INTC_VECT(SPI1, 0x8c0),
 243         INTC_VECT(IRQ13, 0x8e0), INTC_VECT(IRQ14, 0x900),
 244         INTC_VECT(USB1, 0x920),
 245         INTC_VECT(TMR01, 0xa00), INTC_VECT(TMR23, 0xa20),
 246         INTC_VECT(TMR45, 0xa40),
 247         INTC_VECT(WDT1, 0xa60),
 248         INTC_VECT(FRT, 0xa80),
 249         INTC_VECT(LPC, 0xaa0), INTC_VECT(LPC, 0xac0),
 250         INTC_VECT(LPC, 0xae0), INTC_VECT(LPC, 0xb00),
 251         INTC_VECT(LPC, 0xb20),
 252         INTC_VECT(SCIF0, 0xb40), INTC_VECT(SCIF1, 0xb60),
 253         INTC_VECT(SCIF3, 0xb80), INTC_VECT(SCIF3, 0xba0),
 254         INTC_VECT(SCIF3, 0xbc0), INTC_VECT(SCIF3, 0xbe0),
 255         INTC_VECT(PECI0I, 0xc00), INTC_VECT(PECI1I, 0xc20),
 256         INTC_VECT(PECI2I, 0xc40),
 257         INTC_VECT(IRQ15, 0xc60),
 258         INTC_VECT(ETHERC, 0xc80), INTC_VECT(ETHERC, 0xca0),
 259         INTC_VECT(SPI0, 0xcc0),
 260         INTC_VECT(ADC1, 0xce0),
 261         INTC_VECT(DMAC1_8, 0xd00), INTC_VECT(DMAC1_8, 0xd20),
 262         INTC_VECT(DMAC1_8, 0xd40), INTC_VECT(DMAC1_8, 0xd60),
 263         INTC_VECT(SIM, 0xd80), INTC_VECT(SIM, 0xda0),
 264         INTC_VECT(SIM, 0xdc0), INTC_VECT(SIM, 0xde0),
 265         INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
 266         INTC_VECT(TMU5, 0xe40),
 267         INTC_VECT(ADC0, 0xe60),
 268         INTC_VECT(SCIF4, 0xf00), INTC_VECT(SCIF4, 0xf20),
 269         INTC_VECT(SCIF4, 0xf40), INTC_VECT(SCIF4, 0xf60),
 270         INTC_VECT(IIC0_0, 0x1400), INTC_VECT(IIC0_1, 0x1420),
 271         INTC_VECT(IIC0_2, 0x1440), INTC_VECT(IIC0_3, 0x1460),
 272         INTC_VECT(IIC1_0, 0x1480), INTC_VECT(IIC1_1, 0x14e0),
 273         INTC_VECT(IIC1_2, 0x1500), INTC_VECT(IIC1_3, 0x1520),
 274         INTC_VECT(IIC2_0, 0x1540), INTC_VECT(IIC2_1, 0x1560),
 275         INTC_VECT(IIC2_2, 0x1580), INTC_VECT(IIC2_3, 0x1600),
 276         INTC_VECT(IIC3_0, 0x1620), INTC_VECT(IIC3_1, 0x1640),
 277         INTC_VECT(IIC3_2, 0x16e0), INTC_VECT(IIC3_3, 0x1700),
 278         INTC_VECT(IIC4_0, 0x17c0), INTC_VECT(IIC4_1, 0x1800),
 279         INTC_VECT(IIC4_2, 0x1820), INTC_VECT(IIC4_3, 0x1840),
 280         INTC_VECT(IIC5_0, 0x1860), INTC_VECT(IIC5_1, 0x1880),
 281         INTC_VECT(IIC5_2, 0x18a0), INTC_VECT(IIC5_3, 0x18c0),
 282         INTC_VECT(IIC6_0, 0x18e0), INTC_VECT(IIC6_1, 0x1900),
 283         INTC_VECT(IIC6_2, 0x1920), INTC_VECT(IIC6_3, 0x1980),
 284         INTC_VECT(IIC7_0, 0x19a0), INTC_VECT(IIC7_1, 0x1a00),
 285         INTC_VECT(IIC7_2, 0x1a20), INTC_VECT(IIC7_3, 0x1a40),
 286         INTC_VECT(IIC8_0, 0x1a60), INTC_VECT(IIC8_1, 0x1a80),
 287         INTC_VECT(IIC8_2, 0x1aa0), INTC_VECT(IIC8_3, 0x1b40),
 288         INTC_VECT(IIC9_0, 0x1b60), INTC_VECT(IIC9_1, 0x1b80),
 289         INTC_VECT(IIC9_2, 0x1c00), INTC_VECT(IIC9_3, 0x1c20),
 290         INTC_VECT(PCIINTA, 0x1ce0),
 291         INTC_VECT(PCIE, 0x1e00),
 292         INTC_VECT(SGPIO, 0x1f80),
 293         INTC_VECT(SGPIO, 0x1fa0),
 294 };
 295
 296 static struct intc_group groups[] __initdata = {
 297         INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
 298         INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
 299 };
 300
 301 static struct intc_mask_reg mask_registers[] __initdata = {
 302         { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
 303           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 304
 305         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
 306           { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
 307             IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
 308             IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
 309             IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
 310             IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
 311             IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
 312             IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
 313             IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
 314
 315         { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
 316           { 0, 0, 0, 0, 0, 0, 0, 0,
 317             0, DMAC1_8, 0, PECI0I, LPC, FRT, WDT1, TMR45,
 318             TMR23, TMR01, 0, 0, 0, 0, 0, DMAC0,
 319             HUDI, 0, WDT0, SCIF3, SCIF2, SDHI, TMU345, TMU012
 320              } },
 321
 322         { 0xffd400d0, 0xffd400d4, 32, /* INT2MSKR1 / INT2MSKCR1 */
 323           { IRQ15, IRQ14, IRQ13, IRQ12, IRQ11, IRQ10, SCIF4, ETHERC,
 324             IRQ9, IRQ8, SCIF1, SCIF0, USB0, 0, 0, USB1,
 325             ADC1, 0, DMAC1_6, ADC0, SPI0, SIM, PECI2I, PECI1I,
 326             ARC4, 0, SPI1, JMC, 0, 0, 0, DVC
 327              } },
 328
 329         { 0xffd10038, 0xffd1003c, 32, /* INT2MSKR2 / INT2MSKCR2 */
 330           { IIC4_1, IIC4_2, IIC5_0, 0, 0, 0, SGPIO, 0,
 331             0, 0, 0, IIC9_2, IIC8_2, IIC8_1, IIC8_0, IIC7_3,
 332             IIC7_2, IIC7_1, IIC6_3, IIC0_0, IIC0_1, IIC0_2, IIC0_3, IIC3_1,
 333             IIC2_3, 0, IIC2_1, IIC9_1, IIC3_3, IIC1_0, PCIE, IIC2_2
 334              } },
 335
 336         { 0xffd100d0, 0xff1400d4, 32, /* INT2MSKR3 / INT2MSKCR4 */
 337           { 0, IIC6_1, IIC6_0, IIC5_1, IIC3_2, IIC2_0, 0, 0,
 338             IIC1_3, IIC1_2, IIC9_0, IIC8_3, IIC4_3, IIC7_0, 0, IIC6_2,
 339             PCIINTA, 0, IIC4_0, 0, 0, 0, 0, IIC9_3,
 340             IIC3_0, 0, IIC5_3, IIC5_2, 0, 0, 0, IIC1_1
 341              } },
 342 };
 343
 344 #define INTPRI          0xffd00010
 345 #define INT2PRI0        0xffd40000
 346 #define INT2PRI1        0xffd40004
 347 #define INT2PRI2        0xffd40008
 348 #define INT2PRI3        0xffd4000c
 349 #define INT2PRI4        0xffd40010
 350 #define INT2PRI5        0xffd40014
 351 #define INT2PRI6        0xffd40018
 352 #define INT2PRI7        0xffd4001c
 353 #define INT2PRI8        0xffd400a0
 354 #define INT2PRI9        0xffd400a4
 355 #define INT2PRI10       0xffd400a8
 356 #define INT2PRI11       0xffd400ac
 357 #define INT2PRI12       0xffd400b0
 358 #define INT2PRI13       0xffd400b4
 359 #define INT2PRI14       0xffd400b8
 360 #define INT2PRI15       0xffd400bc
 361 #define INT2PRI16       0xffd10000
 362 #define INT2PRI17       0xffd10004
 363 #define INT2PRI18       0xffd10008
 364 #define INT2PRI19       0xffd1000c
 365 #define INT2PRI20       0xffd10010
 366 #define INT2PRI21       0xffd10014
 367 #define INT2PRI22       0xffd10018
 368 #define INT2PRI23       0xffd1001c
 369 #define INT2PRI24       0xffd100a0
 370 #define INT2PRI25       0xffd100a4
 371 #define INT2PRI26       0xffd100a8
 372 #define INT2PRI27       0xffd100ac
 373 #define INT2PRI28       0xffd100b0
 374 #define INT2PRI29       0xffd100b4
 375 #define INT2PRI30       0xffd100b8
 376 #define INT2PRI31       0xffd100bc
 377
 378 static struct intc_prio_reg prio_registers[] __initdata = {
 379         { INTPRI, 0, 32, 4, { IRQ0, IRQ1, IRQ2, IRQ3,
 380                               IRQ4, IRQ5, IRQ6, IRQ7 } },
 381
 382         { INT2PRI0, 0, 32, 8, { TMU0, TMU1, TMU2, TMU2_TICPI } },
 383         { INT2PRI1, 0, 32, 8, { TMU3, TMU4, TMU5, SDHI } },
 384         { INT2PRI2, 0, 32, 8, { SCIF2, SCIF3, WDT0, IRQ8 } },
 385         { INT2PRI3, 0, 32, 8, { HUDI, DMAC0, ADC0, IRQ9 } },
 386         { INT2PRI4, 0, 32, 8, { IRQ10, 0, TMR01, TMR23 } },
 387         { INT2PRI5, 0, 32, 8, { TMR45, WDT1, FRT, LPC } },
 388         { INT2PRI6, 0, 32, 8, { PECI0I, ETHERC, DMAC1_8, 0 } },
 389         { INT2PRI7, 0, 32, 8, { SCIF4, 0, IRQ11, IRQ12 } },
 390         { INT2PRI8, 0, 32, 8, { 0, 0, 0, DVC } },
 391         { INT2PRI9, 0, 32, 8, { ARC4, 0, SPI1, JMC } },
 392         { INT2PRI10, 0, 32, 8, { SPI0, SIM, PECI2I, PECI1I } },
 393         { INT2PRI11, 0, 32, 8, { ADC1, IRQ13, DMAC1_6, IRQ14 } },
 394         { INT2PRI12, 0, 32, 8, { USB0, 0, IRQ15, USB1 } },
 395         { INT2PRI13, 0, 32, 8, { 0, 0, SCIF1, SCIF0 } },
 396
 397         { INT2PRI16, 0, 32, 8, { IIC2_2, 0, 0, 0 } },
 398         { INT2PRI17, 0, 32, 8, { PCIE, 0, 0, IIC1_0 } },
 399         { INT2PRI18, 0, 32, 8, { IIC3_3, IIC9_1, IIC2_1, IIC1_2 } },
 400         { INT2PRI19, 0, 32, 8, { IIC2_3, IIC3_1, 0, IIC1_3 } },
 401         { INT2PRI20, 0, 32, 8, { IIC2_0, IIC6_3, IIC7_1, IIC7_2 } },
 402         { INT2PRI21, 0, 32, 8, { IIC7_3, IIC8_0, IIC8_1, IIC8_2 } },
 403         { INT2PRI22, 0, 32, 8, { IIC9_2, 0, 0, 0 } },
 404         { INT2PRI23, 0, 32, 8, { 0, SGPIO, IIC3_2, IIC5_1 } },
 405         { INT2PRI24, 0, 32, 8, { 0, 0, 0, IIC1_1 } },
 406         { INT2PRI25, 0, 32, 8, { IIC3_0, 0, IIC5_3, IIC5_2 } },
 407         { INT2PRI26, 0, 32, 8, { 0, 0, 0, IIC9_3 } },
 408         { INT2PRI27, 0, 32, 8, { PCIINTA, IIC6_0, IIC4_0, IIC6_1 } },
 409         { INT2PRI28, 0, 32, 8, { IIC4_3, IIC7_0, 0, IIC6_2 } },
 410         { INT2PRI29, 0, 32, 8, { 0, 0, IIC9_0, IIC8_3 } },
 411         { INT2PRI30, 0, 32, 8, { IIC4_1, IIC4_2, IIC5_0, 0 } },
 412         { INT2PRI31, 0, 32, 8, { IIC0_0, IIC0_1, IIC0_2, IIC0_3 } },
 413 };
 414
 415 static DECLARE_INTC_DESC(intc_desc, "sh7757", vectors, groups,
 416                          mask_registers, prio_registers, NULL);
 417
 418 /* Support for external interrupt pins in IRQ mode */
 419 static struct intc_vect vectors_irq0123[] __initdata = {
 420         INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
 421         INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
 422 };
 423
 424 static struct intc_vect vectors_irq4567[] __initdata = {
 425         INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
 426         INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
 427 };
 428
 429 static struct intc_sense_reg sense_registers[] __initdata = {
 430         { 0xffd0001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
 431                                             IRQ4, IRQ5, IRQ6, IRQ7 } },
 432 };
 433
 434 static struct intc_mask_reg ack_registers[] __initdata = {
 435         { 0xffd00024, 0, 32, /* INTREQ */
 436           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 437 };
 438
 439 static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7757-irq0123",
 440                              vectors_irq0123, NULL, mask_registers,
 441                              prio_registers, sense_registers, ack_registers);
 442
 443 static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7757-irq4567",
 444                              vectors_irq4567, NULL, mask_registers,
 445                              prio_registers, sense_registers, ack_registers);
 446
 447 /* External interrupt pins in IRL mode */
 448 static struct intc_vect vectors_irl0123[] __initdata = {
 449         INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
 450         INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
 451         INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
 452         INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
 453         INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
 454         INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
 455         INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
 456         INTC_VECT(IRL0_HHHL, 0x3c0),
 457 };
 458
 459 static struct intc_vect vectors_irl4567[] __initdata = {
 460         INTC_VECT(IRL4_LLLL, 0xb00), INTC_VECT(IRL4_LLLH, 0xb20),
 461         INTC_VECT(IRL4_LLHL, 0xb40), INTC_VECT(IRL4_LLHH, 0xb60),
 462         INTC_VECT(IRL4_LHLL, 0xb80), INTC_VECT(IRL4_LHLH, 0xba0),
 463         INTC_VECT(IRL4_LHHL, 0xbc0), INTC_VECT(IRL4_LHHH, 0xbe0),
 464         INTC_VECT(IRL4_HLLL, 0xc00), INTC_VECT(IRL4_HLLH, 0xc20),
 465         INTC_VECT(IRL4_HLHL, 0xc40), INTC_VECT(IRL4_HLHH, 0xc60),
 466         INTC_VECT(IRL4_HHLL, 0xc80), INTC_VECT(IRL4_HHLH, 0xca0),
 467         INTC_VECT(IRL4_HHHL, 0xcc0),
 468 };
 469
 470 static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7757-irl0123", vectors_irl0123,
 471                          NULL, mask_registers, NULL, NULL);
 472
 473 static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7757-irl4567", vectors_irl4567,
 474                          NULL, mask_registers, NULL, NULL);
 475
 476 #define INTC_ICR0       0xffd00000
 477 #define INTC_INTMSK0    0xffd00044
 478 #define INTC_INTMSK1    0xffd00048
 479 #define INTC_INTMSK2    0xffd40080
 480 #define INTC_INTMSKCLR1 0xffd00068
 481 #define INTC_INTMSKCLR2 0xffd40084
 482
 483 void __init plat_irq_setup(void)
 484 {
 485         /* disable IRQ3-0 + IRQ7-4 */
 486         __raw_writel(0xff000000, INTC_INTMSK0);
 487
 488         /* disable IRL3-0 + IRL7-4 */
 489         __raw_writel(0xc0000000, INTC_INTMSK1);
 490         __raw_writel(0xfffefffe, INTC_INTMSK2);
 491
 492         /* select IRL mode for IRL3-0 + IRL7-4 */
 493         __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
 494
 495         /* disable holding function, ie enable "SH-4 Mode" */
 496         __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
 497
 498         register_intc_controller(&intc_desc);
 499 }
 500
 501 void __init plat_irq_setup_pins(int mode)
 502 {
 503         switch (mode) {
 504         case IRQ_MODE_IRQ7654:
 505                 /* select IRQ mode for IRL7-4 */
 506                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
 507                 register_intc_controller(&intc_desc_irq4567);
 508                 break;
 509         case IRQ_MODE_IRQ3210:
 510                 /* select IRQ mode for IRL3-0 */
 511                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
 512                 register_intc_controller(&intc_desc_irq0123);
 513                 break;
 514         case IRQ_MODE_IRL7654:
 515                 /* enable IRL7-4 but don't provide any masking */
 516                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
 517                 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
 518                 break;
 519         case IRQ_MODE_IRL3210:
 520                 /* enable IRL0-3 but don't provide any masking */
 521                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
 522                 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
 523                 break;
 524         case IRQ_MODE_IRL7654_MASK:
 525                 /* enable IRL7-4 and mask using cpu intc controller */
 526                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
 527                 register_intc_controller(&intc_desc_irl4567);
 528                 break;
 529         case IRQ_MODE_IRL3210_MASK:
 530                 /* enable IRL0-3 and mask using cpu intc controller */
 531                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
 532                 register_intc_controller(&intc_desc_irl0123);
 533                 break;
 534         default:
 535                 BUG();
 536         }
 537 }
 538
 539 void __init plat_mem_setup(void)
 540 {
 541 }