2 * Save/restore floating point context for signal handlers.
4 * Copyright (C) 1999, 2000 Kaz Kojima & Niibe Yutaka
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 * FIXME! These routines can be optimized in big endian case.
12 #include <linux/sched.h>
13 #include <linux/signal.h>
14 #include <asm/processor.h>
18 /* The PR (precision) bit in the FP Status Register must be clear when
19 * an frchg instruction is executed, otherwise the instruction is undefined.
20 * Executing frchg with PR set causes a trap on some SH4 implementations.
23 #define FPSCR_RCHG 0x00000000
27 * Save FPU registers onto task structure.
30 save_fpu(struct task_struct *tsk)
35 asm volatile("sts.l fpul, @-%0\n\t"
36 "sts.l fpscr, @-%0\n\t"
37 "fmov.s fr15, @-%0\n\t"
38 "fmov.s fr14, @-%0\n\t"
39 "fmov.s fr13, @-%0\n\t"
40 "fmov.s fr12, @-%0\n\t"
41 "fmov.s fr11, @-%0\n\t"
42 "fmov.s fr10, @-%0\n\t"
43 "fmov.s fr9, @-%0\n\t"
44 "fmov.s fr8, @-%0\n\t"
45 "fmov.s fr7, @-%0\n\t"
46 "fmov.s fr6, @-%0\n\t"
47 "fmov.s fr5, @-%0\n\t"
48 "fmov.s fr4, @-%0\n\t"
49 "fmov.s fr3, @-%0\n\t"
50 "fmov.s fr2, @-%0\n\t"
51 "fmov.s fr1, @-%0\n\t"
52 "fmov.s fr0, @-%0\n\t"
55 : "0" ((char *)(&tsk->thread.fpu.hard.status)),
64 restore_fpu(struct task_struct *tsk)
69 asm volatile("fmov.s @%0+, fr0\n\t"
70 "fmov.s @%0+, fr1\n\t"
71 "fmov.s @%0+, fr2\n\t"
72 "fmov.s @%0+, fr3\n\t"
73 "fmov.s @%0+, fr4\n\t"
74 "fmov.s @%0+, fr5\n\t"
75 "fmov.s @%0+, fr6\n\t"
76 "fmov.s @%0+, fr7\n\t"
77 "fmov.s @%0+, fr8\n\t"
78 "fmov.s @%0+, fr9\n\t"
79 "fmov.s @%0+, fr10\n\t"
80 "fmov.s @%0+, fr11\n\t"
81 "fmov.s @%0+, fr12\n\t"
82 "fmov.s @%0+, fr13\n\t"
83 "fmov.s @%0+, fr14\n\t"
84 "fmov.s @%0+, fr15\n\t"
85 "lds.l @%0+, fpscr\n\t"
86 "lds.l @%0+, fpul\n\t"
88 : "0" (&tsk->thread.fpu), "r" (FPSCR_RCHG)
94 * Load the FPU with signalling NANS. This bit pattern we're using
95 * has the property that no matter wether considered as single or as
96 * double precission represents signaling NANS.
103 asm volatile("lds %0, fpul\n\t"
114 "fsts fpul, fr10\n\t"
115 "fsts fpul, fr11\n\t"
116 "fsts fpul, fr12\n\t"
117 "fsts fpul, fr13\n\t"
118 "fsts fpul, fr14\n\t"
119 "fsts fpul, fr15\n\t"
122 : "r" (0), "r" (FPSCR_RCHG), "r" (FPSCR_INIT));
127 * Emulate arithmetic ops on denormalized number for some FPU insns.
130 /* denormalized float * float */
131 static int denormal_mulf(int hx, int hy)
134 unsigned long long m, n;
137 ix = hx & 0x7fffffff;
138 iy = hy & 0x7fffffff;
139 if (iy < 0x00800000 || ix == 0)
140 return ((hx ^ hy) & 0x80000000);
142 exp = (iy & 0x7f800000) >> 23;
144 iy = (iy & 0x007fffff) | 0x00800000;
145 m = (unsigned long long)ix * iy;
148 while (n) { n >>= 1; w++; }
150 /* FIXME: use guard bits */
153 ix = ((int) (m >> (w - 23)) & 0x007fffff) | (exp << 23);
154 else if (exp + 22 >= 0)
155 ix = (int) (m >> (w - 22 - exp)) & 0x007fffff;
159 ix |= (hx ^ hy) & 0x80000000;
163 /* denormalized double * double */
164 static void mult64(unsigned long long x, unsigned long long y,
165 unsigned long long *highp, unsigned long long *lowp)
167 unsigned long long sub0, sub1, sub2, sub3;
168 unsigned long long high, low;
170 sub0 = (x >> 32) * (unsigned long) (y >> 32);
171 sub1 = (x & 0xffffffffLL) * (unsigned long) (y >> 32);
172 sub2 = (x >> 32) * (unsigned long) (y & 0xffffffffLL);
173 sub3 = (x & 0xffffffffLL) * (unsigned long) (y & 0xffffffffLL);
176 sub3 += (sub1 << 32);
180 sub3 += (sub2 << 32);
184 high += (sub1 >> 32) + (sub2 >> 32);
190 static inline long long rshift64(unsigned long long mh,
191 unsigned long long ml, int n)
194 return mh >> (n - 64);
195 return (mh << (64 - n)) | (ml >> n);
198 static long long denormal_muld(long long hx, long long hy)
200 unsigned long long ix, iy;
201 unsigned long long mh, ml, nh, nl;
204 ix = hx & 0x7fffffffffffffffLL;
205 iy = hy & 0x7fffffffffffffffLL;
206 if (iy < 0x0010000000000000LL || ix == 0)
207 return ((hx ^ hy) & 0x8000000000000000LL);
209 exp = (iy & 0x7ff0000000000000LL) >> 52;
210 ix &= 0x000fffffffffffffLL;
211 iy = (iy & 0x000fffffffffffffLL) | 0x0010000000000000LL;
212 mult64(ix, iy, &mh, &ml);
217 while (nh) { nh >>= 1; w++;}
220 while (nl) { nl >>= 1; w++;}
222 /* FIXME: use guard bits */
223 exp += w - 1022 - 52 * 2;
225 ix = (rshift64(mh, ml, w - 52) & 0x000fffffffffffffLL)
226 | ((long long)exp << 52);
227 else if (exp + 51 >= 0)
228 ix = rshift64(mh, ml, w - 51 - exp) & 0x000fffffffffffffLL;
232 ix |= (hx ^ hy) & 0x8000000000000000LL;
236 /* ix - iy where iy: denormal and ix, iy >= 0 */
237 static int denormal_subf1(unsigned int ix, unsigned int iy)
245 exp = (ix & 0x7f800000) >> 23;
252 frac = (ix & 0x007fffff) | 0x00800000;
254 while (frac < 0x00800000) {
260 return (exp << 23) | (frac & 0x007fffff);
263 /* ix + iy where iy: denormal and ix, iy >= 0 */
264 static int denormal_addf1(unsigned int ix, unsigned int iy)
272 exp = (ix & 0x7f800000) >> 23;
279 frac = (ix & 0x007fffff) | 0x00800000;
281 if (frac >= 0x01000000) {
286 return (exp << 23) | (frac & 0x007fffff);
289 static int denormal_addf(int hx, int hy)
294 if ((hx ^ hy) & 0x80000000) {
295 sign = hx & 0x80000000;
296 ix = hx & 0x7fffffff;
297 iy = hy & 0x7fffffff;
298 if (iy < 0x00800000) {
299 ix = denormal_subf1(ix, iy);
305 ix = denormal_subf1(iy, ix);
309 sign = hx & 0x80000000;
310 ix = hx & 0x7fffffff;
311 iy = hy & 0x7fffffff;
313 ix = denormal_addf1(ix, iy);
315 ix = denormal_addf1(iy, ix);
321 /* ix - iy where iy: denormal and ix, iy >= 0 */
322 static long long denormal_subd1(unsigned long long ix, unsigned long long iy)
327 if (ix < 0x0010000000000000LL)
330 exp = (ix & 0x7ff0000000000000LL) >> 52;
337 frac = (ix & 0x000fffffffffffffLL) | 0x0010000000000000LL;
339 while (frac < 0x0010000000000000LL) {
345 return ((long long)exp << 52) | (frac & 0x000fffffffffffffLL);
348 /* ix + iy where iy: denormal and ix, iy >= 0 */
349 static long long denormal_addd1(unsigned long long ix, unsigned long long iy)
354 if (ix < 0x0010000000000000LL)
357 exp = (ix & 0x7ff0000000000000LL) >> 52;
364 frac = (ix & 0x000fffffffffffffLL) | 0x0010000000000000LL;
366 if (frac >= 0x0020000000000000LL) {
371 return (exp << 52) | (frac & 0x000fffffffffffffLL);
374 static long long denormal_addd(long long hx, long long hy)
376 unsigned long long ix, iy;
379 if ((hx ^ hy) & 0x8000000000000000LL) {
380 sign = hx & 0x8000000000000000LL;
381 ix = hx & 0x7fffffffffffffffLL;
382 iy = hy & 0x7fffffffffffffffLL;
383 if (iy < 0x0010000000000000LL) {
384 ix = denormal_subd1(ix, iy);
387 sign ^= 0x8000000000000000LL;
390 ix = denormal_subd1(iy, ix);
391 sign ^= 0x8000000000000000LL;
394 sign = hx & 0x8000000000000000LL;
395 ix = hx & 0x7fffffffffffffffLL;
396 iy = hy & 0x7fffffffffffffffLL;
397 if (iy < 0x0010000000000000LL)
398 ix = denormal_addd1(ix, iy);
400 ix = denormal_addd1(iy, ix);
407 * denormal_to_double - Given denormalized float number,
410 * @fpu: Pointer to sh_fpu_hard structure
411 * @n: Index to FP register
414 denormal_to_double (struct sh_fpu_hard_struct *fpu, int n)
416 unsigned long du, dl;
417 unsigned long x = fpu->fpul;
418 int exp = 1023 - 126;
420 if (x != 0 && (x & 0x7f800000) == 0) {
421 du = (x & 0x80000000);
422 while ((x & 0x00800000) == 0) {
427 du |= (exp << 20) | (x >> 3);
430 fpu->fp_regs[n] = du;
431 fpu->fp_regs[n+1] = dl;
436 * ieee_fpe_handler - Handle denormalized number exception
438 * @regs: Pointer to register structure
440 * Returns 1 when it's handled (should not cause exception).
443 ieee_fpe_handler (struct pt_regs *regs)
445 unsigned short insn = *(unsigned short *) regs->pc;
446 unsigned short finsn;
447 unsigned long nextpc;
455 (nib[0] == 0x4 && nib[2] == 0x0 && nib[3] == 0xb)) /* bsr & jsr */
456 regs->pr = regs->pc + 4;
457 if (nib[0] == 0xa || nib[0] == 0xb) { /* bra & bsr */
458 nextpc = regs->pc + 4 + ((short) ((insn & 0xfff) << 4) >> 3);
459 finsn = *(unsigned short *) (regs->pc + 2);
460 } else if (nib[0] == 0x8 && nib[1] == 0xd) { /* bt/s */
462 nextpc = regs->pc + 4 + ((char) (insn & 0xff) << 1);
464 nextpc = regs->pc + 4;
465 finsn = *(unsigned short *) (regs->pc + 2);
466 } else if (nib[0] == 0x8 && nib[1] == 0xf) { /* bf/s */
468 nextpc = regs->pc + 4;
470 nextpc = regs->pc + 4 + ((char) (insn & 0xff) << 1);
471 finsn = *(unsigned short *) (regs->pc + 2);
472 } else if (nib[0] == 0x4 && nib[3] == 0xb &&
473 (nib[2] == 0x0 || nib[2] == 0x2)) { /* jmp & jsr */
474 nextpc = regs->regs[nib[1]];
475 finsn = *(unsigned short *) (regs->pc + 2);
476 } else if (nib[0] == 0x0 && nib[3] == 0x3 &&
477 (nib[2] == 0x0 || nib[2] == 0x2)) { /* braf & bsrf */
478 nextpc = regs->pc + 4 + regs->regs[nib[1]];
479 finsn = *(unsigned short *) (regs->pc + 2);
480 } else if (insn == 0x000b) { /* rts */
482 finsn = *(unsigned short *) (regs->pc + 2);
484 nextpc = regs->pc + 2;
488 #define FPSCR_FPU_ERROR (1 << 17)
490 if ((finsn & 0xf1ff) == 0xf0ad) { /* fcnvsd */
491 struct task_struct *tsk = current;
493 if ((tsk->thread.fpu.hard.fpscr & FPSCR_FPU_ERROR)) {
495 denormal_to_double (&tsk->thread.fpu.hard,
502 } else if ((finsn & 0xf00f) == 0xf002) { /* fmul */
503 struct task_struct *tsk = current;
508 n = (finsn >> 8) & 0xf;
509 m = (finsn >> 4) & 0xf;
510 hx = tsk->thread.fpu.hard.fp_regs[n];
511 hy = tsk->thread.fpu.hard.fp_regs[m];
512 fpscr = tsk->thread.fpu.hard.fpscr;
513 prec = fpscr & (1 << 19);
515 if ((fpscr & FPSCR_FPU_ERROR)
516 && (prec && ((hx & 0x7fffffff) < 0x00100000
517 || (hy & 0x7fffffff) < 0x00100000))) {
520 /* FPU error because of denormal */
521 llx = ((long long) hx << 32)
522 | tsk->thread.fpu.hard.fp_regs[n+1];
523 lly = ((long long) hy << 32)
524 | tsk->thread.fpu.hard.fp_regs[m+1];
525 if ((hx & 0x7fffffff) >= 0x00100000)
526 llx = denormal_muld(lly, llx);
528 llx = denormal_muld(llx, lly);
529 tsk->thread.fpu.hard.fp_regs[n] = llx >> 32;
530 tsk->thread.fpu.hard.fp_regs[n+1] = llx & 0xffffffff;
531 } else if ((fpscr & FPSCR_FPU_ERROR)
532 && (!prec && ((hx & 0x7fffffff) < 0x00800000
533 || (hy & 0x7fffffff) < 0x00800000))) {
534 /* FPU error because of denormal */
535 if ((hx & 0x7fffffff) >= 0x00800000)
536 hx = denormal_mulf(hy, hx);
538 hx = denormal_mulf(hx, hy);
539 tsk->thread.fpu.hard.fp_regs[n] = hx;
545 } else if ((finsn & 0xf00e) == 0xf000) { /* fadd, fsub */
546 struct task_struct *tsk = current;
551 n = (finsn >> 8) & 0xf;
552 m = (finsn >> 4) & 0xf;
553 hx = tsk->thread.fpu.hard.fp_regs[n];
554 hy = tsk->thread.fpu.hard.fp_regs[m];
555 fpscr = tsk->thread.fpu.hard.fpscr;
556 prec = fpscr & (1 << 19);
558 if ((fpscr & FPSCR_FPU_ERROR)
559 && (prec && ((hx & 0x7fffffff) < 0x00100000
560 || (hy & 0x7fffffff) < 0x00100000))) {
563 /* FPU error because of denormal */
564 llx = ((long long) hx << 32)
565 | tsk->thread.fpu.hard.fp_regs[n+1];
566 lly = ((long long) hy << 32)
567 | tsk->thread.fpu.hard.fp_regs[m+1];
568 if ((finsn & 0xf00f) == 0xf000)
569 llx = denormal_addd(llx, lly);
571 llx = denormal_addd(llx, lly ^ (1LL << 63));
572 tsk->thread.fpu.hard.fp_regs[n] = llx >> 32;
573 tsk->thread.fpu.hard.fp_regs[n+1] = llx & 0xffffffff;
574 } else if ((fpscr & FPSCR_FPU_ERROR)
575 && (!prec && ((hx & 0x7fffffff) < 0x00800000
576 || (hy & 0x7fffffff) < 0x00800000))) {
577 /* FPU error because of denormal */
578 if ((finsn & 0xf00f) == 0xf000)
579 hx = denormal_addf(hx, hy);
581 hx = denormal_addf(hx, hy ^ 0x80000000);
582 tsk->thread.fpu.hard.fp_regs[n] = hx;
593 BUILD_TRAP_HANDLER(fpu_error)
595 struct task_struct *tsk = current;
598 __unlazy_fpu(tsk, regs);
599 if (ieee_fpe_handler(regs)) {
600 tsk->thread.fpu.hard.fpscr &=
601 ~(FPSCR_CAUSE_MASK | FPSCR_FLAG_MASK);
604 task_thread_info(tsk)->status |= TS_USEDFPU;
608 force_sig(SIGFPE, tsk);
611 BUILD_TRAP_HANDLER(fpu_state_restore)
613 struct task_struct *tsk = current;
617 if (!user_mode(regs)) {
618 printk(KERN_ERR "BUG: FPU is used in kernel mode.\n");
623 /* Using the FPU again. */
626 /* First time FPU user. */
630 task_thread_info(tsk)->status |= TS_USEDFPU;