2 * arch/sh/kernel/cpu/init.c
6 * Copyright (C) 2002 - 2009 Paul Mundt
7 * Copyright (C) 2003 Richard Curnow
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
13 #include <linux/init.h>
14 #include <linux/kernel.h>
16 #include <linux/log2.h>
17 #include <asm/mmu_context.h>
18 #include <asm/processor.h>
19 #include <asm/uaccess.h>
21 #include <asm/system.h>
22 #include <asm/cacheflush.h>
23 #include <asm/cache.h>
27 #ifdef CONFIG_SUPERH32
32 * Generic wrapper for command line arguments to disable on-chip
33 * peripherals (nofpu, nodsp, and so forth).
35 #define onchip_setup(x) \
36 static int x##_disabled __initdata = 0; \
38 static int __init x##_setup(char *opts) \
43 __setup("no" __stringify(x), x##_setup);
48 #ifdef CONFIG_SPECULATIVE_EXECUTION
49 #define CPUOPM 0xff2f0000
50 #define CPUOPM_RABD (1 << 5)
52 static void __init speculative_execution_init(void)
55 ctrl_outl(ctrl_inl(CPUOPM) & ~CPUOPM_RABD, CPUOPM);
57 /* Flush the update */
58 (void)ctrl_inl(CPUOPM);
62 #define speculative_execution_init() do { } while (0)
65 #ifdef CONFIG_CPU_SH4A
66 #define EXPMASK 0xff2f0004
67 #define EXPMASK_RTEDS (1 << 0)
68 #define EXPMASK_BRDSSLP (1 << 1)
69 #define EXPMASK_MMCAW (1 << 4)
71 static void __init expmask_init(void)
73 unsigned long expmask = __raw_readl(EXPMASK);
78 * Disable support for slottable sleep instruction
79 * and non-nop instructions in the rte delay slot.
81 expmask &= ~(EXPMASK_RTEDS | EXPMASK_BRDSSLP);
84 * Enable associative writes to the memory-mapped cache array
85 * until the cache flush ops have been rewritten.
87 expmask |= EXPMASK_MMCAW;
89 __raw_writel(expmask, EXPMASK);
93 #define expmask_init() do { } while (0)
96 /* 2nd-level cache init */
97 void __uses_jump_to_uncached __attribute__ ((weak)) l2_cache_init(void)
102 * Generic first-level cache init
104 #ifdef CONFIG_SUPERH32
105 static void __uses_jump_to_uncached cache_init(void)
107 unsigned long ccr, flags;
113 * At this point we don't know whether the cache is enabled or not - a
114 * bootloader may have enabled it. There are at least 2 things that
115 * could be dirty in the cache at this point:
116 * 1. kernel command line set up by boot loader
117 * 2. spilled registers from the prolog of this function
118 * => before re-initialising the cache, we must do a purge of the whole
119 * cache out to memory for safety. As long as nothing is spilled
120 * during the loop to lines that have already been done, this is safe.
123 if (ccr & CCR_CACHE_ENABLE) {
124 unsigned long ways, waysize, addrstart;
126 waysize = current_cpu_data.dcache.sets;
130 * If the OC is already in RAM mode, we only have
131 * half of the entries to flush..
133 if (ccr & CCR_CACHE_ORA)
137 waysize <<= current_cpu_data.dcache.entry_shift;
139 #ifdef CCR_CACHE_EMODE
140 /* If EMODE is not set, we only have 1 way to flush. */
141 if (!(ccr & CCR_CACHE_EMODE))
145 ways = current_cpu_data.dcache.ways;
147 addrstart = CACHE_OC_ADDRESS_ARRAY;
151 for (addr = addrstart;
152 addr < addrstart + waysize;
153 addr += current_cpu_data.dcache.linesz)
156 addrstart += current_cpu_data.dcache.way_incr;
161 * Default CCR values .. enable the caches
162 * and invalidate them immediately..
164 flags = CCR_CACHE_ENABLE | CCR_CACHE_INVALIDATE;
166 #ifdef CCR_CACHE_EMODE
167 /* Force EMODE if possible */
168 if (current_cpu_data.dcache.ways > 1)
169 flags |= CCR_CACHE_EMODE;
171 flags &= ~CCR_CACHE_EMODE;
174 #if defined(CONFIG_CACHE_WRITETHROUGH)
176 flags |= CCR_CACHE_WT;
177 #elif defined(CONFIG_CACHE_WRITEBACK)
179 flags |= CCR_CACHE_CB;
182 flags &= ~CCR_CACHE_ENABLE;
187 ctrl_outl(flags, CCR);
191 #define cache_init() do { } while (0)
194 #define CSHAPE(totalsize, linesize, assoc) \
195 ((totalsize & ~0xff) | (linesize << 4) | assoc)
197 #define CACHE_DESC_SHAPE(desc) \
198 CSHAPE((desc).way_size * (desc).ways, ilog2((desc).linesz), (desc).ways)
200 static void detect_cache_shape(void)
202 l1d_cache_shape = CACHE_DESC_SHAPE(current_cpu_data.dcache);
204 if (current_cpu_data.dcache.flags & SH_CACHE_COMBINED)
205 l1i_cache_shape = l1d_cache_shape;
207 l1i_cache_shape = CACHE_DESC_SHAPE(current_cpu_data.icache);
209 if (current_cpu_data.flags & CPU_HAS_L2_CACHE)
210 l2_cache_shape = CACHE_DESC_SHAPE(current_cpu_data.scache);
212 l2_cache_shape = -1; /* No S-cache */
216 static void __init release_dsp(void)
220 /* Clear SR.DSP bit */
221 __asm__ __volatile__ (
230 static void __init dsp_init(void)
235 * Set the SR.DSP bit, wait for one instruction, and then read
238 __asm__ __volatile__ (
248 /* If the DSP bit is still set, this CPU has a DSP */
250 current_cpu_data.flags |= CPU_HAS_DSP;
252 /* Now that we've determined the DSP status, clear the DSP bit. */
255 #endif /* CONFIG_SH_DSP */
260 * This is our initial entry point for each CPU, and is invoked on the boot
261 * CPU prior to calling start_kernel(). For SMP, a combination of this and
262 * start_secondary() will bring up each processor to a ready state prior
263 * to hand forking the idle loop.
265 * We do all of the basic processor init here, including setting up the
266 * caches, FPU, DSP, kicking the UBC, etc. By the time start_kernel() is
267 * hit (and subsequently platform_setup()) things like determining the
268 * CPU subtype and initial configuration will all be done.
270 * Each processor family is still responsible for doing its own probing
271 * and cache configuration in detect_cpu_and_cache_system().
274 asmlinkage void __init sh_cpu_init(void)
276 current_thread_info()->cpu = hard_smp_processor_id();
278 /* First, probe the CPU */
279 detect_cpu_and_cache_system();
281 if (current_cpu_data.type == CPU_SH_NONE)
282 panic("Unknown CPU");
284 /* First setup the rest of the I-cache info */
285 current_cpu_data.icache.entry_mask = current_cpu_data.icache.way_incr -
286 current_cpu_data.icache.linesz;
288 current_cpu_data.icache.way_size = current_cpu_data.icache.sets *
289 current_cpu_data.icache.linesz;
291 /* And the D-cache too */
292 current_cpu_data.dcache.entry_mask = current_cpu_data.dcache.way_incr -
293 current_cpu_data.dcache.linesz;
295 current_cpu_data.dcache.way_size = current_cpu_data.dcache.sets *
296 current_cpu_data.dcache.linesz;
301 if (raw_smp_processor_id() == 0) {
302 shm_align_mask = max_t(unsigned long,
303 current_cpu_data.dcache.way_size - 1,
306 /* Boot CPU sets the cache shape */
307 detect_cache_shape();
310 /* Disable the FPU */
312 printk("FPU Disabled\n");
313 current_cpu_data.flags &= ~CPU_HAS_FPU;
316 /* FPU initialization */
318 if ((current_cpu_data.flags & CPU_HAS_FPU)) {
319 current_thread_info()->status &= ~TS_USEDFPU;
324 * Initialize the per-CPU ASID cache very early, since the
325 * TLB flushing routines depend on this being setup.
327 current_cpu_data.asid_cache = NO_CONTEXT;
333 /* Disable the DSP */
335 printk("DSP Disabled\n");
336 current_cpu_data.flags &= ~CPU_HAS_DSP;
341 speculative_execution_init();