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   1 #ifndef __ASM_SH_CPU_SH4_DMA_SH7780_H
   2 #define __ASM_SH_CPU_SH4_DMA_SH7780_H
   3
   4 #if defined(CONFIG_CPU_SUBTYPE_SH7343) || \
   5         defined(CONFIG_CPU_SUBTYPE_SH7722) || \
   6         defined(CONFIG_CPU_SUBTYPE_SH7730)
   7 #define DMTE0_IRQ       48
   8 #define DMTE4_IRQ       76
   9 #define DMAE0_IRQ       78      /* DMA Error IRQ*/
  10 #define SH_DMAC_BASE0   0xFE008020
  11 #define SH_DMARS_BASE   0xFE009000
  12 #elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
  13         defined(CONFIG_CPU_SUBTYPE_SH7764)
  14 #define DMTE0_IRQ       34
  15 #define DMTE4_IRQ       44
  16 #define DMAE0_IRQ       38
  17 #define SH_DMAC_BASE0   0xFF608020
  18 #define SH_DMARS_BASE   0xFF609000
  19 #elif defined(CONFIG_CPU_SUBTYPE_SH7723) || \
  20       defined(CONFIG_CPU_SUBTYPE_SH7724)
  21 #define DMTE0_IRQ       48      /* DMAC0A*/
  22 #define DMTE4_IRQ       40      /* DMAC0B */
  23 #define DMTE6_IRQ       42
  24 #define DMTE8_IRQ       76      /* DMAC1A */
  25 #define DMTE9_IRQ       77
  26 #define DMTE10_IRQ      72      /* DMAC1B */
  27 #define DMTE11_IRQ      73
  28 #define DMAE0_IRQ       78      /* DMA Error IRQ*/
  29 #define DMAE1_IRQ       74      /* DMA Error IRQ*/
  30 #define SH_DMAC_BASE0   0xFE008020
  31 #define SH_DMAC_BASE1   0xFDC08020
  32 #define SH_DMARS_BASE   0xFDC09000
  33 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
  34 #define DMTE0_IRQ       34
  35 #define DMTE4_IRQ       44
  36 #define DMTE6_IRQ       46
  37 #define DMTE8_IRQ       92
  38 #define DMTE9_IRQ       93
  39 #define DMTE10_IRQ      94
  40 #define DMTE11_IRQ      95
  41 #define DMAE0_IRQ       38      /* DMA Error IRQ */
  42 #define SH_DMAC_BASE0   0xFC808020
  43 #define SH_DMAC_BASE1   0xFC818020
  44 #define SH_DMARS_BASE   0xFC809000
  45 #else /* SH7785 */
  46 #define DMTE0_IRQ       33
  47 #define DMTE4_IRQ       37
  48 #define DMTE6_IRQ       52
  49 #define DMTE8_IRQ       54
  50 #define DMTE9_IRQ       55
  51 #define DMTE10_IRQ      56
  52 #define DMTE11_IRQ      57
  53 #define DMAE0_IRQ       39      /* DMA Error IRQ0 */
  54 #define DMAE1_IRQ       58      /* DMA Error IRQ1 */
  55 #define SH_DMAC_BASE0   0xFC808020
  56 #define SH_DMAC_BASE1   0xFCC08020
  57 #define SH_DMARS_BASE   0xFC809000
  58 #endif
  59
  60 #define REQ_HE  0x000000C0
  61 #define REQ_H   0x00000080
  62 #define REQ_LE  0x00000040
  63 #define TM_BURST 0x0000020
  64 #define TS_8    0x00000000
  65 #define TS_16   0x00000008
  66 #define TS_32   0x00000010
  67 #define TS_16BLK        0x00000018
  68 #define TS_32BLK        0x00100000
  69
  70 /*
  71  * The SuperH DMAC supports a number of transmit sizes, we list them here,
  72  * with their respective values as they appear in the CHCR registers.
  73  *
  74  * Defaults to a 64-bit transfer size.
  75  */
  76 enum {
  77         XMIT_SZ_8BIT,
  78         XMIT_SZ_16BIT,
  79         XMIT_SZ_32BIT,
  80         XMIT_SZ_128BIT,
  81         XMIT_SZ_256BIT,
  82 };
  83
  84 /*
  85  * The DMA count is defined as the number of bytes to transfer.
  86  */
  87 static unsigned int ts_shift[] __maybe_unused = {
  88         [XMIT_SZ_8BIT]          = 0,
  89         [XMIT_SZ_16BIT]         = 1,
  90         [XMIT_SZ_32BIT]         = 2,
  91         [XMIT_SZ_128BIT]        = 4,
  92         [XMIT_SZ_256BIT]        = 5,
  93 };
  94
  95 #endif /* __ASM_SH_CPU_SH4_DMA_SH7780_H */