2 * Copyright (C) 2009 Renesas Solutions Corp.
4 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
11 #include <linux/init.h>
12 #include <linux/device.h>
13 #include <linux/platform_device.h>
14 #include <linux/mtd/physmap.h>
15 #include <linux/gpio.h>
16 #include <linux/interrupt.h>
18 #include <linux/delay.h>
19 #include <linux/usb/r8a66597.h>
20 #include <video/sh_mobile_lcdc.h>
21 #include <media/sh_mobile_ceu.h>
22 #include <asm/heartbeat.h>
23 #include <asm/sh_eth.h>
24 #include <cpu/sh7724.h>
27 * Address Interface BusWidth
28 *-----------------------------------------
29 * 0x0000_0000 uboot 16bit
30 * 0x0004_0000 Linux romImage 16bit
31 * 0x0014_0000 MTD for Linux 16bit
32 * 0x0400_0000 Internal I/O 16/32bit
33 * 0x0800_0000 DRAM 32bit
34 * 0x1800_0000 MFI 16bit
38 static unsigned char led_pos[] = { 0, 1, 2, 3 };
39 static struct heartbeat_data heartbeat_data = {
45 static struct resource heartbeat_resources[] = {
47 .start = 0xA405012C, /* PTG */
48 .end = 0xA405012E - 1,
49 .flags = IORESOURCE_MEM,
53 static struct platform_device heartbeat_device = {
57 .platform_data = &heartbeat_data,
59 .num_resources = ARRAY_SIZE(heartbeat_resources),
60 .resource = heartbeat_resources,
64 static struct mtd_partition nor_flash_partitions[] = {
66 .name = "boot loader",
68 .size = (5 * 1024 * 1024),
69 .mask_flags = MTD_CAP_ROM,
72 .offset = MTDPART_OFS_APPEND,
73 .size = MTDPART_SIZ_FULL,
77 static struct physmap_flash_data nor_flash_data = {
79 .parts = nor_flash_partitions,
80 .nr_parts = ARRAY_SIZE(nor_flash_partitions),
83 static struct resource nor_flash_resources[] = {
88 .flags = IORESOURCE_MEM,
92 static struct platform_device nor_flash_device = {
93 .name = "physmap-flash",
94 .resource = nor_flash_resources,
95 .num_resources = ARRAY_SIZE(nor_flash_resources),
97 .platform_data = &nor_flash_data,
102 #define SH_ETH_ADDR (0xA4600000)
103 #define SH_ETH_MAHR (SH_ETH_ADDR + 0x1C0)
104 #define SH_ETH_MALR (SH_ETH_ADDR + 0x1C8)
105 static struct resource sh_eth_resources[] = {
107 .start = SH_ETH_ADDR,
108 .end = SH_ETH_ADDR + 0x1FC,
109 .flags = IORESOURCE_MEM,
113 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
117 struct sh_eth_plat_data sh_eth_plat = {
118 .phy = 0x1f, /* SMSC LAN8700 */
119 .edmac_endian = EDMAC_LITTLE_ENDIAN,
122 static struct platform_device sh_eth_device = {
126 .platform_data = &sh_eth_plat,
128 .num_resources = ARRAY_SIZE(sh_eth_resources),
129 .resource = sh_eth_resources,
133 void usb0_port_power(int port, int power)
135 gpio_set_value(GPIO_PTB4, power);
138 static struct r8a66597_platdata usb0_host_data = {
140 .port_power = usb0_port_power,
143 static struct resource usb0_host_resources[] = {
146 .end = 0xa4d80124 - 1,
147 .flags = IORESOURCE_MEM,
152 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
156 static struct platform_device usb0_host_device = {
157 .name = "r8a66597_hcd",
160 .dma_mask = NULL, /* not use dma */
161 .coherent_dma_mask = 0xffffffff,
162 .platform_data = &usb0_host_data,
164 .num_resources = ARRAY_SIZE(usb0_host_resources),
165 .resource = usb0_host_resources,
171 * CN5 can use both host/function,
172 * and we can determine it by checking PTB[3]
174 * This time only USB1 host is supported.
176 void usb1_port_power(int port, int power)
178 if (!gpio_get_value(GPIO_PTB3)) {
179 printk(KERN_ERR "USB1 function is not supported\n");
183 gpio_set_value(GPIO_PTB5, power);
186 static struct r8a66597_platdata usb1_host_data = {
188 .port_power = usb1_port_power,
191 static struct resource usb1_host_resources[] = {
194 .end = 0xa4d90124 - 1,
195 .flags = IORESOURCE_MEM,
200 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
204 static struct platform_device usb1_host_device = {
205 .name = "r8a66597_hcd",
208 .dma_mask = NULL, /* not use dma */
209 .coherent_dma_mask = 0xffffffff,
210 .platform_data = &usb1_host_data,
212 .num_resources = ARRAY_SIZE(usb1_host_resources),
213 .resource = usb1_host_resources,
217 static struct sh_mobile_lcdc_info lcdc_info = {
219 .interface_type = RGB18,
220 .chan = LCDC_CHAN_MAINLCD,
223 .sync = 0, /* hsync and vsync are active low */
225 .lcd_size_cfg = { /* 7.0 inch */
234 static struct resource lcdc_resources[] = {
239 .flags = IORESOURCE_MEM,
243 .flags = IORESOURCE_IRQ,
247 static struct platform_device lcdc_device = {
248 .name = "sh_mobile_lcdc_fb",
249 .num_resources = ARRAY_SIZE(lcdc_resources),
250 .resource = lcdc_resources,
252 .platform_data = &lcdc_info,
255 .hwblk_id = HWBLK_LCDC,
260 static struct sh_mobile_ceu_info sh_mobile_ceu0_info = {
261 .flags = SH_CEU_FLAG_USE_8BIT_BUS,
264 static struct resource ceu0_resources[] = {
269 .flags = IORESOURCE_MEM,
273 .flags = IORESOURCE_IRQ,
276 /* place holder for contiguous memory */
280 static struct platform_device ceu0_device = {
281 .name = "sh_mobile_ceu",
282 .id = 0, /* "ceu0" clock */
283 .num_resources = ARRAY_SIZE(ceu0_resources),
284 .resource = ceu0_resources,
286 .platform_data = &sh_mobile_ceu0_info,
289 .hwblk_id = HWBLK_CEU0,
294 static struct sh_mobile_ceu_info sh_mobile_ceu1_info = {
295 .flags = SH_CEU_FLAG_USE_8BIT_BUS,
298 static struct resource ceu1_resources[] = {
303 .flags = IORESOURCE_MEM,
307 .flags = IORESOURCE_IRQ,
310 /* place holder for contiguous memory */
314 static struct platform_device ceu1_device = {
315 .name = "sh_mobile_ceu",
316 .id = 1, /* "ceu1" clock */
317 .num_resources = ARRAY_SIZE(ceu1_resources),
318 .resource = ceu1_resources,
320 .platform_data = &sh_mobile_ceu1_info,
323 .hwblk_id = HWBLK_CEU1,
328 static struct i2c_board_info i2c1_devices[] = {
330 I2C_BOARD_INFO("r2025sd", 0x32),
334 static struct platform_device *ecovec_devices[] __initdata = {
339 &usb1_host_device, /* USB1 host support */
345 #define PORT_HIZA 0xA4050158
346 #define IODRIVEA 0xA405018A
347 static int __init devices_setup(void)
350 gpio_request(GPIO_FN_SCIF0_TXD, NULL);
351 gpio_request(GPIO_FN_SCIF0_RXD, NULL);
353 /* enable debug LED */
354 gpio_request(GPIO_PTG0, NULL);
355 gpio_request(GPIO_PTG1, NULL);
356 gpio_request(GPIO_PTG2, NULL);
357 gpio_request(GPIO_PTG3, NULL);
358 gpio_direction_output(GPIO_PTG0, 0);
359 gpio_direction_output(GPIO_PTG1, 0);
360 gpio_direction_output(GPIO_PTG2, 0);
361 gpio_direction_output(GPIO_PTG3, 0);
364 gpio_request(GPIO_PTA1, NULL);
365 gpio_direction_output(GPIO_PTA1, 1);
368 gpio_request(GPIO_FN_RMII_RXD0, NULL);
369 gpio_request(GPIO_FN_RMII_RXD1, NULL);
370 gpio_request(GPIO_FN_RMII_TXD0, NULL);
371 gpio_request(GPIO_FN_RMII_TXD1, NULL);
372 gpio_request(GPIO_FN_RMII_REF_CLK, NULL);
373 gpio_request(GPIO_FN_RMII_TX_EN, NULL);
374 gpio_request(GPIO_FN_RMII_RX_ER, NULL);
375 gpio_request(GPIO_FN_RMII_CRS_DV, NULL);
376 gpio_request(GPIO_FN_MDIO, NULL);
377 gpio_request(GPIO_FN_MDC, NULL);
378 gpio_request(GPIO_FN_LNKSTA, NULL);
381 gpio_request(GPIO_PTB3, NULL);
382 gpio_request(GPIO_PTB4, NULL);
383 gpio_request(GPIO_PTB5, NULL);
384 gpio_direction_input(GPIO_PTB3);
385 gpio_direction_output(GPIO_PTB4, 0);
386 gpio_direction_output(GPIO_PTB5, 0);
387 ctrl_outw(0x0600, 0xa40501d4);
388 ctrl_outw(0x0600, 0xa4050192);
391 gpio_request(GPIO_FN_LCDD23, NULL);
392 gpio_request(GPIO_FN_LCDD22, NULL);
393 gpio_request(GPIO_FN_LCDD21, NULL);
394 gpio_request(GPIO_FN_LCDD20, NULL);
395 gpio_request(GPIO_FN_LCDD19, NULL);
396 gpio_request(GPIO_FN_LCDD18, NULL);
397 gpio_request(GPIO_FN_LCDD17, NULL);
398 gpio_request(GPIO_FN_LCDD16, NULL);
399 gpio_request(GPIO_FN_LCDD15, NULL);
400 gpio_request(GPIO_FN_LCDD14, NULL);
401 gpio_request(GPIO_FN_LCDD13, NULL);
402 gpio_request(GPIO_FN_LCDD12, NULL);
403 gpio_request(GPIO_FN_LCDD11, NULL);
404 gpio_request(GPIO_FN_LCDD10, NULL);
405 gpio_request(GPIO_FN_LCDD9, NULL);
406 gpio_request(GPIO_FN_LCDD8, NULL);
407 gpio_request(GPIO_FN_LCDD7, NULL);
408 gpio_request(GPIO_FN_LCDD6, NULL);
409 gpio_request(GPIO_FN_LCDD5, NULL);
410 gpio_request(GPIO_FN_LCDD4, NULL);
411 gpio_request(GPIO_FN_LCDD3, NULL);
412 gpio_request(GPIO_FN_LCDD2, NULL);
413 gpio_request(GPIO_FN_LCDD1, NULL);
414 gpio_request(GPIO_FN_LCDD0, NULL);
415 gpio_request(GPIO_FN_LCDDISP, NULL);
416 gpio_request(GPIO_FN_LCDHSYN, NULL);
417 gpio_request(GPIO_FN_LCDDCK, NULL);
418 gpio_request(GPIO_FN_LCDVSYN, NULL);
419 gpio_request(GPIO_FN_LCDDON, NULL);
420 gpio_request(GPIO_FN_LCDLCLK, NULL);
421 ctrl_outw((ctrl_inw(PORT_HIZA) & ~0x0001), PORT_HIZA);
423 gpio_request(GPIO_PTE6, NULL);
424 gpio_request(GPIO_PTU1, NULL);
425 gpio_request(GPIO_PTR1, NULL);
426 gpio_request(GPIO_PTA2, NULL);
427 gpio_direction_input(GPIO_PTE6);
428 gpio_direction_output(GPIO_PTU1, 0);
429 gpio_direction_output(GPIO_PTR1, 0);
430 gpio_direction_output(GPIO_PTA2, 0);
432 /* I/O buffer drive ability is low */
433 ctrl_outw((ctrl_inw(IODRIVEA) & ~0x00c0) | 0x0040 , IODRIVEA);
435 if (gpio_get_value(GPIO_PTE6)) {
437 lcdc_info.clock_source = LCDC_CLK_EXTERNAL;
438 lcdc_info.ch[0].clock_divider = 1,
439 lcdc_info.ch[0].lcd_cfg.name = "DVI";
440 lcdc_info.ch[0].lcd_cfg.xres = 1280;
441 lcdc_info.ch[0].lcd_cfg.yres = 720;
442 lcdc_info.ch[0].lcd_cfg.left_margin = 220;
443 lcdc_info.ch[0].lcd_cfg.right_margin = 110;
444 lcdc_info.ch[0].lcd_cfg.hsync_len = 40;
445 lcdc_info.ch[0].lcd_cfg.upper_margin = 20;
446 lcdc_info.ch[0].lcd_cfg.lower_margin = 5;
447 lcdc_info.ch[0].lcd_cfg.vsync_len = 5;
449 gpio_set_value(GPIO_PTA2, 1);
450 gpio_set_value(GPIO_PTU1, 1);
454 lcdc_info.clock_source = LCDC_CLK_PERIPHERAL;
455 lcdc_info.ch[0].clock_divider = 2,
456 lcdc_info.ch[0].lcd_cfg.name = "Panel";
457 lcdc_info.ch[0].lcd_cfg.xres = 800;
458 lcdc_info.ch[0].lcd_cfg.yres = 480;
459 lcdc_info.ch[0].lcd_cfg.left_margin = 220;
460 lcdc_info.ch[0].lcd_cfg.right_margin = 110;
461 lcdc_info.ch[0].lcd_cfg.hsync_len = 70;
462 lcdc_info.ch[0].lcd_cfg.upper_margin = 20;
463 lcdc_info.ch[0].lcd_cfg.lower_margin = 5;
464 lcdc_info.ch[0].lcd_cfg.vsync_len = 5;
466 gpio_set_value(GPIO_PTR1, 1);
470 * LCDDON control is needed for Panel,
471 * but current sh_mobile_lcdc driver doesn't control it.
472 * It is temporary correspondence
474 gpio_request(GPIO_PTF4, NULL);
475 gpio_direction_output(GPIO_PTF4, 1);
479 gpio_request(GPIO_FN_VIO0_D15, NULL);
480 gpio_request(GPIO_FN_VIO0_D14, NULL);
481 gpio_request(GPIO_FN_VIO0_D13, NULL);
482 gpio_request(GPIO_FN_VIO0_D12, NULL);
483 gpio_request(GPIO_FN_VIO0_D11, NULL);
484 gpio_request(GPIO_FN_VIO0_D10, NULL);
485 gpio_request(GPIO_FN_VIO0_D9, NULL);
486 gpio_request(GPIO_FN_VIO0_D8, NULL);
487 gpio_request(GPIO_FN_VIO0_D7, NULL);
488 gpio_request(GPIO_FN_VIO0_D6, NULL);
489 gpio_request(GPIO_FN_VIO0_D5, NULL);
490 gpio_request(GPIO_FN_VIO0_D4, NULL);
491 gpio_request(GPIO_FN_VIO0_D3, NULL);
492 gpio_request(GPIO_FN_VIO0_D2, NULL);
493 gpio_request(GPIO_FN_VIO0_D1, NULL);
494 gpio_request(GPIO_FN_VIO0_D0, NULL);
495 gpio_request(GPIO_FN_VIO0_VD, NULL);
496 gpio_request(GPIO_FN_VIO0_CLK, NULL);
497 gpio_request(GPIO_FN_VIO0_FLD, NULL);
498 gpio_request(GPIO_FN_VIO0_HD, NULL);
499 platform_resource_setup_memory(&ceu0_device, "ceu0", 4 << 20);
502 gpio_request(GPIO_FN_VIO1_D7, NULL);
503 gpio_request(GPIO_FN_VIO1_D6, NULL);
504 gpio_request(GPIO_FN_VIO1_D5, NULL);
505 gpio_request(GPIO_FN_VIO1_D4, NULL);
506 gpio_request(GPIO_FN_VIO1_D3, NULL);
507 gpio_request(GPIO_FN_VIO1_D2, NULL);
508 gpio_request(GPIO_FN_VIO1_D1, NULL);
509 gpio_request(GPIO_FN_VIO1_D0, NULL);
510 gpio_request(GPIO_FN_VIO1_FLD, NULL);
511 gpio_request(GPIO_FN_VIO1_HD, NULL);
512 gpio_request(GPIO_FN_VIO1_VD, NULL);
513 gpio_request(GPIO_FN_VIO1_CLK, NULL);
514 platform_resource_setup_memory(&ceu1_device, "ceu1", 4 << 20);
516 /* enable I2C device */
517 i2c_register_board_info(1, i2c1_devices,
518 ARRAY_SIZE(i2c1_devices));
520 return platform_add_devices(ecovec_devices,
521 ARRAY_SIZE(ecovec_devices));
523 arch_initcall(devices_setup);
525 static struct sh_machine_vector mv_ecovec __initmv = {
526 .mv_name = "R0P7724 (EcoVec)",