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   1 /*
   2  *  arch/powerpc/kernel/mpic.c
   3  *
   4  *  Driver for interrupt controllers following the OpenPIC standard, the
   5  *  common implementation beeing IBM's MPIC. This driver also can deal
   6  *  with various broken implementations of this HW.
   7  *
   8  *  Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
   9  *
  10  *  This file is subject to the terms and conditions of the GNU General Public
  11  *  License.  See the file COPYING in the main directory of this archive
  12  *  for more details.
  13  */
  14
  15 #undef DEBUG
  16 #undef DEBUG_IPI
  17 #undef DEBUG_IRQ
  18 #undef DEBUG_LOW
  19
  20 #include <linux/types.h>
  21 #include <linux/kernel.h>
  22 #include <linux/init.h>
  23 #include <linux/irq.h>
  24 #include <linux/smp.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/bootmem.h>
  27 #include <linux/spinlock.h>
  28 #include <linux/pci.h>
  29
  30 #include <asm/ptrace.h>
  31 #include <asm/signal.h>
  32 #include <asm/io.h>
  33 #include <asm/pgtable.h>
  34 #include <asm/irq.h>
  35 #include <asm/machdep.h>
  36 #include <asm/mpic.h>
  37 #include <asm/smp.h>
  38
  39 #include "mpic.h"
  40
  41 #ifdef DEBUG
  42 #define DBG(fmt...) printk(fmt)
  43 #else
  44 #define DBG(fmt...)
  45 #endif
  46
  47 static struct mpic *mpics;
  48 static struct mpic *mpic_primary;
  49 static DEFINE_SPINLOCK(mpic_lock);
  50
  51 #ifdef CONFIG_PPC32     /* XXX for now */
  52 #ifdef CONFIG_IRQ_ALL_CPUS
  53 #define distribute_irqs (1)
  54 #else
  55 #define distribute_irqs (0)
  56 #endif
  57 #endif
  58
  59 #ifdef CONFIG_MPIC_WEIRD
  60 static u32 mpic_infos[][MPIC_IDX_END] = {
  61         [0] = { /* Original OpenPIC compatible MPIC */
  62                 MPIC_GREG_BASE,
  63                 MPIC_GREG_FEATURE_0,
  64                 MPIC_GREG_GLOBAL_CONF_0,
  65                 MPIC_GREG_VENDOR_ID,
  66                 MPIC_GREG_IPI_VECTOR_PRI_0,
  67                 MPIC_GREG_IPI_STRIDE,
  68                 MPIC_GREG_SPURIOUS,
  69                 MPIC_GREG_TIMER_FREQ,
  70
  71                 MPIC_TIMER_BASE,
  72                 MPIC_TIMER_STRIDE,
  73                 MPIC_TIMER_CURRENT_CNT,
  74                 MPIC_TIMER_BASE_CNT,
  75                 MPIC_TIMER_VECTOR_PRI,
  76                 MPIC_TIMER_DESTINATION,
  77
  78                 MPIC_CPU_BASE,
  79                 MPIC_CPU_STRIDE,
  80                 MPIC_CPU_IPI_DISPATCH_0,
  81                 MPIC_CPU_IPI_DISPATCH_STRIDE,
  82                 MPIC_CPU_CURRENT_TASK_PRI,
  83                 MPIC_CPU_WHOAMI,
  84                 MPIC_CPU_INTACK,
  85                 MPIC_CPU_EOI,
  86
  87                 MPIC_IRQ_BASE,
  88                 MPIC_IRQ_STRIDE,
  89                 MPIC_IRQ_VECTOR_PRI,
  90                 MPIC_VECPRI_VECTOR_MASK,
  91                 MPIC_VECPRI_POLARITY_POSITIVE,
  92                 MPIC_VECPRI_POLARITY_NEGATIVE,
  93                 MPIC_VECPRI_SENSE_LEVEL,
  94                 MPIC_VECPRI_SENSE_EDGE,
  95                 MPIC_VECPRI_POLARITY_MASK,
  96                 MPIC_VECPRI_SENSE_MASK,
  97                 MPIC_IRQ_DESTINATION
  98         },
  99         [1] = { /* Tsi108/109 PIC */
 100                 TSI108_GREG_BASE,
 101                 TSI108_GREG_FEATURE_0,
 102                 TSI108_GREG_GLOBAL_CONF_0,
 103                 TSI108_GREG_VENDOR_ID,
 104                 TSI108_GREG_IPI_VECTOR_PRI_0,
 105                 TSI108_GREG_IPI_STRIDE,
 106                 TSI108_GREG_SPURIOUS,
 107                 TSI108_GREG_TIMER_FREQ,
 108
 109                 TSI108_TIMER_BASE,
 110                 TSI108_TIMER_STRIDE,
 111                 TSI108_TIMER_CURRENT_CNT,
 112                 TSI108_TIMER_BASE_CNT,
 113                 TSI108_TIMER_VECTOR_PRI,
 114                 TSI108_TIMER_DESTINATION,
 115
 116                 TSI108_CPU_BASE,
 117                 TSI108_CPU_STRIDE,
 118                 TSI108_CPU_IPI_DISPATCH_0,
 119                 TSI108_CPU_IPI_DISPATCH_STRIDE,
 120                 TSI108_CPU_CURRENT_TASK_PRI,
 121                 TSI108_CPU_WHOAMI,
 122                 TSI108_CPU_INTACK,
 123                 TSI108_CPU_EOI,
 124
 125                 TSI108_IRQ_BASE,
 126                 TSI108_IRQ_STRIDE,
 127                 TSI108_IRQ_VECTOR_PRI,
 128                 TSI108_VECPRI_VECTOR_MASK,
 129                 TSI108_VECPRI_POLARITY_POSITIVE,
 130                 TSI108_VECPRI_POLARITY_NEGATIVE,
 131                 TSI108_VECPRI_SENSE_LEVEL,
 132                 TSI108_VECPRI_SENSE_EDGE,
 133                 TSI108_VECPRI_POLARITY_MASK,
 134                 TSI108_VECPRI_SENSE_MASK,
 135                 TSI108_IRQ_DESTINATION
 136         },
 137 };
 138
 139 #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
 140
 141 #else /* CONFIG_MPIC_WEIRD */
 142
 143 #define MPIC_INFO(name) MPIC_##name
 144
 145 #endif /* CONFIG_MPIC_WEIRD */
 146
 147 /*
 148  * Register accessor functions
 149  */
 150
 151
 152 static inline u32 _mpic_read(enum mpic_reg_type type,
 153                              struct mpic_reg_bank *rb,
 154                              unsigned int reg)
 155 {
 156         switch(type) {
 157 #ifdef CONFIG_PPC_DCR
 158         case mpic_access_dcr:
 159                 return dcr_read(rb->dhost, reg);
 160 #endif
 161         case mpic_access_mmio_be:
 162                 return in_be32(rb->base + (reg >> 2));
 163         case mpic_access_mmio_le:
 164         default:
 165                 return in_le32(rb->base + (reg >> 2));
 166         }
 167 }
 168
 169 static inline void _mpic_write(enum mpic_reg_type type,
 170                                struct mpic_reg_bank *rb,
 171                                unsigned int reg, u32 value)
 172 {
 173         switch(type) {
 174 #ifdef CONFIG_PPC_DCR
 175         case mpic_access_dcr:
 176                 return dcr_write(rb->dhost, reg, value);
 177 #endif
 178         case mpic_access_mmio_be:
 179                 return out_be32(rb->base + (reg >> 2), value);
 180         case mpic_access_mmio_le:
 181         default:
 182                 return out_le32(rb->base + (reg >> 2), value);
 183         }
 184 }
 185
 186 static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
 187 {
 188         enum mpic_reg_type type = mpic->reg_type;
 189         unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
 190                               (ipi * MPIC_INFO(GREG_IPI_STRIDE));
 191
 192         if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le)
 193                 type = mpic_access_mmio_be;
 194         return _mpic_read(type, &mpic->gregs, offset);
 195 }
 196
 197 static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
 198 {
 199         unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
 200                               (ipi * MPIC_INFO(GREG_IPI_STRIDE));
 201
 202         _mpic_write(mpic->reg_type, &mpic->gregs, offset, value);
 203 }
 204
 205 static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
 206 {
 207         unsigned int cpu = 0;
 208
 209         if (mpic->flags & MPIC_PRIMARY)
 210                 cpu = hard_smp_processor_id();
 211         return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg);
 212 }
 213
 214 static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
 215 {
 216         unsigned int cpu = 0;
 217
 218         if (mpic->flags & MPIC_PRIMARY)
 219                 cpu = hard_smp_processor_id();
 220
 221         _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value);
 222 }
 223
 224 static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg)
 225 {
 226         unsigned int    isu = src_no >> mpic->isu_shift;
 227         unsigned int    idx = src_no & mpic->isu_mask;
 228
 229 #ifdef CONFIG_MPIC_BROKEN_REGREAD
 230         if (reg == 0)
 231                 return mpic->isu_reg0_shadow[idx];
 232         else
 233 #endif
 234                 return _mpic_read(mpic->reg_type, &mpic->isus[isu],
 235                                   reg + (idx * MPIC_INFO(IRQ_STRIDE)));
 236 }
 237
 238 static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
 239                                    unsigned int reg, u32 value)
 240 {
 241         unsigned int    isu = src_no >> mpic->isu_shift;
 242         unsigned int    idx = src_no & mpic->isu_mask;
 243
 244         _mpic_write(mpic->reg_type, &mpic->isus[isu],
 245                     reg + (idx * MPIC_INFO(IRQ_STRIDE)), value);
 246
 247 #ifdef CONFIG_MPIC_BROKEN_REGREAD
 248         if (reg == 0)
 249                 mpic->isu_reg0_shadow[idx] = value;
 250 #endif
 251 }
 252
 253 #define mpic_read(b,r)          _mpic_read(mpic->reg_type,&(b),(r))
 254 #define mpic_write(b,r,v)       _mpic_write(mpic->reg_type,&(b),(r),(v))
 255 #define mpic_ipi_read(i)        _mpic_ipi_read(mpic,(i))
 256 #define mpic_ipi_write(i,v)     _mpic_ipi_write(mpic,(i),(v))
 257 #define mpic_cpu_read(i)        _mpic_cpu_read(mpic,(i))
 258 #define mpic_cpu_write(i,v)     _mpic_cpu_write(mpic,(i),(v))
 259 #define mpic_irq_read(s,r)      _mpic_irq_read(mpic,(s),(r))
 260 #define mpic_irq_write(s,r,v)   _mpic_irq_write(mpic,(s),(r),(v))
 261
 262
 263 /*
 264  * Low level utility functions
 265  */
 266
 267
 268 static void _mpic_map_mmio(struct mpic *mpic, unsigned long phys_addr,
 269                            struct mpic_reg_bank *rb, unsigned int offset,
 270                            unsigned int size)
 271 {
 272         rb->base = ioremap(phys_addr + offset, size);
 273         BUG_ON(rb->base == NULL);
 274 }
 275
 276 #ifdef CONFIG_PPC_DCR
 277 static void _mpic_map_dcr(struct mpic *mpic, struct mpic_reg_bank *rb,
 278                           unsigned int offset, unsigned int size)
 279 {
 280         const u32 *dbasep;
 281
 282         dbasep = of_get_property(mpic->irqhost->of_node, "dcr-reg", NULL);
 283
 284         rb->dhost = dcr_map(mpic->irqhost->of_node, *dbasep + offset, size);
 285         BUG_ON(!DCR_MAP_OK(rb->dhost));
 286 }
 287
 288 static inline void mpic_map(struct mpic *mpic, unsigned long phys_addr,
 289                             struct mpic_reg_bank *rb, unsigned int offset,
 290                             unsigned int size)
 291 {
 292         if (mpic->flags & MPIC_USES_DCR)
 293                 _mpic_map_dcr(mpic, rb, offset, size);
 294         else
 295                 _mpic_map_mmio(mpic, phys_addr, rb, offset, size);
 296 }
 297 #else /* CONFIG_PPC_DCR */
 298 #define mpic_map(m,p,b,o,s)     _mpic_map_mmio(m,p,b,o,s)
 299 #endif /* !CONFIG_PPC_DCR */
 300
 301
 302
 303 /* Check if we have one of those nice broken MPICs with a flipped endian on
 304  * reads from IPI registers
 305  */
 306 static void __init mpic_test_broken_ipi(struct mpic *mpic)
 307 {
 308         u32 r;
 309
 310         mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK);
 311         r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0));
 312
 313         if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {
 314                 printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
 315                 mpic->flags |= MPIC_BROKEN_IPI;
 316         }
 317 }
 318
 319 #ifdef CONFIG_MPIC_U3_HT_IRQS
 320
 321 /* Test if an interrupt is sourced from HyperTransport (used on broken U3s)
 322  * to force the edge setting on the MPIC and do the ack workaround.
 323  */
 324 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
 325 {
 326         if (source >= 128 || !mpic->fixups)
 327                 return 0;
 328         return mpic->fixups[source].base != NULL;
 329 }
 330
 331
 332 static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source)
 333 {
 334         struct mpic_irq_fixup *fixup = &mpic->fixups[source];
 335
 336         if (fixup->applebase) {
 337                 unsigned int soff = (fixup->index >> 3) & ~3;
 338                 unsigned int mask = 1U << (fixup->index & 0x1f);
 339                 writel(mask, fixup->applebase + soff);
 340         } else {
 341                 spin_lock(&mpic->fixup_lock);
 342                 writeb(0x11 + 2 * fixup->index, fixup->base + 2);
 343                 writel(fixup->data, fixup->base + 4);
 344                 spin_unlock(&mpic->fixup_lock);
 345         }
 346 }
 347
 348 static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
 349                                       unsigned int irqflags)
 350 {
 351         struct mpic_irq_fixup *fixup = &mpic->fixups[source];
 352         unsigned long flags;
 353         u32 tmp;
 354
 355         if (fixup->base == NULL)
 356                 return;
 357
 358         DBG("startup_ht_interrupt(0x%x, 0x%x) index: %d\n",
 359             source, irqflags, fixup->index);
 360         spin_lock_irqsave(&mpic->fixup_lock, flags);
 361         /* Enable and configure */
 362         writeb(0x10 + 2 * fixup->index, fixup->base + 2);
 363         tmp = readl(fixup->base + 4);
 364         tmp &= ~(0x23U);
 365         if (irqflags & IRQ_LEVEL)
 366                 tmp |= 0x22;
 367         writel(tmp, fixup->base + 4);
 368         spin_unlock_irqrestore(&mpic->fixup_lock, flags);
 369
 370 #ifdef CONFIG_PM
 371         /* use the lowest bit inverted to the actual HW,
 372          * set if this fixup was enabled, clear otherwise */
 373         mpic->save_data[source].fixup_data = tmp | 1;
 374 #endif
 375 }
 376
 377 static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source,
 378                                        unsigned int irqflags)
 379 {
 380         struct mpic_irq_fixup *fixup = &mpic->fixups[source];
 381         unsigned long flags;
 382         u32 tmp;
 383
 384         if (fixup->base == NULL)
 385                 return;
 386
 387         DBG("shutdown_ht_interrupt(0x%x, 0x%x)\n", source, irqflags);
 388
 389         /* Disable */
 390         spin_lock_irqsave(&mpic->fixup_lock, flags);
 391         writeb(0x10 + 2 * fixup->index, fixup->base + 2);
 392         tmp = readl(fixup->base + 4);
 393         tmp |= 1;
 394         writel(tmp, fixup->base + 4);
 395         spin_unlock_irqrestore(&mpic->fixup_lock, flags);
 396
 397 #ifdef CONFIG_PM
 398         /* use the lowest bit inverted to the actual HW,
 399          * set if this fixup was enabled, clear otherwise */
 400         mpic->save_data[source].fixup_data = tmp & ~1;
 401 #endif
 402 }
 403
 404 #ifdef CONFIG_PCI_MSI
 405 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
 406                                     unsigned int devfn)
 407 {
 408         u8 __iomem *base;
 409         u8 pos, flags;
 410         u64 addr = 0;
 411
 412         for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
 413              pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
 414                 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
 415                 if (id == PCI_CAP_ID_HT) {
 416                         id = readb(devbase + pos + 3);
 417                         if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING)
 418                                 break;
 419                 }
 420         }
 421
 422         if (pos == 0)
 423                 return;
 424
 425         base = devbase + pos;
 426
 427         flags = readb(base + HT_MSI_FLAGS);
 428         if (!(flags & HT_MSI_FLAGS_FIXED)) {
 429                 addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK;
 430                 addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32);
 431         }
 432
 433         printk(KERN_DEBUG "mpic:   - HT:%02x.%x %s MSI mapping found @ 0x%lx\n",
 434                 PCI_SLOT(devfn), PCI_FUNC(devfn),
 435                 flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr);
 436
 437         if (!(flags & HT_MSI_FLAGS_ENABLE))
 438                 writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS);
 439 }
 440 #else
 441 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
 442                                     unsigned int devfn)
 443 {
 444         return;
 445 }
 446 #endif
 447
 448 static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase,
 449                                     unsigned int devfn, u32 vdid)
 450 {
 451         int i, irq, n;
 452         u8 __iomem *base;
 453         u32 tmp;
 454         u8 pos;
 455
 456         for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
 457              pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
 458                 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
 459                 if (id == PCI_CAP_ID_HT) {
 460                         id = readb(devbase + pos + 3);
 461                         if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ)
 462                                 break;
 463                 }
 464         }
 465         if (pos == 0)
 466                 return;
 467
 468         base = devbase + pos;
 469         writeb(0x01, base + 2);
 470         n = (readl(base + 4) >> 16) & 0xff;
 471
 472         printk(KERN_INFO "mpic:   - HT:%02x.%x [0x%02x] vendor %04x device %04x"
 473                " has %d irqs\n",
 474                devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1);
 475
 476         for (i = 0; i <= n; i++) {
 477                 writeb(0x10 + 2 * i, base + 2);
 478                 tmp = readl(base + 4);
 479                 irq = (tmp >> 16) & 0xff;
 480                 DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp);
 481                 /* mask it , will be unmasked later */
 482                 tmp |= 0x1;
 483                 writel(tmp, base + 4);
 484                 mpic->fixups[irq].index = i;
 485                 mpic->fixups[irq].base = base;
 486                 /* Apple HT PIC has a non-standard way of doing EOIs */
 487                 if ((vdid & 0xffff) == 0x106b)
 488                         mpic->fixups[irq].applebase = devbase + 0x60;
 489                 else
 490                         mpic->fixups[irq].applebase = NULL;
 491                 writeb(0x11 + 2 * i, base + 2);
 492                 mpic->fixups[irq].data = readl(base + 4) | 0x80000000;
 493         }
 494 }
 495
 496
 497 static void __init mpic_scan_ht_pics(struct mpic *mpic)
 498 {
 499         unsigned int devfn;
 500         u8 __iomem *cfgspace;
 501
 502         printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n");
 503
 504         /* Allocate fixups array */
 505         mpic->fixups = alloc_bootmem(128 * sizeof(struct mpic_irq_fixup));
 506         BUG_ON(mpic->fixups == NULL);
 507         memset(mpic->fixups, 0, 128 * sizeof(struct mpic_irq_fixup));
 508
 509         /* Init spinlock */
 510         spin_lock_init(&mpic->fixup_lock);
 511
 512         /* Map U3 config space. We assume all IO-APICs are on the primary bus
 513          * so we only need to map 64kB.
 514          */
 515         cfgspace = ioremap(0xf2000000, 0x10000);
 516         BUG_ON(cfgspace == NULL);
 517
 518         /* Now we scan all slots. We do a very quick scan, we read the header
 519          * type, vendor ID and device ID only, that's plenty enough
 520          */
 521         for (devfn = 0; devfn < 0x100; devfn++) {
 522                 u8 __iomem *devbase = cfgspace + (devfn << 8);
 523                 u8 hdr_type = readb(devbase + PCI_HEADER_TYPE);
 524                 u32 l = readl(devbase + PCI_VENDOR_ID);
 525                 u16 s;
 526
 527                 DBG("devfn %x, l: %x\n", devfn, l);
 528
 529                 /* If no device, skip */
 530                 if (l == 0xffffffff || l == 0x00000000 ||
 531                     l == 0x0000ffff || l == 0xffff0000)
 532                         goto next;
 533                 /* Check if is supports capability lists */
 534                 s = readw(devbase + PCI_STATUS);
 535                 if (!(s & PCI_STATUS_CAP_LIST))
 536                         goto next;
 537
 538                 mpic_scan_ht_pic(mpic, devbase, devfn, l);
 539                 mpic_scan_ht_msi(mpic, devbase, devfn);
 540
 541         next:
 542                 /* next device, if function 0 */
 543                 if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0)
 544                         devfn += 7;
 545         }
 546 }
 547
 548 #else /* CONFIG_MPIC_U3_HT_IRQS */
 549
 550 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
 551 {
 552         return 0;
 553 }
 554
 555 static void __init mpic_scan_ht_pics(struct mpic *mpic)
 556 {
 557 }
 558
 559 #endif /* CONFIG_MPIC_U3_HT_IRQS */
 560
 561
 562 #define mpic_irq_to_hw(virq)    ((unsigned int)irq_map[virq].hwirq)
 563
 564 /* Find an mpic associated with a given linux interrupt */
 565 static struct mpic *mpic_find(unsigned int irq, unsigned int *is_ipi)
 566 {
 567         unsigned int src = mpic_irq_to_hw(irq);
 568         struct mpic *mpic;
 569
 570         if (irq < NUM_ISA_INTERRUPTS)
 571                 return NULL;
 572
 573         mpic = irq_desc[irq].chip_data;
 574
 575         if (is_ipi)
 576                 *is_ipi = (src >= mpic->ipi_vecs[0] &&
 577                            src <= mpic->ipi_vecs[3]);
 578
 579         return mpic;
 580 }
 581
 582 /* Convert a cpu mask from logical to physical cpu numbers. */
 583 static inline u32 mpic_physmask(u32 cpumask)
 584 {
 585         int i;
 586         u32 mask = 0;
 587
 588         for (i = 0; i < NR_CPUS; ++i, cpumask >>= 1)
 589                 mask |= (cpumask & 1) << get_hard_smp_processor_id(i);
 590         return mask;
 591 }
 592
 593 #ifdef CONFIG_SMP
 594 /* Get the mpic structure from the IPI number */
 595 static inline struct mpic * mpic_from_ipi(unsigned int ipi)
 596 {
 597         return irq_desc[ipi].chip_data;
 598 }
 599 #endif
 600
 601 /* Get the mpic structure from the irq number */
 602 static inline struct mpic * mpic_from_irq(unsigned int irq)
 603 {
 604         return irq_desc[irq].chip_data;
 605 }
 606
 607 /* Send an EOI */
 608 static inline void mpic_eoi(struct mpic *mpic)
 609 {
 610         mpic_cpu_write(MPIC_INFO(CPU_EOI), 0);
 611         (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI));
 612 }
 613
 614 #ifdef CONFIG_SMP
 615 static irqreturn_t mpic_ipi_action(int irq, void *data)
 616 {
 617         long ipi = (long)data;
 618
 619         smp_message_recv(ipi);
 620
 621         return IRQ_HANDLED;
 622 }
 623 #endif /* CONFIG_SMP */
 624
 625 /*
 626  * Linux descriptor level callbacks
 627  */
 628
 629
 630 void mpic_unmask_irq(unsigned int irq)
 631 {
 632         unsigned int loops = 100000;
 633         struct mpic *mpic = mpic_from_irq(irq);
 634         unsigned int src = mpic_irq_to_hw(irq);
 635
 636         DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, irq, src);
 637
 638         mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
 639                        mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) &
 640                        ~MPIC_VECPRI_MASK);
 641         /* make sure mask gets to controller before we return to user */
 642         do {
 643                 if (!loops--) {
 644                         printk(KERN_ERR "mpic_enable_irq timeout\n");
 645                         break;
 646                 }
 647         } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);
 648 }
 649
 650 void mpic_mask_irq(unsigned int irq)
 651 {
 652         unsigned int loops = 100000;
 653         struct mpic *mpic = mpic_from_irq(irq);
 654         unsigned int src = mpic_irq_to_hw(irq);
 655
 656         DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src);
 657
 658         mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
 659                        mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
 660                        MPIC_VECPRI_MASK);
 661
 662         /* make sure mask gets to controller before we return to user */
 663         do {
 664                 if (!loops--) {
 665                         printk(KERN_ERR "mpic_enable_irq timeout\n");
 666                         break;
 667                 }
 668         } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));
 669 }
 670
 671 void mpic_end_irq(unsigned int irq)
 672 {
 673         struct mpic *mpic = mpic_from_irq(irq);
 674
 675 #ifdef DEBUG_IRQ
 676         DBG("%s: end_irq: %d\n", mpic->name, irq);
 677 #endif
 678         /* We always EOI on end_irq() even for edge interrupts since that
 679          * should only lower the priority, the MPIC should have properly
 680          * latched another edge interrupt coming in anyway
 681          */
 682
 683         mpic_eoi(mpic);
 684 }
 685
 686 #ifdef CONFIG_MPIC_U3_HT_IRQS
 687
 688 static void mpic_unmask_ht_irq(unsigned int irq)
 689 {
 690         struct mpic *mpic = mpic_from_irq(irq);
 691         unsigned int src = mpic_irq_to_hw(irq);
 692
 693         mpic_unmask_irq(irq);
 694
 695         if (irq_desc[irq].status & IRQ_LEVEL)
 696                 mpic_ht_end_irq(mpic, src);
 697 }
 698
 699 static unsigned int mpic_startup_ht_irq(unsigned int irq)
 700 {
 701         struct mpic *mpic = mpic_from_irq(irq);
 702         unsigned int src = mpic_irq_to_hw(irq);
 703
 704         mpic_unmask_irq(irq);
 705         mpic_startup_ht_interrupt(mpic, src, irq_desc[irq].status);
 706
 707         return 0;
 708 }
 709
 710 static void mpic_shutdown_ht_irq(unsigned int irq)
 711 {
 712         struct mpic *mpic = mpic_from_irq(irq);
 713         unsigned int src = mpic_irq_to_hw(irq);
 714
 715         mpic_shutdown_ht_interrupt(mpic, src, irq_desc[irq].status);
 716         mpic_mask_irq(irq);
 717 }
 718
 719 static void mpic_end_ht_irq(unsigned int irq)
 720 {
 721         struct mpic *mpic = mpic_from_irq(irq);
 722         unsigned int src = mpic_irq_to_hw(irq);
 723
 724 #ifdef DEBUG_IRQ
 725         DBG("%s: end_irq: %d\n", mpic->name, irq);
 726 #endif
 727         /* We always EOI on end_irq() even for edge interrupts since that
 728          * should only lower the priority, the MPIC should have properly
 729          * latched another edge interrupt coming in anyway
 730          */
 731
 732         if (irq_desc[irq].status & IRQ_LEVEL)
 733                 mpic_ht_end_irq(mpic, src);
 734         mpic_eoi(mpic);
 735 }
 736 #endif /* !CONFIG_MPIC_U3_HT_IRQS */
 737
 738 #ifdef CONFIG_SMP
 739
 740 static void mpic_unmask_ipi(unsigned int irq)
 741 {
 742         struct mpic *mpic = mpic_from_ipi(irq);
 743         unsigned int src = mpic_irq_to_hw(irq) - mpic->ipi_vecs[0];
 744
 745         DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, irq, src);
 746         mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);
 747 }
 748
 749 static void mpic_mask_ipi(unsigned int irq)
 750 {
 751         /* NEVER disable an IPI... that's just plain wrong! */
 752 }
 753
 754 static void mpic_end_ipi(unsigned int irq)
 755 {
 756         struct mpic *mpic = mpic_from_ipi(irq);
 757
 758         /*
 759          * IPIs are marked IRQ_PER_CPU. This has the side effect of
 760          * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from
 761          * applying to them. We EOI them late to avoid re-entering.
 762          * We mark IPI's with IRQF_DISABLED as they must run with
 763          * irqs disabled.
 764          */
 765         mpic_eoi(mpic);
 766 }
 767
 768 #endif /* CONFIG_SMP */
 769
 770 void mpic_set_affinity(unsigned int irq, cpumask_t cpumask)
 771 {
 772         struct mpic *mpic = mpic_from_irq(irq);
 773         unsigned int src = mpic_irq_to_hw(irq);
 774
 775         cpumask_t tmp;
 776
 777         cpus_and(tmp, cpumask, cpu_online_map);
 778
 779         mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),
 780                        mpic_physmask(cpus_addr(tmp)[0]));
 781 }
 782
 783 static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
 784 {
 785         /* Now convert sense value */
 786         switch(type & IRQ_TYPE_SENSE_MASK) {
 787         case IRQ_TYPE_EDGE_RISING:
 788                 return MPIC_INFO(VECPRI_SENSE_EDGE) |
 789                        MPIC_INFO(VECPRI_POLARITY_POSITIVE);
 790         case IRQ_TYPE_EDGE_FALLING:
 791         case IRQ_TYPE_EDGE_BOTH:
 792                 return MPIC_INFO(VECPRI_SENSE_EDGE) |
 793                        MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
 794         case IRQ_TYPE_LEVEL_HIGH:
 795                 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
 796                        MPIC_INFO(VECPRI_POLARITY_POSITIVE);
 797         case IRQ_TYPE_LEVEL_LOW:
 798         default:
 799                 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
 800                        MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
 801         }
 802 }
 803
 804 int mpic_set_irq_type(unsigned int virq, unsigned int flow_type)
 805 {
 806         struct mpic *mpic = mpic_from_irq(virq);
 807         unsigned int src = mpic_irq_to_hw(virq);
 808         struct irq_desc *desc = get_irq_desc(virq);
 809         unsigned int vecpri, vold, vnew;
 810
 811         DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
 812             mpic, virq, src, flow_type);
 813
 814         if (src >= mpic->irq_count)
 815                 return -EINVAL;
 816
 817         if (flow_type == IRQ_TYPE_NONE)
 818                 if (mpic->senses && src < mpic->senses_count)
 819                         flow_type = mpic->senses[src];
 820         if (flow_type == IRQ_TYPE_NONE)
 821                 flow_type = IRQ_TYPE_LEVEL_LOW;
 822
 823         desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
 824         desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
 825         if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
 826                 desc->status |= IRQ_LEVEL;
 827
 828         if (mpic_is_ht_interrupt(mpic, src))
 829                 vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
 830                         MPIC_VECPRI_SENSE_EDGE;
 831         else
 832                 vecpri = mpic_type_to_vecpri(mpic, flow_type);
 833
 834         vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
 835         vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
 836                         MPIC_INFO(VECPRI_SENSE_MASK));
 837         vnew |= vecpri;
 838         if (vold != vnew)
 839                 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);
 840
 841         return 0;
 842 }
 843
 844 static struct irq_chip mpic_irq_chip = {
 845         .mask           = mpic_mask_irq,
 846         .unmask         = mpic_unmask_irq,
 847         .eoi            = mpic_end_irq,
 848         .set_type       = mpic_set_irq_type,
 849 };
 850
 851 #ifdef CONFIG_SMP
 852 static struct irq_chip mpic_ipi_chip = {
 853         .mask           = mpic_mask_ipi,
 854         .unmask         = mpic_unmask_ipi,
 855         .eoi            = mpic_end_ipi,
 856 };
 857 #endif /* CONFIG_SMP */
 858
 859 #ifdef CONFIG_MPIC_U3_HT_IRQS
 860 static struct irq_chip mpic_irq_ht_chip = {
 861         .startup        = mpic_startup_ht_irq,
 862         .shutdown       = mpic_shutdown_ht_irq,
 863         .mask           = mpic_mask_irq,
 864         .unmask         = mpic_unmask_ht_irq,
 865         .eoi            = mpic_end_ht_irq,
 866         .set_type       = mpic_set_irq_type,
 867 };
 868 #endif /* CONFIG_MPIC_U3_HT_IRQS */
 869
 870
 871 static int mpic_host_match(struct irq_host *h, struct device_node *node)
 872 {
 873         /* Exact match, unless mpic node is NULL */
 874         return h->of_node == NULL || h->of_node == node;
 875 }
 876
 877 static int mpic_host_map(struct irq_host *h, unsigned int virq,
 878                          irq_hw_number_t hw)
 879 {
 880         struct mpic *mpic = h->host_data;
 881         struct irq_chip *chip;
 882
 883         DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw);
 884
 885         if (hw == mpic->spurious_vec)
 886                 return -EINVAL;
 887         if (mpic->protected && test_bit(hw, mpic->protected))
 888                 return -EINVAL;
 889
 890 #ifdef CONFIG_SMP
 891         else if (hw >= mpic->ipi_vecs[0]) {
 892                 WARN_ON(!(mpic->flags & MPIC_PRIMARY));
 893
 894                 DBG("mpic: mapping as IPI\n");
 895                 set_irq_chip_data(virq, mpic);
 896                 set_irq_chip_and_handler(virq, &mpic->hc_ipi,
 897                                          handle_percpu_irq);
 898                 return 0;
 899         }
 900 #endif /* CONFIG_SMP */
 901
 902         if (hw >= mpic->irq_count)
 903                 return -EINVAL;
 904
 905         mpic_msi_reserve_hwirq(mpic, hw);
 906
 907         /* Default chip */
 908         chip = &mpic->hc_irq;
 909
 910 #ifdef CONFIG_MPIC_U3_HT_IRQS
 911         /* Check for HT interrupts, override vecpri */
 912         if (mpic_is_ht_interrupt(mpic, hw))
 913                 chip = &mpic->hc_ht_irq;
 914 #endif /* CONFIG_MPIC_U3_HT_IRQS */
 915
 916         DBG("mpic: mapping to irq chip @%p\n", chip);
 917
 918         set_irq_chip_data(virq, mpic);
 919         set_irq_chip_and_handler(virq, chip, handle_fasteoi_irq);
 920
 921         /* Set default irq type */
 922         set_irq_type(virq, IRQ_TYPE_NONE);
 923
 924         return 0;
 925 }
 926
 927 static int mpic_host_xlate(struct irq_host *h, struct device_node *ct,
 928                            u32 *intspec, unsigned int intsize,
 929                            irq_hw_number_t *out_hwirq, unsigned int *out_flags)
 930
 931 {
 932         static unsigned char map_mpic_senses[4] = {
 933                 IRQ_TYPE_EDGE_RISING,
 934                 IRQ_TYPE_LEVEL_LOW,
 935                 IRQ_TYPE_LEVEL_HIGH,
 936                 IRQ_TYPE_EDGE_FALLING,
 937         };
 938
 939         *out_hwirq = intspec[0];
 940         if (intsize > 1) {
 941                 u32 mask = 0x3;
 942
 943                 /* Apple invented a new race of encoding on machines with
 944                  * an HT APIC. They encode, among others, the index within
 945                  * the HT APIC. We don't care about it here since thankfully,
 946                  * it appears that they have the APIC already properly
 947                  * configured, and thus our current fixup code that reads the
 948                  * APIC config works fine. However, we still need to mask out
 949                  * bits in the specifier to make sure we only get bit 0 which
 950                  * is the level/edge bit (the only sense bit exposed by Apple),
 951                  * as their bit 1 means something else.
 952                  */
 953                 if (machine_is(powermac))
 954                         mask = 0x1;
 955                 *out_flags = map_mpic_senses[intspec[1] & mask];
 956         } else
 957                 *out_flags = IRQ_TYPE_NONE;
 958
 959         DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n",
 960             intsize, intspec[0], intspec[1], *out_hwirq, *out_flags);
 961
 962         return 0;
 963 }
 964
 965 static struct irq_host_ops mpic_host_ops = {
 966         .match = mpic_host_match,
 967         .map = mpic_host_map,
 968         .xlate = mpic_host_xlate,
 969 };
 970
 971 /*
 972  * Exported functions
 973  */
 974
 975 struct mpic * __init mpic_alloc(struct device_node *node,
 976                                 phys_addr_t phys_addr,
 977                                 unsigned int flags,
 978                                 unsigned int isu_size,
 979                                 unsigned int irq_count,
 980                                 const char *name)
 981 {
 982         struct mpic     *mpic;
 983         u32             reg;
 984         const char      *vers;
 985         int             i;
 986         int             intvec_top;
 987         u64             paddr = phys_addr;
 988
 989         mpic = alloc_bootmem(sizeof(struct mpic));
 990         if (mpic == NULL)
 991                 return NULL;
 992
 993         memset(mpic, 0, sizeof(struct mpic));
 994         mpic->name = name;
 995
 996         mpic->irqhost = irq_alloc_host(of_node_get(node), IRQ_HOST_MAP_LINEAR,
 997                                        isu_size, &mpic_host_ops,
 998                                        flags & MPIC_LARGE_VECTORS ? 2048 : 256);
 999         if (mpic->irqhost == NULL) {
1000                 of_node_put(node);
1001                 return NULL;
1002         }
1003
1004         mpic->irqhost->host_data = mpic;
1005         mpic->hc_irq = mpic_irq_chip;
1006         mpic->hc_irq.typename = name;
1007         if (flags & MPIC_PRIMARY)
1008                 mpic->hc_irq.set_affinity = mpic_set_affinity;
1009 #ifdef CONFIG_MPIC_U3_HT_IRQS
1010         mpic->hc_ht_irq = mpic_irq_ht_chip;
1011         mpic->hc_ht_irq.typename = name;
1012         if (flags & MPIC_PRIMARY)
1013                 mpic->hc_ht_irq.set_affinity = mpic_set_affinity;
1014 #endif /* CONFIG_MPIC_U3_HT_IRQS */
1015
1016 #ifdef CONFIG_SMP
1017         mpic->hc_ipi = mpic_ipi_chip;
1018         mpic->hc_ipi.typename = name;
1019 #endif /* CONFIG_SMP */
1020
1021         mpic->flags = flags;
1022         mpic->isu_size = isu_size;
1023         mpic->irq_count = irq_count;
1024         mpic->num_sources = 0; /* so far */
1025
1026         if (flags & MPIC_LARGE_VECTORS)
1027                 intvec_top = 2047;
1028         else
1029                 intvec_top = 255;
1030
1031         mpic->timer_vecs[0] = intvec_top - 8;
1032         mpic->timer_vecs[1] = intvec_top - 7;
1033         mpic->timer_vecs[2] = intvec_top - 6;
1034         mpic->timer_vecs[3] = intvec_top - 5;
1035         mpic->ipi_vecs[0]   = intvec_top - 4;
1036         mpic->ipi_vecs[1]   = intvec_top - 3;
1037         mpic->ipi_vecs[2]   = intvec_top - 2;
1038         mpic->ipi_vecs[3]   = intvec_top - 1;
1039         mpic->spurious_vec  = intvec_top;
1040
1041         /* Check for "big-endian" in device-tree */
1042         if (node && of_get_property(node, "big-endian", NULL) != NULL)
1043                 mpic->flags |= MPIC_BIG_ENDIAN;
1044
1045         /* Look for protected sources */
1046         if (node) {
1047                 unsigned int psize, bits, mapsize;
1048                 const u32 *psrc =
1049                         of_get_property(node, "protected-sources", &psize);
1050                 if (psrc) {
1051                         psize /= 4;
1052                         bits = intvec_top + 1;
1053                         mapsize = BITS_TO_LONGS(bits) * sizeof(unsigned long);
1054                         mpic->protected = alloc_bootmem(mapsize);
1055                         BUG_ON(mpic->protected == NULL);
1056                         memset(mpic->protected, 0, mapsize);
1057                         for (i = 0; i < psize; i++) {
1058                                 if (psrc[i] > intvec_top)
1059                                         continue;
1060                                 __set_bit(psrc[i], mpic->protected);
1061                         }
1062                 }
1063         }
1064
1065 #ifdef CONFIG_MPIC_WEIRD
1066         mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)];
1067 #endif
1068
1069         /* default register type */
1070         mpic->reg_type = (flags & MPIC_BIG_ENDIAN) ?
1071                 mpic_access_mmio_be : mpic_access_mmio_le;
1072
1073         /* If no physical address is passed in, a device-node is mandatory */
1074         BUG_ON(paddr == 0 && node == NULL);
1075
1076         /* If no physical address passed in, check if it's dcr based */
1077         if (paddr == 0 && of_get_property(node, "dcr-reg", NULL) != NULL) {
1078 #ifdef CONFIG_PPC_DCR
1079                 mpic->flags |= MPIC_USES_DCR;
1080                 mpic->reg_type = mpic_access_dcr;
1081 #else
1082                 BUG();
1083 #endif /* CONFIG_PPC_DCR */
1084         }
1085
1086         /* If the MPIC is not DCR based, and no physical address was passed
1087          * in, try to obtain one
1088          */
1089         if (paddr == 0 && !(mpic->flags & MPIC_USES_DCR)) {
1090                 const u32 *reg;
1091                 reg = of_get_property(node, "reg", NULL);
1092                 BUG_ON(reg == NULL);
1093                 paddr = of_translate_address(node, reg);
1094                 BUG_ON(paddr == OF_BAD_ADDR);
1095         }
1096
1097         /* Map the global registers */
1098         mpic_map(mpic, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000);
1099         mpic_map(mpic, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
1100
1101         /* Reset */
1102         if (flags & MPIC_WANTS_RESET) {
1103                 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1104                            mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1105                            | MPIC_GREG_GCONF_RESET);
1106                 while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1107                        & MPIC_GREG_GCONF_RESET)
1108                         mb();
1109         }
1110
1111         /* Read feature register, calculate num CPUs and, for non-ISU
1112          * MPICs, num sources as well. On ISU MPICs, sources are counted
1113          * as ISUs are added
1114          */
1115         reg = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
1116         mpic->num_cpus = ((reg & MPIC_GREG_FEATURE_LAST_CPU_MASK)
1117                           >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1;
1118         if (isu_size == 0)
1119                 mpic->num_sources = ((reg & MPIC_GREG_FEATURE_LAST_SRC_MASK)
1120                                      >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1;
1121
1122         /* Map the per-CPU registers */
1123         for (i = 0; i < mpic->num_cpus; i++) {
1124                 mpic_map(mpic, paddr, &mpic->cpuregs[i],
1125                          MPIC_INFO(CPU_BASE) + i * MPIC_INFO(CPU_STRIDE),
1126                          0x1000);
1127         }
1128
1129         /* Initialize main ISU if none provided */
1130         if (mpic->isu_size == 0) {
1131                 mpic->isu_size = mpic->num_sources;
1132                 mpic_map(mpic, paddr, &mpic->isus[0],
1133                          MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1134         }
1135         mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
1136         mpic->isu_mask = (1 << mpic->isu_shift) - 1;
1137
1138         /* Display version */
1139         switch (reg & MPIC_GREG_FEATURE_VERSION_MASK) {
1140         case 1:
1141                 vers = "1.0";
1142                 break;
1143         case 2:
1144                 vers = "1.2";
1145                 break;
1146         case 3:
1147                 vers = "1.3";
1148                 break;
1149         default:
1150                 vers = "<unknown>";
1151                 break;
1152         }
1153         printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx,"
1154                " max %d CPUs\n",
1155                name, vers, (unsigned long long)paddr, mpic->num_cpus);
1156         printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n",
1157                mpic->isu_size, mpic->isu_shift, mpic->isu_mask);
1158
1159         mpic->next = mpics;
1160         mpics = mpic;
1161
1162         if (flags & MPIC_PRIMARY) {
1163                 mpic_primary = mpic;
1164                 irq_set_default_host(mpic->irqhost);
1165         }
1166
1167         return mpic;
1168 }
1169
1170 void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
1171                             phys_addr_t paddr)
1172 {
1173         unsigned int isu_first = isu_num * mpic->isu_size;
1174
1175         BUG_ON(isu_num >= MPIC_MAX_ISU);
1176
1177         mpic_map(mpic, paddr, &mpic->isus[isu_num], 0,
1178                  MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1179         if ((isu_first + mpic->isu_size) > mpic->num_sources)
1180                 mpic->num_sources = isu_first + mpic->isu_size;
1181 }
1182
1183 void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count)
1184 {
1185         mpic->senses = senses;
1186         mpic->senses_count = count;
1187 }
1188
1189 void __init mpic_init(struct mpic *mpic)
1190 {
1191         int i;
1192
1193         BUG_ON(mpic->num_sources == 0);
1194
1195         printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
1196
1197         /* Set current processor priority to max */
1198         mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1199
1200         /* Initialize timers: just disable them all */
1201         for (i = 0; i < 4; i++) {
1202                 mpic_write(mpic->tmregs,
1203                            i * MPIC_INFO(TIMER_STRIDE) +
1204                            MPIC_INFO(TIMER_DESTINATION), 0);
1205                 mpic_write(mpic->tmregs,
1206                            i * MPIC_INFO(TIMER_STRIDE) +
1207                            MPIC_INFO(TIMER_VECTOR_PRI),
1208                            MPIC_VECPRI_MASK |
1209                            (mpic->timer_vecs[0] + i));
1210         }
1211
1212         /* Initialize IPIs to our reserved vectors and mark them disabled for now */
1213         mpic_test_broken_ipi(mpic);
1214         for (i = 0; i < 4; i++) {
1215                 mpic_ipi_write(i,
1216                                MPIC_VECPRI_MASK |
1217                                (10 << MPIC_VECPRI_PRIORITY_SHIFT) |
1218                                (mpic->ipi_vecs[0] + i));
1219         }
1220
1221         /* Initialize interrupt sources */
1222         if (mpic->irq_count == 0)
1223                 mpic->irq_count = mpic->num_sources;
1224
1225         /* Do the HT PIC fixups on U3 broken mpic */
1226         DBG("MPIC flags: %x\n", mpic->flags);
1227         if ((mpic->flags & MPIC_U3_HT_IRQS) && (mpic->flags & MPIC_PRIMARY)) {
1228                 mpic_scan_ht_pics(mpic);
1229                 mpic_u3msi_init(mpic);
1230         }
1231
1232         for (i = 0; i < mpic->num_sources; i++) {
1233                 /* start with vector = source number, and masked */
1234                 u32 vecpri = MPIC_VECPRI_MASK | i |
1235                         (8 << MPIC_VECPRI_PRIORITY_SHIFT);
1236
1237                 /* check if protected */
1238                 if (mpic->protected && test_bit(i, mpic->protected))
1239                         continue;
1240                 /* init hw */
1241                 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
1242                 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1243                                1 << hard_smp_processor_id());
1244         }
1245
1246         /* Init spurious vector */
1247         mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec);
1248
1249         /* Disable 8259 passthrough, if supported */
1250         if (!(mpic->flags & MPIC_NO_PTHROU_DIS))
1251                 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1252                            mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1253                            | MPIC_GREG_GCONF_8259_PTHROU_DIS);
1254
1255         /* Set current processor priority to 0 */
1256         mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1257
1258 #ifdef CONFIG_PM
1259         /* allocate memory to save mpic state */
1260         mpic->save_data = alloc_bootmem(mpic->num_sources * sizeof(struct mpic_irq_save));
1261         BUG_ON(mpic->save_data == NULL);
1262 #endif
1263 }
1264
1265 void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio)
1266 {
1267         u32 v;
1268
1269         v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1270         v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK;
1271         v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio);
1272         mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1273 }
1274
1275 void __init mpic_set_serial_int(struct mpic *mpic, int enable)
1276 {
1277         unsigned long flags;
1278         u32 v;
1279
1280         spin_lock_irqsave(&mpic_lock, flags);
1281         v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1282         if (enable)
1283                 v |= MPIC_GREG_GLOBAL_CONF_1_SIE;
1284         else
1285                 v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE;
1286         mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1287         spin_unlock_irqrestore(&mpic_lock, flags);
1288 }
1289
1290 void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
1291 {
1292         int is_ipi;
1293         struct mpic *mpic = mpic_find(irq, &is_ipi);
1294         unsigned int src = mpic_irq_to_hw(irq);
1295         unsigned long flags;
1296         u32 reg;
1297
1298         spin_lock_irqsave(&mpic_lock, flags);
1299         if (is_ipi) {
1300                 reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &
1301                         ~MPIC_VECPRI_PRIORITY_MASK;
1302                 mpic_ipi_write(src - mpic->ipi_vecs[0],
1303                                reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1304         } else {
1305                 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI))
1306                         & ~MPIC_VECPRI_PRIORITY_MASK;
1307                 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
1308                                reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1309         }
1310         spin_unlock_irqrestore(&mpic_lock, flags);
1311 }
1312
1313 unsigned int mpic_irq_get_priority(unsigned int irq)
1314 {
1315         int is_ipi;
1316         struct mpic *mpic = mpic_find(irq, &is_ipi);
1317         unsigned int src = mpic_irq_to_hw(irq);
1318         unsigned long flags;
1319         u32 reg;
1320
1321         spin_lock_irqsave(&mpic_lock, flags);
1322         if (is_ipi)
1323                 reg = mpic_ipi_read(src = mpic->ipi_vecs[0]);
1324         else
1325                 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
1326         spin_unlock_irqrestore(&mpic_lock, flags);
1327         return (reg & MPIC_VECPRI_PRIORITY_MASK) >> MPIC_VECPRI_PRIORITY_SHIFT;
1328 }
1329
1330 void mpic_setup_this_cpu(void)
1331 {
1332 #ifdef CONFIG_SMP
1333         struct mpic *mpic = mpic_primary;
1334         unsigned long flags;
1335         u32 msk = 1 << hard_smp_processor_id();
1336         unsigned int i;
1337
1338         BUG_ON(mpic == NULL);
1339
1340         DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1341
1342         spin_lock_irqsave(&mpic_lock, flags);
1343
1344         /* let the mpic know we want intrs. default affinity is 0xffffffff
1345          * until changed via /proc. That's how it's done on x86. If we want
1346          * it differently, then we should make sure we also change the default
1347          * values of irq_desc[].affinity in irq.c.
1348          */
1349         if (distribute_irqs) {
1350                 for (i = 0; i < mpic->num_sources ; i++)
1351                         mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1352                                 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk);
1353         }
1354
1355         /* Set current processor priority to 0 */
1356         mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1357
1358         spin_unlock_irqrestore(&mpic_lock, flags);
1359 #endif /* CONFIG_SMP */
1360 }
1361
1362 int mpic_cpu_get_priority(void)
1363 {
1364         struct mpic *mpic = mpic_primary;
1365
1366         return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI));
1367 }
1368
1369 void mpic_cpu_set_priority(int prio)
1370 {
1371         struct mpic *mpic = mpic_primary;
1372
1373         prio &= MPIC_CPU_TASKPRI_MASK;
1374         mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio);
1375 }
1376
1377 /*
1378  * XXX: someone who knows mpic should check this.
1379  * do we need to eoi the ipi including for kexec cpu here (see xics comments)?
1380  * or can we reset the mpic in the new kernel?
1381  */
1382 void mpic_teardown_this_cpu(int secondary)
1383 {
1384         struct mpic *mpic = mpic_primary;
1385         unsigned long flags;
1386         u32 msk = 1 << hard_smp_processor_id();
1387         unsigned int i;
1388
1389         BUG_ON(mpic == NULL);
1390
1391         DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1392         spin_lock_irqsave(&mpic_lock, flags);
1393
1394         /* let the mpic know we don't want intrs.  */
1395         for (i = 0; i < mpic->num_sources ; i++)
1396                 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1397                         mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk);
1398
1399         /* Set current processor priority to max */
1400         mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1401
1402         spin_unlock_irqrestore(&mpic_lock, flags);
1403 }
1404
1405
1406 void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask)
1407 {
1408         struct mpic *mpic = mpic_primary;
1409
1410         BUG_ON(mpic == NULL);
1411
1412 #ifdef DEBUG_IPI
1413         DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no);
1414 #endif
1415
1416         mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) +
1417                        ipi_no * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE),
1418                        mpic_physmask(cpu_mask & cpus_addr(cpu_online_map)[0]));
1419 }
1420
1421 unsigned int mpic_get_one_irq(struct mpic *mpic)
1422 {
1423         u32 src;
1424
1425         src = mpic_cpu_read(MPIC_INFO(CPU_INTACK)) & MPIC_INFO(VECPRI_VECTOR_MASK);
1426 #ifdef DEBUG_LOW
1427         DBG("%s: get_one_irq(): %d\n", mpic->name, src);
1428 #endif
1429         if (unlikely(src == mpic->spurious_vec)) {
1430                 if (mpic->flags & MPIC_SPV_EOI)
1431                         mpic_eoi(mpic);
1432                 return NO_IRQ;
1433         }
1434         if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1435                 if (printk_ratelimit())
1436                         printk(KERN_WARNING "%s: Got protected source %d !\n",
1437                                mpic->name, (int)src);
1438                 mpic_eoi(mpic);
1439                 return NO_IRQ;
1440         }
1441
1442         return irq_linear_revmap(mpic->irqhost, src);
1443 }
1444
1445 unsigned int mpic_get_irq(void)
1446 {
1447         struct mpic *mpic = mpic_primary;
1448
1449         BUG_ON(mpic == NULL);
1450
1451         return mpic_get_one_irq(mpic);
1452 }
1453
1454
1455 #ifdef CONFIG_SMP
1456 void mpic_request_ipis(void)
1457 {
1458         struct mpic *mpic = mpic_primary;
1459         long i, err;
1460         static char *ipi_names[] = {
1461                 "IPI0 (call function)",
1462                 "IPI1 (reschedule)",
1463                 "IPI2 (unused)",
1464                 "IPI3 (debugger break)",
1465         };
1466         BUG_ON(mpic == NULL);
1467
1468         printk(KERN_INFO "mpic: requesting IPIs ... \n");
1469
1470         for (i = 0; i < 4; i++) {
1471                 unsigned int vipi = irq_create_mapping(mpic->irqhost,
1472                                                        mpic->ipi_vecs[0] + i);
1473                 if (vipi == NO_IRQ) {
1474                         printk(KERN_ERR "Failed to map IPI %ld\n", i);
1475                         break;
1476                 }
1477                 err = request_irq(vipi, mpic_ipi_action,
1478                                   IRQF_DISABLED|IRQF_PERCPU,
1479                                   ipi_names[i], (void *)i);
1480                 if (err) {
1481                         printk(KERN_ERR "Request of irq %d for IPI %ld failed\n",
1482                                vipi, i);
1483                         break;
1484                 }
1485         }
1486 }
1487
1488 void smp_mpic_message_pass(int target, int msg)
1489 {
1490         /* make sure we're sending something that translates to an IPI */
1491         if ((unsigned int)msg > 3) {
1492                 printk("SMP %d: smp_message_pass: unknown msg %d\n",
1493                        smp_processor_id(), msg);
1494                 return;
1495         }
1496         switch (target) {
1497         case MSG_ALL:
1498                 mpic_send_ipi(msg, 0xffffffff);
1499                 break;
1500         case MSG_ALL_BUT_SELF:
1501                 mpic_send_ipi(msg, 0xffffffff & ~(1 << smp_processor_id()));
1502                 break;
1503         default:
1504                 mpic_send_ipi(msg, 1 << target);
1505                 break;
1506         }
1507 }
1508
1509 int __init smp_mpic_probe(void)
1510 {
1511         int nr_cpus;
1512
1513         DBG("smp_mpic_probe()...\n");
1514
1515         nr_cpus = cpus_weight(cpu_possible_map);
1516
1517         DBG("nr_cpus: %d\n", nr_cpus);
1518
1519         if (nr_cpus > 1)
1520                 mpic_request_ipis();
1521
1522         return nr_cpus;
1523 }
1524
1525 void __devinit smp_mpic_setup_cpu(int cpu)
1526 {
1527         mpic_setup_this_cpu();
1528 }
1529 #endif /* CONFIG_SMP */
1530
1531 #ifdef CONFIG_PM
1532 static int mpic_suspend(struct sys_device *dev, pm_message_t state)
1533 {
1534         struct mpic *mpic = container_of(dev, struct mpic, sysdev);
1535         int i;
1536
1537         for (i = 0; i < mpic->num_sources; i++) {
1538                 mpic->save_data[i].vecprio =
1539                         mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI));
1540                 mpic->save_data[i].dest =
1541                         mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION));
1542         }
1543
1544         return 0;
1545 }
1546
1547 static int mpic_resume(struct sys_device *dev)
1548 {
1549         struct mpic *mpic = container_of(dev, struct mpic, sysdev);
1550         int i;
1551
1552         for (i = 0; i < mpic->num_sources; i++) {
1553                 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI),
1554                                mpic->save_data[i].vecprio);
1555                 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1556                                mpic->save_data[i].dest);
1557
1558 #ifdef CONFIG_MPIC_U3_HT_IRQS
1559         {
1560                 struct mpic_irq_fixup *fixup = &mpic->fixups[i];
1561
1562                 if (fixup->base) {
1563                         /* we use the lowest bit in an inverted meaning */
1564                         if ((mpic->save_data[i].fixup_data & 1) == 0)
1565                                 continue;
1566
1567                         /* Enable and configure */
1568                         writeb(0x10 + 2 * fixup->index, fixup->base + 2);
1569
1570                         writel(mpic->save_data[i].fixup_data & ~1,
1571                                fixup->base + 4);
1572                 }
1573         }
1574 #endif
1575         } /* end for loop */
1576
1577         return 0;
1578 }
1579 #endif
1580
1581 static struct sysdev_class mpic_sysclass = {
1582 #ifdef CONFIG_PM
1583         .resume = mpic_resume,
1584         .suspend = mpic_suspend,
1585 #endif
1586         set_kset_name("mpic"),
1587 };
1588
1589 static int mpic_init_sys(void)
1590 {
1591         struct mpic *mpic = mpics;
1592         int error, id = 0;
1593
1594         error = sysdev_class_register(&mpic_sysclass);
1595
1596         while (mpic && !error) {
1597                 mpic->sysdev.cls = &mpic_sysclass;
1598                 mpic->sysdev.id = id++;
1599                 error = sysdev_register(&mpic->sysdev);
1600                 mpic = mpic->next;
1601         }
1602         return error;
1603 }
1604
1605 device_initcall(mpic_init_sys);