2 * PS3 Platform spu routines.
4 * Copyright (C) 2006 Sony Computer Entertainment Inc.
5 * Copyright 2006 Sony Corp.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/mmzone.h>
28 #include <asm/spu_priv1.h>
30 #include <asm/lv1call.h>
32 /* spu_management_ops */
35 * enum spe_type - Type of spe to create.
36 * @spe_type_logical: Standard logical spe.
38 * For use with lv1_construct_logical_spe(). The current HV does not support
39 * any types other than those listed.
47 * struct spe_shadow - logical spe shadow register area.
49 * Read-only shadow of spe registers.
53 u8 padding_0140[0x0140];
54 u64 int_status_class0_RW; /* 0x0140 */
55 u64 int_status_class1_RW; /* 0x0148 */
56 u64 int_status_class2_RW; /* 0x0150 */
57 u8 padding_0158[0x0610-0x0158];
58 u64 mfc_dsisr_RW; /* 0x0610 */
59 u8 padding_0618[0x0620-0x0618];
60 u64 mfc_dar_RW; /* 0x0620 */
61 u8 padding_0628[0x0800-0x0628];
62 u64 mfc_dsipr_R; /* 0x0800 */
63 u8 padding_0808[0x0810-0x0808];
64 u64 mfc_lscrr_R; /* 0x0810 */
65 u8 padding_0818[0x0c00-0x0818];
66 u64 mfc_cer_R; /* 0x0c00 */
67 u8 padding_0c08[0x0f00-0x0c08];
68 u64 spe_execution_status; /* 0x0f00 */
69 u8 padding_0f08[0x1000-0x0f08];
73 * enum spe_ex_state - Logical spe execution state.
74 * @spe_ex_state_unexecutable: Uninitialized.
75 * @spe_ex_state_executable: Enabled, not ready.
76 * @spe_ex_state_executed: Ready for use.
78 * The execution state (status) of the logical spe as reported in
79 * struct spe_shadow:spe_execution_status.
83 SPE_EX_STATE_UNEXECUTABLE = 0,
84 SPE_EX_STATE_EXECUTABLE = 2,
85 SPE_EX_STATE_EXECUTED = 3,
89 * struct priv1_cache - Cached values of priv1 registers.
90 * @masks[]: Array of cached spe interrupt masks, indexed by class.
91 * @sr1: Cached mfc_sr1 register.
92 * @tclass_id: Cached mfc_tclass_id register.
102 * struct spu_pdata - Platform state variables.
103 * @spe_id: HV spe id returned by lv1_construct_logical_spe().
104 * @resource_id: HV spe resource id returned by
105 * ps3_repository_read_spe_resource_id().
106 * @priv2_addr: lpar address of spe priv2 area returned by
107 * lv1_construct_logical_spe().
108 * @shadow_addr: lpar address of spe register shadow area returned by
109 * lv1_construct_logical_spe().
110 * @shadow: Virtual (ioremap) address of spe register shadow area.
111 * @cache: Cached values of priv1 registers.
119 struct spe_shadow __iomem *shadow;
120 struct priv1_cache cache;
123 static struct spu_pdata *spu_pdata(struct spu *spu)
128 #define dump_areas(_a, _b, _c, _d, _e) \
129 _dump_areas(_a, _b, _c, _d, _e, __func__, __LINE__)
130 static void _dump_areas(unsigned int spe_id, unsigned long priv2,
131 unsigned long problem, unsigned long ls, unsigned long shadow,
132 const char* func, int line)
134 pr_debug("%s:%d: spe_id: %xh (%u)\n", func, line, spe_id, spe_id);
135 pr_debug("%s:%d: priv2: %lxh\n", func, line, priv2);
136 pr_debug("%s:%d: problem: %lxh\n", func, line, problem);
137 pr_debug("%s:%d: ls: %lxh\n", func, line, ls);
138 pr_debug("%s:%d: shadow: %lxh\n", func, line, shadow);
141 static unsigned long get_vas_id(void)
145 lv1_get_logical_ppe_id(&id);
146 lv1_get_virtual_address_space_id_of_ppe(id, &id);
151 static int __init construct_spu(struct spu *spu)
154 unsigned long unused;
156 result = lv1_construct_logical_spe(PAGE_SHIFT, PAGE_SHIFT, PAGE_SHIFT,
157 PAGE_SHIFT, PAGE_SHIFT, get_vas_id(), SPE_TYPE_LOGICAL,
158 &spu_pdata(spu)->priv2_addr, &spu->problem_phys,
159 &spu->local_store_phys, &unused,
160 &spu_pdata(spu)->shadow_addr,
161 &spu_pdata(spu)->spe_id);
164 pr_debug("%s:%d: lv1_construct_logical_spe failed: %s\n",
165 __func__, __LINE__, ps3_result(result));
172 static int __init add_spu_pages(unsigned long start_addr, unsigned long size)
175 unsigned long start_pfn;
176 unsigned long nr_pages;
177 struct pglist_data *pgdata;
180 BUG_ON(!mem_init_done);
182 start_pfn = start_addr >> PAGE_SHIFT;
183 nr_pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
185 pgdata = NODE_DATA(0);
186 zone = pgdata->node_zones;
188 result = __add_pages(zone, start_pfn, nr_pages);
191 pr_debug("%s:%d: __add_pages failed: (%d)\n",
192 __func__, __LINE__, result);
197 static void spu_unmap(struct spu *spu)
200 iounmap(spu->problem);
201 iounmap((__force u8 __iomem *)spu->local_store);
202 iounmap(spu_pdata(spu)->shadow);
205 static int __init setup_areas(struct spu *spu)
207 struct table {char* name; unsigned long addr; unsigned long size;};
212 result = add_spu_pages(spu->local_store_phys, LS_SIZE);
216 result = add_spu_pages(spu->problem_phys, sizeof(struct spu_problem));
222 spu_pdata(spu)->shadow = __ioremap(
223 spu_pdata(spu)->shadow_addr, sizeof(struct spe_shadow),
224 PAGE_READONLY | _PAGE_NO_CACHE | _PAGE_GUARDED);
225 if (!spu_pdata(spu)->shadow) {
226 pr_debug("%s:%d: ioremap shadow failed\n", __func__, __LINE__);
230 spu->local_store = ioremap(spu->local_store_phys, LS_SIZE);
231 if (!spu->local_store) {
232 pr_debug("%s:%d: ioremap local_store failed\n",
237 spu->problem = ioremap(spu->problem_phys,
238 sizeof(struct spu_problem));
240 pr_debug("%s:%d: ioremap problem failed\n", __func__, __LINE__);
244 spu->priv2 = ioremap(spu_pdata(spu)->priv2_addr,
245 sizeof(struct spu_priv2));
247 pr_debug("%s:%d: ioremap priv2 failed\n", __func__, __LINE__);
251 dump_areas(spu_pdata(spu)->spe_id, spu_pdata(spu)->priv2_addr,
252 spu->problem_phys, spu->local_store_phys,
253 spu_pdata(spu)->shadow_addr);
254 dump_areas(spu_pdata(spu)->spe_id, (unsigned long)spu->priv2,
255 (unsigned long)spu->problem, (unsigned long)spu->local_store,
256 (unsigned long)spu_pdata(spu)->shadow);
266 static int __init setup_interrupts(struct spu *spu)
270 result = ps3_alloc_spe_irq(PS3_BINDING_CPU_ANY, spu_pdata(spu)->spe_id,
276 result = ps3_alloc_spe_irq(PS3_BINDING_CPU_ANY, spu_pdata(spu)->spe_id,
282 result = ps3_alloc_spe_irq(PS3_BINDING_CPU_ANY, spu_pdata(spu)->spe_id,
291 ps3_free_spe_irq(spu->irqs[1]);
293 ps3_free_spe_irq(spu->irqs[0]);
295 spu->irqs[0] = spu->irqs[1] = spu->irqs[2] = NO_IRQ;
299 static int __init enable_spu(struct spu *spu)
303 result = lv1_enable_logical_spe(spu_pdata(spu)->spe_id,
304 spu_pdata(spu)->resource_id);
307 pr_debug("%s:%d: lv1_enable_logical_spe failed: %s\n",
308 __func__, __LINE__, ps3_result(result));
312 result = setup_areas(spu);
317 result = setup_interrupts(spu);
320 goto fail_interrupts;
327 lv1_disable_logical_spe(spu_pdata(spu)->spe_id, 0);
332 static int ps3_destroy_spu(struct spu *spu)
336 pr_debug("%s:%d spu_%d\n", __func__, __LINE__, spu->number);
338 result = lv1_disable_logical_spe(spu_pdata(spu)->spe_id, 0);
341 ps3_free_spe_irq(spu->irqs[2]);
342 ps3_free_spe_irq(spu->irqs[1]);
343 ps3_free_spe_irq(spu->irqs[0]);
345 spu->irqs[0] = spu->irqs[1] = spu->irqs[2] = NO_IRQ;
349 result = lv1_destruct_logical_spe(spu_pdata(spu)->spe_id);
358 static int __init ps3_create_spu(struct spu *spu, void *data)
362 pr_debug("%s:%d spu_%d\n", __func__, __LINE__, spu->number);
364 spu->pdata = kzalloc(sizeof(struct spu_pdata),
372 spu_pdata(spu)->resource_id = (unsigned long)data;
374 /* Init cached reg values to HV defaults. */
376 spu_pdata(spu)->cache.sr1 = 0x33;
378 result = construct_spu(spu);
383 /* For now, just go ahead and enable it. */
385 result = enable_spu(spu);
390 /* Make sure the spu is in SPE_EX_STATE_EXECUTED. */
392 /* need something better here!!! */
393 while (in_be64(&spu_pdata(spu)->shadow->spe_execution_status)
394 != SPE_EX_STATE_EXECUTED)
401 ps3_destroy_spu(spu);
406 static int __init ps3_enumerate_spus(int (*fn)(void *data))
409 unsigned int num_resource_id;
412 result = ps3_repository_read_num_spu_resource_id(&num_resource_id);
414 pr_debug("%s:%d: num_resource_id %u\n", __func__, __LINE__,
418 * For now, just create logical spus equal to the number
419 * of physical spus reserved for the partition.
422 for (i = 0; i < num_resource_id; i++) {
423 enum ps3_spu_resource_type resource_type;
424 unsigned int resource_id;
426 result = ps3_repository_read_spu_resource_id(i,
427 &resource_type, &resource_id);
432 if (resource_type == PS3_SPU_RESOURCE_TYPE_EXCLUSIVE) {
433 result = fn((void*)(unsigned long)resource_id);
441 printk(KERN_WARNING "%s:%d: Error initializing spus\n",
447 const struct spu_management_ops spu_management_ps3_ops = {
448 .enumerate_spus = ps3_enumerate_spus,
449 .create_spu = ps3_create_spu,
450 .destroy_spu = ps3_destroy_spu,
455 static void int_mask_and(struct spu *spu, int class, u64 mask)
459 /* are these serialized by caller??? */
460 old_mask = spu_int_mask_get(spu, class);
461 spu_int_mask_set(spu, class, old_mask & mask);
464 static void int_mask_or(struct spu *spu, int class, u64 mask)
468 old_mask = spu_int_mask_get(spu, class);
469 spu_int_mask_set(spu, class, old_mask | mask);
472 static void int_mask_set(struct spu *spu, int class, u64 mask)
474 spu_pdata(spu)->cache.masks[class] = mask;
475 lv1_set_spe_interrupt_mask(spu_pdata(spu)->spe_id, class,
476 spu_pdata(spu)->cache.masks[class]);
479 static u64 int_mask_get(struct spu *spu, int class)
481 return spu_pdata(spu)->cache.masks[class];
484 static void int_stat_clear(struct spu *spu, int class, u64 stat)
486 /* Note that MFC_DSISR will be cleared when class1[MF] is set. */
488 lv1_clear_spe_interrupt_status(spu_pdata(spu)->spe_id, class,
492 static u64 int_stat_get(struct spu *spu, int class)
496 lv1_get_spe_interrupt_status(spu_pdata(spu)->spe_id, class, &stat);
500 static void cpu_affinity_set(struct spu *spu, int cpu)
505 static u64 mfc_dar_get(struct spu *spu)
507 return in_be64(&spu_pdata(spu)->shadow->mfc_dar_RW);
510 static void mfc_dsisr_set(struct spu *spu, u64 dsisr)
512 /* Nothing to do, cleared in int_stat_clear(). */
515 static u64 mfc_dsisr_get(struct spu *spu)
517 return in_be64(&spu_pdata(spu)->shadow->mfc_dsisr_RW);
520 static void mfc_sdr_setup(struct spu *spu)
525 static void mfc_sr1_set(struct spu *spu, u64 sr1)
527 /* Check bits allowed by HV. */
529 static const u64 allowed = ~(MFC_STATE1_LOCAL_STORAGE_DECODE_MASK
530 | MFC_STATE1_PROBLEM_STATE_MASK);
532 BUG_ON((sr1 & allowed) != (spu_pdata(spu)->cache.sr1 & allowed));
534 spu_pdata(spu)->cache.sr1 = sr1;
535 lv1_set_spe_privilege_state_area_1_register(
536 spu_pdata(spu)->spe_id,
537 offsetof(struct spu_priv1, mfc_sr1_RW),
538 spu_pdata(spu)->cache.sr1);
541 static u64 mfc_sr1_get(struct spu *spu)
543 return spu_pdata(spu)->cache.sr1;
546 static void mfc_tclass_id_set(struct spu *spu, u64 tclass_id)
548 spu_pdata(spu)->cache.tclass_id = tclass_id;
549 lv1_set_spe_privilege_state_area_1_register(
550 spu_pdata(spu)->spe_id,
551 offsetof(struct spu_priv1, mfc_tclass_id_RW),
552 spu_pdata(spu)->cache.tclass_id);
555 static u64 mfc_tclass_id_get(struct spu *spu)
557 return spu_pdata(spu)->cache.tclass_id;
560 static void tlb_invalidate(struct spu *spu)
565 static void resource_allocation_groupID_set(struct spu *spu, u64 id)
570 static u64 resource_allocation_groupID_get(struct spu *spu)
572 return 0; /* No support. */
575 static void resource_allocation_enable_set(struct spu *spu, u64 enable)
580 static u64 resource_allocation_enable_get(struct spu *spu)
582 return 0; /* No support. */
585 const struct spu_priv1_ops spu_priv1_ps3_ops = {
586 .int_mask_and = int_mask_and,
587 .int_mask_or = int_mask_or,
588 .int_mask_set = int_mask_set,
589 .int_mask_get = int_mask_get,
590 .int_stat_clear = int_stat_clear,
591 .int_stat_get = int_stat_get,
592 .cpu_affinity_set = cpu_affinity_set,
593 .mfc_dar_get = mfc_dar_get,
594 .mfc_dsisr_set = mfc_dsisr_set,
595 .mfc_dsisr_get = mfc_dsisr_get,
596 .mfc_sdr_setup = mfc_sdr_setup,
597 .mfc_sr1_set = mfc_sr1_set,
598 .mfc_sr1_get = mfc_sr1_get,
599 .mfc_tclass_id_set = mfc_tclass_id_set,
600 .mfc_tclass_id_get = mfc_tclass_id_get,
601 .tlb_invalidate = tlb_invalidate,
602 .resource_allocation_groupID_set = resource_allocation_groupID_set,
603 .resource_allocation_groupID_get = resource_allocation_groupID_get,
604 .resource_allocation_enable_set = resource_allocation_enable_set,
605 .resource_allocation_enable_get = resource_allocation_enable_get,
608 void ps3_spu_set_platform(void)
610 spu_priv1_ops = &spu_priv1_ps3_ops;
611 spu_management_ops = &spu_management_ps3_ops;