2 * Support for PCI bridges found on Power Macintoshes.
4 * Copyright (C) 2003 Benjamin Herrenschmuidt (benh@kernel.crashing.org)
5 * Copyright (C) 1997 Paul Mackerras (paulus@samba.org)
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
13 #include <linux/kernel.h>
14 #include <linux/pci.h>
15 #include <linux/delay.h>
16 #include <linux/string.h>
17 #include <linux/init.h>
18 #include <linux/bootmem.h>
20 #include <asm/sections.h>
23 #include <asm/pci-bridge.h>
24 #include <asm/machdep.h>
25 #include <asm/pmac_feature.h>
27 #include <asm/iommu.h>
28 #include <asm/ppc-pci.h>
34 #define DBG(x...) printk(x)
39 static int add_bridge(struct device_node *dev);
41 /* XXX Could be per-controller, but I don't think we risk anything by
42 * assuming we won't have both UniNorth and Bandit */
43 static int has_uninorth;
45 static struct pci_controller *u3_agp;
46 static struct pci_controller *u3_ht;
47 #endif /* CONFIG_PPC64 */
49 extern u8 pci_cache_line_size;
50 extern int pcibios_assign_bus_offset;
52 struct device_node *k2_skiplist[2];
55 * Magic constants for enabling cache coherency in the bandit/PSX bridge.
57 #define BANDIT_DEVID_2 8
58 #define BANDIT_REVID 3
60 #define BANDIT_DEVNUM 11
61 #define BANDIT_MAGIC 0x50
62 #define BANDIT_COHERENT 0x40
64 static int __init fixup_one_level_bus_range(struct device_node *node, int higher)
66 for (; node != 0;node = node->sibling) {
68 unsigned int *class_code;
71 /* For PCI<->PCI bridges or CardBus bridges, we go down */
72 class_code = (unsigned int *) get_property(node, "class-code", NULL);
73 if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
74 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS))
76 bus_range = (int *) get_property(node, "bus-range", &len);
77 if (bus_range != NULL && len > 2 * sizeof(int)) {
78 if (bus_range[1] > higher)
79 higher = bus_range[1];
81 higher = fixup_one_level_bus_range(node->child, higher);
86 /* This routine fixes the "bus-range" property of all bridges in the
87 * system since they tend to have their "last" member wrong on macs
89 * Note that the bus numbers manipulated here are OF bus numbers, they
90 * are not Linux bus numbers.
92 static void __init fixup_bus_range(struct device_node *bridge)
97 /* Lookup the "bus-range" property for the hose */
98 bus_range = (int *) get_property(bridge, "bus-range", &len);
99 if (bus_range == NULL || len < 2 * sizeof(int)) {
100 printk(KERN_WARNING "Can't get bus-range for %s\n",
104 bus_range[1] = fixup_one_level_bus_range(bridge->child, bus_range[1]);
108 * Apple MacRISC (U3, UniNorth, Bandit, Chaos) PCI controllers.
110 * The "Bandit" version is present in all early PCI PowerMacs,
111 * and up to the first ones using Grackle. Some machines may
112 * have 2 bandit controllers (2 PCI busses).
114 * "Chaos" is used in some "Bandit"-type machines as a bridge
115 * for the separate display bus. It is accessed the same
116 * way as bandit, but cannot be probed for devices. It therefore
117 * has its own config access functions.
119 * The "UniNorth" version is present in all Core99 machines
120 * (iBook, G4, new IMacs, and all the recent Apple machines).
121 * It contains 3 controllers in one ASIC.
123 * The U3 is the bridge used on G5 machines. It contains an
124 * AGP bus which is dealt with the old UniNorth access routines
125 * and a HyperTransport bus which uses its own set of access
129 #define MACRISC_CFA0(devfn, off) \
130 ((1 << (unsigned long)PCI_SLOT(dev_fn)) \
131 | (((unsigned long)PCI_FUNC(dev_fn)) << 8) \
132 | (((unsigned long)(off)) & 0xFCUL))
134 #define MACRISC_CFA1(bus, devfn, off) \
135 ((((unsigned long)(bus)) << 16) \
136 |(((unsigned long)(devfn)) << 8) \
137 |(((unsigned long)(off)) & 0xFCUL) \
140 static unsigned long macrisc_cfg_access(struct pci_controller* hose,
141 u8 bus, u8 dev_fn, u8 offset)
145 if (bus == hose->first_busno) {
146 if (dev_fn < (11 << 3))
148 caddr = MACRISC_CFA0(dev_fn, offset);
150 caddr = MACRISC_CFA1(bus, dev_fn, offset);
152 /* Uninorth will return garbage if we don't read back the value ! */
154 out_le32(hose->cfg_addr, caddr);
155 } while (in_le32(hose->cfg_addr) != caddr);
157 offset &= has_uninorth ? 0x07 : 0x03;
158 return ((unsigned long)hose->cfg_data) + offset;
161 static int macrisc_read_config(struct pci_bus *bus, unsigned int devfn,
162 int offset, int len, u32 *val)
164 struct pci_controller *hose;
167 hose = pci_bus_to_host(bus);
169 return PCIBIOS_DEVICE_NOT_FOUND;
171 addr = macrisc_cfg_access(hose, bus->number, devfn, offset);
173 return PCIBIOS_DEVICE_NOT_FOUND;
175 * Note: the caller has already checked that offset is
176 * suitably aligned and that len is 1, 2 or 4.
180 *val = in_8((u8 *)addr);
183 *val = in_le16((u16 *)addr);
186 *val = in_le32((u32 *)addr);
189 return PCIBIOS_SUCCESSFUL;
192 static int macrisc_write_config(struct pci_bus *bus, unsigned int devfn,
193 int offset, int len, u32 val)
195 struct pci_controller *hose;
198 hose = pci_bus_to_host(bus);
200 return PCIBIOS_DEVICE_NOT_FOUND;
202 addr = macrisc_cfg_access(hose, bus->number, devfn, offset);
204 return PCIBIOS_DEVICE_NOT_FOUND;
206 * Note: the caller has already checked that offset is
207 * suitably aligned and that len is 1, 2 or 4.
211 out_8((u8 *)addr, val);
212 (void) in_8((u8 *)addr);
215 out_le16((u16 *)addr, val);
216 (void) in_le16((u16 *)addr);
219 out_le32((u32 *)addr, val);
220 (void) in_le32((u32 *)addr);
223 return PCIBIOS_SUCCESSFUL;
226 static struct pci_ops macrisc_pci_ops =
234 * Verify that a specific (bus, dev_fn) exists on chaos
237 chaos_validate_dev(struct pci_bus *bus, int devfn, int offset)
239 struct device_node *np;
240 u32 *vendor, *device;
242 np = pci_busdev_to_OF_node(bus, devfn);
244 return PCIBIOS_DEVICE_NOT_FOUND;
246 vendor = (u32 *)get_property(np, "vendor-id", NULL);
247 device = (u32 *)get_property(np, "device-id", NULL);
248 if (vendor == NULL || device == NULL)
249 return PCIBIOS_DEVICE_NOT_FOUND;
251 if ((*vendor == 0x106b) && (*device == 3) && (offset >= 0x10)
252 && (offset != 0x14) && (offset != 0x18) && (offset <= 0x24))
253 return PCIBIOS_BAD_REGISTER_NUMBER;
255 return PCIBIOS_SUCCESSFUL;
259 chaos_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
262 int result = chaos_validate_dev(bus, devfn, offset);
263 if (result == PCIBIOS_BAD_REGISTER_NUMBER)
265 if (result != PCIBIOS_SUCCESSFUL)
267 return macrisc_read_config(bus, devfn, offset, len, val);
271 chaos_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
274 int result = chaos_validate_dev(bus, devfn, offset);
275 if (result != PCIBIOS_SUCCESSFUL)
277 return macrisc_write_config(bus, devfn, offset, len, val);
280 static struct pci_ops chaos_pci_ops =
286 static void __init setup_chaos(struct pci_controller *hose,
287 struct reg_property *addr)
289 /* assume a `chaos' bridge */
290 hose->ops = &chaos_pci_ops;
291 hose->cfg_addr = ioremap(addr->address + 0x800000, 0x1000);
292 hose->cfg_data = ioremap(addr->address + 0xc00000, 0x1000);
295 #define setup_chaos(hose, addr)
296 #endif /* CONFIG_PPC32 */
300 * These versions of U3 HyperTransport config space access ops do not
301 * implement self-view of the HT host yet
305 * This function deals with some "special cases" devices.
307 * 0 -> No special case
308 * 1 -> Skip the device but act as if the access was successfull
309 * (return 0xff's on reads, eventually, cache config space
310 * accesses in a later version)
311 * -1 -> Hide the device (unsuccessful acess)
313 static int u3_ht_skip_device(struct pci_controller *hose,
314 struct pci_bus *bus, unsigned int devfn)
316 struct device_node *busdn, *dn;
319 /* We only allow config cycles to devices that are in OF device-tree
320 * as we are apparently having some weird things going on with some
321 * revs of K2 on recent G5s
324 busdn = pci_device_to_OF_node(bus->self);
326 busdn = hose->arch_data;
327 for (dn = busdn->child; dn; dn = dn->sibling)
328 if (dn->data && PCI_DN(dn)->devfn == devfn)
334 * When a device in K2 is powered down, we die on config
335 * cycle accesses. Fix that here.
338 if (k2_skiplist[i] == dn)
344 #define U3_HT_CFA0(devfn, off) \
345 ((((unsigned long)devfn) << 8) | offset)
346 #define U3_HT_CFA1(bus, devfn, off) \
347 (U3_HT_CFA0(devfn, off) \
348 + (((unsigned long)bus) << 16) \
351 static unsigned long u3_ht_cfg_access(struct pci_controller* hose,
352 u8 bus, u8 devfn, u8 offset)
354 if (bus == hose->first_busno) {
355 /* For now, we don't self probe U3 HT bridge */
356 if (PCI_SLOT(devfn) == 0)
358 return ((unsigned long)hose->cfg_data) + U3_HT_CFA0(devfn, offset);
360 return ((unsigned long)hose->cfg_data) + U3_HT_CFA1(bus, devfn, offset);
363 static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn,
364 int offset, int len, u32 *val)
366 struct pci_controller *hose;
369 hose = pci_bus_to_host(bus);
371 return PCIBIOS_DEVICE_NOT_FOUND;
373 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
375 return PCIBIOS_DEVICE_NOT_FOUND;
377 switch (u3_ht_skip_device(hose, bus, devfn)) {
385 *val = 0xffff; break;
387 *val = 0xfffffffful; break;
389 return PCIBIOS_SUCCESSFUL;
391 return PCIBIOS_DEVICE_NOT_FOUND;
395 * Note: the caller has already checked that offset is
396 * suitably aligned and that len is 1, 2 or 4.
400 *val = in_8((u8 *)addr);
403 *val = in_le16((u16 *)addr);
406 *val = in_le32((u32 *)addr);
409 return PCIBIOS_SUCCESSFUL;
412 static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn,
413 int offset, int len, u32 val)
415 struct pci_controller *hose;
418 hose = pci_bus_to_host(bus);
420 return PCIBIOS_DEVICE_NOT_FOUND;
422 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
424 return PCIBIOS_DEVICE_NOT_FOUND;
426 switch (u3_ht_skip_device(hose, bus, devfn)) {
430 return PCIBIOS_SUCCESSFUL;
432 return PCIBIOS_DEVICE_NOT_FOUND;
436 * Note: the caller has already checked that offset is
437 * suitably aligned and that len is 1, 2 or 4.
441 out_8((u8 *)addr, val);
442 (void) in_8((u8 *)addr);
445 out_le16((u16 *)addr, val);
446 (void) in_le16((u16 *)addr);
449 out_le32((u32 *)addr, val);
450 (void) in_le32((u32 *)addr);
453 return PCIBIOS_SUCCESSFUL;
456 static struct pci_ops u3_ht_pci_ops =
461 #endif /* CONFIG_PPC64 */
465 * For a bandit bridge, turn on cache coherency if necessary.
466 * N.B. we could clean this up using the hose ops directly.
468 static void __init init_bandit(struct pci_controller *bp)
470 unsigned int vendev, magic;
473 /* read the word at offset 0 in config space for device 11 */
474 out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + PCI_VENDOR_ID);
476 vendev = in_le32(bp->cfg_data);
477 if (vendev == (PCI_DEVICE_ID_APPLE_BANDIT << 16) +
478 PCI_VENDOR_ID_APPLE) {
479 /* read the revision id */
480 out_le32(bp->cfg_addr,
481 (1UL << BANDIT_DEVNUM) + PCI_REVISION_ID);
483 rev = in_8(bp->cfg_data);
484 if (rev != BANDIT_REVID)
486 "Unknown revision %d for bandit\n", rev);
487 } else if (vendev != (BANDIT_DEVID_2 << 16) + PCI_VENDOR_ID_APPLE) {
488 printk(KERN_WARNING "bandit isn't? (%x)\n", vendev);
492 /* read the word at offset 0x50 */
493 out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + BANDIT_MAGIC);
495 magic = in_le32(bp->cfg_data);
496 if ((magic & BANDIT_COHERENT) != 0)
498 magic |= BANDIT_COHERENT;
500 out_le32(bp->cfg_data, magic);
501 printk(KERN_INFO "Cache coherency enabled for bandit/PSX\n");
505 * Tweak the PCI-PCI bridge chip on the blue & white G3s.
507 static void __init init_p2pbridge(void)
509 struct device_node *p2pbridge;
510 struct pci_controller* hose;
514 /* XXX it would be better here to identify the specific
515 PCI-PCI bridge chip we have. */
516 if ((p2pbridge = find_devices("pci-bridge")) == 0
517 || p2pbridge->parent == NULL
518 || strcmp(p2pbridge->parent->name, "pci") != 0)
520 if (pci_device_from_OF_node(p2pbridge, &bus, &devfn) < 0) {
521 DBG("Can't find PCI infos for PCI<->PCI bridge\n");
524 /* Warning: At this point, we have not yet renumbered all busses.
525 * So we must use OF walking to find out hose
527 hose = pci_find_hose_for_OF_device(p2pbridge);
529 DBG("Can't find hose for PCI<->PCI bridge\n");
532 if (early_read_config_word(hose, bus, devfn,
533 PCI_BRIDGE_CONTROL, &val) < 0) {
534 printk(KERN_ERR "init_p2pbridge: couldn't read bridge control\n");
537 val &= ~PCI_BRIDGE_CTL_MASTER_ABORT;
538 early_write_config_word(hose, bus, devfn, PCI_BRIDGE_CONTROL, val);
542 * Some Apple desktop machines have a NEC PD720100A USB2 controller
543 * on the motherboard. Open Firmware, on these, will disable the
544 * EHCI part of it so it behaves like a pair of OHCI's. This fixup
545 * code re-enables it ;)
547 static void __init fixup_nec_usb2(void)
549 struct device_node *nec;
551 for (nec = NULL; (nec = of_find_node_by_name(nec, "usb")) != NULL;) {
552 struct pci_controller *hose;
556 prop = (u32 *)get_property(nec, "vendor-id", NULL);
561 prop = (u32 *)get_property(nec, "device-id", NULL);
566 prop = (u32 *)get_property(nec, "reg", NULL);
569 devfn = (prop[0] >> 8) & 0xff;
570 bus = (prop[0] >> 16) & 0xff;
571 if (PCI_FUNC(devfn) != 0)
573 hose = pci_find_hose_for_OF_device(nec);
576 early_read_config_dword(hose, bus, devfn, 0xe4, &data);
578 printk("Found NEC PD720100A USB2 chip with disabled EHCI, fixing up...\n");
580 early_write_config_dword(hose, bus, devfn, 0xe4, data);
581 early_write_config_byte(hose, bus, devfn | 2, PCI_INTERRUPT_LINE,
587 #define GRACKLE_CFA(b, d, o) (0x80 | ((b) << 8) | ((d) << 16) \
588 | (((o) & ~3) << 24))
590 #define GRACKLE_PICR1_STG 0x00000040
591 #define GRACKLE_PICR1_LOOPSNOOP 0x00000010
593 /* N.B. this is called before bridges is initialized, so we can't
594 use grackle_pcibios_{read,write}_config_dword. */
595 static inline void grackle_set_stg(struct pci_controller* bp, int enable)
599 out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8));
600 val = in_le32(bp->cfg_data);
601 val = enable? (val | GRACKLE_PICR1_STG) :
602 (val & ~GRACKLE_PICR1_STG);
603 out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8));
604 out_le32(bp->cfg_data, val);
605 (void)in_le32(bp->cfg_data);
608 static inline void grackle_set_loop_snoop(struct pci_controller *bp, int enable)
612 out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8));
613 val = in_le32(bp->cfg_data);
614 val = enable? (val | GRACKLE_PICR1_LOOPSNOOP) :
615 (val & ~GRACKLE_PICR1_LOOPSNOOP);
616 out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8));
617 out_le32(bp->cfg_data, val);
618 (void)in_le32(bp->cfg_data);
621 void __init setup_grackle(struct pci_controller *hose)
623 setup_indirect_pci(hose, 0xfec00000, 0xfee00000);
624 if (machine_is_compatible("AAPL,PowerBook1998"))
625 grackle_set_loop_snoop(hose, 1);
626 #if 0 /* Disabled for now, HW problems ??? */
627 grackle_set_stg(hose, 1);
631 static void __init setup_bandit(struct pci_controller *hose,
632 struct reg_property *addr)
634 hose->ops = ¯isc_pci_ops;
635 hose->cfg_addr = ioremap(addr->address + 0x800000, 0x1000);
636 hose->cfg_data = ioremap(addr->address + 0xc00000, 0x1000);
640 static int __init setup_uninorth(struct pci_controller *hose,
641 struct reg_property *addr)
643 pci_assign_all_buses = 1;
645 hose->ops = ¯isc_pci_ops;
646 hose->cfg_addr = ioremap(addr->address + 0x800000, 0x1000);
647 hose->cfg_data = ioremap(addr->address + 0xc00000, 0x1000);
648 /* We "know" that the bridge at f2000000 has the PCI slots. */
649 return addr->address == 0xf2000000;
654 static void __init setup_u3_agp(struct pci_controller* hose)
656 /* On G5, we move AGP up to high bus number so we don't need
657 * to reassign bus numbers for HT. If we ever have P2P bridges
658 * on AGP, we'll have to move pci_assign_all_busses to the
659 * pci_controller structure so we enable it for AGP and not for
661 * We hard code the address because of the different size of
662 * the reg address cell, we shall fix that by killing struct
663 * reg_property and using some accessor functions instead
665 hose->first_busno = 0xf0;
666 hose->last_busno = 0xff;
668 hose->ops = ¯isc_pci_ops;
669 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);
670 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);
675 static void __init setup_u3_ht(struct pci_controller* hose)
677 struct device_node *np = (struct device_node *)hose->arch_data;
680 hose->ops = &u3_ht_pci_ops;
682 /* We hard code the address because of the different size of
683 * the reg address cell, we shall fix that by killing struct
684 * reg_property and using some accessor functions instead
686 hose->cfg_data = (volatile unsigned char *)ioremap(0xf2000000, 0x02000000);
689 * /ht node doesn't expose a "ranges" property, so we "remove" regions that
690 * have been allocated to AGP. So far, this version of the code doesn't assign
691 * any of the 0xfxxxxxxx "fine" memory regions to /ht.
692 * We need to fix that sooner or later by either parsing all child "ranges"
693 * properties or figuring out the U3 address space decoding logic and
694 * then read its configuration register (if any).
696 hose->io_base_phys = 0xf4000000;
697 hose->pci_io_size = 0x00400000;
698 hose->io_resource.name = np->full_name;
699 hose->io_resource.start = 0;
700 hose->io_resource.end = 0x003fffff;
701 hose->io_resource.flags = IORESOURCE_IO;
702 hose->pci_mem_offset = 0;
703 hose->first_busno = 0;
704 hose->last_busno = 0xef;
705 hose->mem_resources[0].name = np->full_name;
706 hose->mem_resources[0].start = 0x80000000;
707 hose->mem_resources[0].end = 0xefffffff;
708 hose->mem_resources[0].flags = IORESOURCE_MEM;
712 if (u3_agp == NULL) {
713 DBG("U3 has no AGP, using full resource range\n");
717 /* We "remove" the AGP resources from the resources allocated to HT, that
718 * is we create "holes". However, that code does assumptions that so far
719 * happen to be true (cross fingers...), typically that resources in the
720 * AGP node are properly ordered
723 for (i=0; i<3; i++) {
724 struct resource *res = &u3_agp->mem_resources[i];
725 if (res->flags != IORESOURCE_MEM)
727 /* We don't care about "fine" resources */
728 if (res->start >= 0xf0000000)
730 /* Check if it's just a matter of "shrinking" us in one direction */
731 if (hose->mem_resources[cur].start == res->start) {
732 DBG("U3/HT: shrink start of %d, %08lx -> %08lx\n",
733 cur, hose->mem_resources[cur].start, res->end + 1);
734 hose->mem_resources[cur].start = res->end + 1;
737 if (hose->mem_resources[cur].end == res->end) {
738 DBG("U3/HT: shrink end of %d, %08lx -> %08lx\n",
739 cur, hose->mem_resources[cur].end, res->start - 1);
740 hose->mem_resources[cur].end = res->start - 1;
743 /* No, it's not the case, we need a hole */
745 /* not enough resources for a hole, we drop part of the range */
746 printk(KERN_WARNING "Running out of resources for /ht host !\n");
747 hose->mem_resources[cur].end = res->start - 1;
751 DBG("U3/HT: hole, %d end at %08lx, %d start at %08lx\n",
752 cur-1, res->start - 1, cur, res->end + 1);
753 hose->mem_resources[cur].name = np->full_name;
754 hose->mem_resources[cur].flags = IORESOURCE_MEM;
755 hose->mem_resources[cur].start = res->end + 1;
756 hose->mem_resources[cur].end = hose->mem_resources[cur-1].end;
757 hose->mem_resources[cur-1].end = res->start - 1;
761 /* XXX this needs to be converged between ppc32 and ppc64... */
762 static struct pci_controller * __init pcibios_alloc_controller(void)
764 struct pci_controller *hose;
766 hose = alloc_bootmem(sizeof(struct pci_controller));
768 pci_setup_pci_controller(hose);
774 * We assume that if we have a G3 powermac, we have one bridge called
775 * "pci" (a MPC106) and no bandit or chaos bridges, and contrariwise,
776 * if we have one or more bandit or chaos bridges, we don't have a MPC106.
778 static int __init add_bridge(struct device_node *dev)
781 struct pci_controller *hose;
783 struct reg_property *addr;
789 DBG("Adding PCI host bridge %s\n", dev->full_name);
793 addr = (struct reg_property *) get_property(dev, "reg", &len);
794 if (addr == NULL || len < sizeof(*addr)) {
795 printk(KERN_WARNING "Can't use %s: no address\n",
800 bus_range = (int *) get_property(dev, "bus-range", &len);
801 if (bus_range == NULL || len < 2 * sizeof(int)) {
802 printk(KERN_WARNING "Can't get bus-range for %s, assume bus 0\n",
806 hose = pcibios_alloc_controller();
809 hose->arch_data = dev;
810 hose->first_busno = bus_range ? bus_range[0] : 0;
811 hose->last_busno = bus_range ? bus_range[1] : 0xff;
815 if (device_is_compatible(dev, "u3-agp")) {
817 disp_name = "U3-AGP";
819 } else if (device_is_compatible(dev, "u3-ht")) {
824 printk(KERN_INFO "Found %s PCI host bridge. Firmware bus number: %d->%d\n",
825 disp_name, hose->first_busno, hose->last_busno);
827 if (device_is_compatible(dev, "uni-north")) {
828 primary = setup_uninorth(hose, addr);
829 disp_name = "UniNorth";
830 } else if (strcmp(dev->name, "pci") == 0) {
831 /* XXX assume this is a mpc106 (grackle) */
833 disp_name = "Grackle (MPC106)";
834 } else if (strcmp(dev->name, "bandit") == 0) {
835 setup_bandit(hose, addr);
836 disp_name = "Bandit";
837 } else if (strcmp(dev->name, "chaos") == 0) {
838 setup_chaos(hose, addr);
842 printk(KERN_INFO "Found %s PCI host bridge at 0x%08lx. Firmware bus number: %d->%d\n",
843 disp_name, addr->address, hose->first_busno, hose->last_busno);
845 DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
846 hose, hose->cfg_addr, hose->cfg_data);
848 /* Interpret the "ranges" property */
849 /* This also maps the I/O region and sets isa_io/mem_base */
850 pci_process_bridge_OF_ranges(hose, dev, primary);
852 /* Fixup "bus-range" OF property */
853 fixup_bus_range(dev);
859 pcibios_fixup_OF_interrupts(void)
861 struct pci_dev* dev = NULL;
864 * Open Firmware often doesn't initialize the
865 * PCI_INTERRUPT_LINE config register properly, so we
866 * should find the device node and apply the interrupt
867 * obtained from the OF device-tree
869 for_each_pci_dev(dev) {
870 struct device_node *node;
871 node = pci_device_to_OF_node(dev);
872 /* this is the node, see if it has interrupts */
873 if (node && node->n_intrs > 0)
874 dev->irq = node->intrs[0].line;
875 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
880 pmac_pcibios_fixup(void)
882 /* Fixup interrupts according to OF tree */
883 pcibios_fixup_OF_interrupts();
887 static void __init pmac_fixup_phb_resources(void)
889 struct pci_controller *hose, *tmp;
891 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
892 printk(KERN_INFO "PCI Host %d, io start: %lx; io end: %lx\n",
894 hose->io_resource.start, hose->io_resource.end);
899 void __init pmac_pci_init(void)
901 struct device_node *np, *root;
902 struct device_node *ht = NULL;
904 root = of_find_node_by_path("/");
906 printk(KERN_CRIT "pmac_pci_init: can't find root "
910 for (np = NULL; (np = of_get_next_child(root, np)) != NULL;) {
911 if (np->name == NULL)
913 if (strcmp(np->name, "bandit") == 0
914 || strcmp(np->name, "chaos") == 0
915 || strcmp(np->name, "pci") == 0) {
916 if (add_bridge(np) == 0)
919 if (strcmp(np->name, "ht") == 0) {
927 /* Probe HT last as it relies on the agp resources to be already
930 if (ht && add_bridge(ht) != 0)
934 * We need to call pci_setup_phb_io for the HT bridge first
935 * so it gets the I/O port numbers starting at 0, and we
936 * need to call it for the AGP bridge after that so it gets
937 * small positive I/O port numbers.
940 pci_setup_phb_io(u3_ht, 1);
942 pci_setup_phb_io(u3_agp, 0);
945 * On ppc64, fixup the IO resources on our host bridges as
946 * the common code does it only for children of the host bridges
948 pmac_fixup_phb_resources();
950 /* Setup the linkage between OF nodes and PHBs */
953 /* Fixup the PCI<->OF mapping for U3 AGP due to bus renumbering. We
954 * assume there is no P2P bridge on the AGP bus, which should be a
955 * safe assumptions hopefully.
958 struct device_node *np = u3_agp->arch_data;
959 PCI_DN(np)->busno = 0xf0;
960 for (np = np->child; np; np = np->sibling)
961 PCI_DN(np)->busno = 0xf0;
964 /* map in PCI I/O space */
967 /* pmac_check_ht_link(); */
969 /* Tell pci.c to not use the common resource allocation mechanism */
975 #else /* CONFIG_PPC64 */
979 /* We are still having some issues with the Xserve G4, enabling
980 * some offset between bus number and domains for now when we
981 * assign all busses should help for now
983 if (pci_assign_all_buses)
984 pcibios_assign_bus_offset = 0x10;
989 pmac_pci_enable_device_hook(struct pci_dev *dev, int initial)
991 struct device_node* node;
995 node = pci_device_to_OF_node(dev);
997 /* We don't want to enable USB controllers absent from the OF tree
998 * (iBook second controller)
1000 if (dev->vendor == PCI_VENDOR_ID_APPLE
1001 && (dev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x10))
1003 printk(KERN_INFO "Apple USB OHCI %s disabled by firmware\n",
1011 uninorth_child = node->parent &&
1012 device_is_compatible(node->parent, "uni-north");
1014 /* Firewire & GMAC were disabled after PCI probe, the driver is
1015 * claiming them, we must re-enable them now.
1017 if (uninorth_child && !strcmp(node->name, "firewire") &&
1018 (device_is_compatible(node, "pci106b,18") ||
1019 device_is_compatible(node, "pci106b,30") ||
1020 device_is_compatible(node, "pci11c1,5811"))) {
1021 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, node, 0, 1);
1022 pmac_call_feature(PMAC_FTR_1394_ENABLE, node, 0, 1);
1025 if (uninorth_child && !strcmp(node->name, "ethernet") &&
1026 device_is_compatible(node, "gmac")) {
1027 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, node, 0, 1);
1035 * Make sure PCI is correctly configured
1037 * We use old pci_bios versions of the function since, by
1038 * default, gmac is not powered up, and so will be absent
1039 * from the kernel initial PCI lookup.
1041 * Should be replaced by 2.4 new PCI mechanisms and really
1042 * register the device.
1044 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1045 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
1046 | PCI_COMMAND_INVALIDATE;
1047 pci_write_config_word(dev, PCI_COMMAND, cmd);
1048 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 16);
1049 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
1050 L1_CACHE_BYTES >> 2);
1056 /* We power down some devices after they have been probed. They'll
1057 * be powered back on later on
1059 void __init pmac_pcibios_after_init(void)
1061 struct device_node* nd;
1063 #ifdef CONFIG_BLK_DEV_IDE
1064 struct pci_dev *dev = NULL;
1066 /* OF fails to initialize IDE controllers on macs
1067 * (and maybe other machines)
1069 * Ideally, this should be moved to the IDE layer, but we need
1070 * to check specifically with Andre Hedrick how to do it cleanly
1071 * since the common IDE code seem to care about the fact that the
1072 * BIOS may have disabled a controller.
1076 for_each_pci_dev(dev) {
1077 if ((dev->class >> 16) == PCI_BASE_CLASS_STORAGE)
1078 pci_enable_device(dev);
1080 #endif /* CONFIG_BLK_DEV_IDE */
1082 nd = find_devices("firewire");
1084 if (nd->parent && (device_is_compatible(nd, "pci106b,18") ||
1085 device_is_compatible(nd, "pci106b,30") ||
1086 device_is_compatible(nd, "pci11c1,5811"))
1087 && device_is_compatible(nd->parent, "uni-north")) {
1088 pmac_call_feature(PMAC_FTR_1394_ENABLE, nd, 0, 0);
1089 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, nd, 0, 0);
1093 nd = find_devices("ethernet");
1095 if (nd->parent && device_is_compatible(nd, "gmac")
1096 && device_is_compatible(nd->parent, "uni-north"))
1097 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, nd, 0, 0);
1103 void pmac_pci_fixup_cardbus(struct pci_dev* dev)
1105 if (_machine != _MACH_Pmac)
1108 * Fix the interrupt routing on the various cardbus bridges
1109 * used on powerbooks
1111 if (dev->vendor != PCI_VENDOR_ID_TI)
1113 if (dev->device == PCI_DEVICE_ID_TI_1130 ||
1114 dev->device == PCI_DEVICE_ID_TI_1131) {
1116 /* Enable PCI interrupt */
1117 if (pci_read_config_byte(dev, 0x91, &val) == 0)
1118 pci_write_config_byte(dev, 0x91, val | 0x30);
1119 /* Disable ISA interrupt mode */
1120 if (pci_read_config_byte(dev, 0x92, &val) == 0)
1121 pci_write_config_byte(dev, 0x92, val & ~0x06);
1123 if (dev->device == PCI_DEVICE_ID_TI_1210 ||
1124 dev->device == PCI_DEVICE_ID_TI_1211 ||
1125 dev->device == PCI_DEVICE_ID_TI_1410 ||
1126 dev->device == PCI_DEVICE_ID_TI_1510) {
1128 /* 0x8c == TI122X_IRQMUX, 2 says to route the INTA
1129 signal out the MFUNC0 pin */
1130 if (pci_read_config_byte(dev, 0x8c, &val) == 0)
1131 pci_write_config_byte(dev, 0x8c, (val & ~0x0f) | 2);
1132 /* Disable ISA interrupt mode */
1133 if (pci_read_config_byte(dev, 0x92, &val) == 0)
1134 pci_write_config_byte(dev, 0x92, val & ~0x06);
1138 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_ANY_ID, pmac_pci_fixup_cardbus);
1140 void pmac_pci_fixup_pciata(struct pci_dev* dev)
1145 * On PowerMacs, we try to switch any PCI ATA controller to
1148 if (_machine != _MACH_Pmac)
1150 /* Some controllers don't have the class IDE */
1151 if (dev->vendor == PCI_VENDOR_ID_PROMISE)
1152 switch(dev->device) {
1153 case PCI_DEVICE_ID_PROMISE_20246:
1154 case PCI_DEVICE_ID_PROMISE_20262:
1155 case PCI_DEVICE_ID_PROMISE_20263:
1156 case PCI_DEVICE_ID_PROMISE_20265:
1157 case PCI_DEVICE_ID_PROMISE_20267:
1158 case PCI_DEVICE_ID_PROMISE_20268:
1159 case PCI_DEVICE_ID_PROMISE_20269:
1160 case PCI_DEVICE_ID_PROMISE_20270:
1161 case PCI_DEVICE_ID_PROMISE_20271:
1162 case PCI_DEVICE_ID_PROMISE_20275:
1163 case PCI_DEVICE_ID_PROMISE_20276:
1164 case PCI_DEVICE_ID_PROMISE_20277:
1167 /* Others, check PCI class */
1168 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
1171 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1172 if ((progif & 5) != 5) {
1173 printk(KERN_INFO "Forcing PCI IDE into native mode: %s\n", pci_name(dev));
1174 (void) pci_write_config_byte(dev, PCI_CLASS_PROG, progif|5);
1175 if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) ||
1177 printk(KERN_ERR "Rewrite of PROGIF failed !\n");
1180 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pmac_pci_fixup_pciata);
1184 * Disable second function on K2-SATA, it's broken
1185 * and disable IO BARs on first one
1187 static void fixup_k2_sata(struct pci_dev* dev)
1192 if (PCI_FUNC(dev->devfn) > 0) {
1193 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1194 cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
1195 pci_write_config_word(dev, PCI_COMMAND, cmd);
1196 for (i = 0; i < 6; i++) {
1197 dev->resource[i].start = dev->resource[i].end = 0;
1198 dev->resource[i].flags = 0;
1199 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, 0);
1202 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1203 cmd &= ~PCI_COMMAND_IO;
1204 pci_write_config_word(dev, PCI_COMMAND, cmd);
1205 for (i = 0; i < 5; i++) {
1206 dev->resource[i].start = dev->resource[i].end = 0;
1207 dev->resource[i].flags = 0;
1208 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, 0);
1212 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 0x0240, fixup_k2_sata);