2 * arch/ppc/platforms/setup.c
4 * Copyright (C) 1995 Linus Torvalds
5 * Adapted from 'alpha' version by Gary Thomas
6 * Modified by Cort Dougan (cort@cs.nmt.edu)
10 * bootup setup stuff..
13 #include <linux/config.h>
14 #include <linux/errno.h>
15 #include <linux/sched.h>
16 #include <linux/kernel.h>
18 #include <linux/stddef.h>
19 #include <linux/unistd.h>
20 #include <linux/ptrace.h>
21 #include <linux/slab.h>
22 #include <linux/user.h>
23 #include <linux/a.out.h>
24 #include <linux/tty.h>
25 #include <linux/major.h>
26 #include <linux/interrupt.h>
27 #include <linux/reboot.h>
28 #include <linux/init.h>
29 #include <linux/pci.h>
30 #include <linux/version.h>
31 #include <linux/adb.h>
32 #include <linux/module.h>
33 #include <linux/delay.h>
34 #include <linux/ide.h>
35 #include <linux/console.h>
36 #include <linux/seq_file.h>
37 #include <linux/root_dev.h>
38 #include <linux/initrd.h>
39 #include <linux/module.h>
42 #include <asm/pgtable.h>
45 #include <asm/pci-bridge.h>
47 #include <asm/machdep.h>
49 #include <asm/hydra.h>
50 #include <asm/sections.h>
52 #include <asm/btext.h>
53 #include <asm/i8259.h>
58 void chrp_get_rtc_time(struct rtc_time *);
59 int chrp_set_rtc_time(struct rtc_time *);
60 void chrp_calibrate_decr(void);
61 long chrp_time_init(void);
63 void chrp_find_bridges(void);
64 void chrp_event_scan(void);
65 void rtas_indicator_progress(char *, unsigned short);
66 void btext_progress(char *, unsigned short);
69 EXPORT_SYMBOL(_chrp_type);
71 struct mpic *chrp_mpic;
74 * XXX this should be in xmon.h, but putting it there means xmon.h
75 * has to include <linux/interrupt.h> (to get irqreturn_t), which
76 * causes all sorts of problems. -- paulus
78 extern irqreturn_t xmon_irq(int, void *, struct pt_regs *);
80 extern unsigned long loops_per_jiffy;
83 extern struct smp_ops_t chrp_smp_ops;
86 static const char *gg2_memtypes[4] = {
87 "FPM", "SDRAM", "EDO", "BEDO"
89 static const char *gg2_cachesizes[4] = {
90 "256 KB", "512 KB", "1 MB", "Reserved"
92 static const char *gg2_cachetypes[4] = {
93 "Asynchronous", "Reserved", "Flow-Through Synchronous",
94 "Pipelined Synchronous"
96 static const char *gg2_cachemodes[4] = {
97 "Disabled", "Write-Through", "Copy-Back", "Transparent Mode"
100 void chrp_show_cpuinfo(struct seq_file *m)
104 struct device_node *root;
105 const char *model = "";
107 root = find_path_device("/");
109 model = get_property(root, "model", NULL);
110 seq_printf(m, "machine\t\t: CHRP %s\n", model);
112 /* longtrail (goldengate) stuff */
113 if (!strncmp(model, "IBM,LongTrail", 13)) {
114 /* VLSI VAS96011/12 `Golden Gate 2' */
116 sdramen = (in_le32(gg2_pci_config_base + GG2_PCI_DRAM_CTRL)
118 for (i = 0; i < (sdramen ? 4 : 6); i++) {
119 t = in_le32(gg2_pci_config_base+
124 switch ((t>>8) & 0x1f) {
147 seq_printf(m, "memory bank %d\t: %s %s\n", i, model,
148 gg2_memtypes[sdramen ? 1 : ((t>>1) & 3)]);
151 t = in_le32(gg2_pci_config_base+GG2_PCI_CC_CTRL);
152 seq_printf(m, "board l2\t: %s %s (%s)\n",
153 gg2_cachesizes[(t>>7) & 3],
154 gg2_cachetypes[(t>>2) & 3],
155 gg2_cachemodes[t & 3]);
160 * Fixes for the National Semiconductor PC78308VUL SuperI/O
162 * Some versions of Open Firmware incorrectly initialize the IRQ settings
163 * for keyboard and mouse
165 static inline void __init sio_write(u8 val, u8 index)
171 static inline u8 __init sio_read(u8 index)
177 static void __init sio_fixup_irq(const char *name, u8 device, u8 level,
180 u8 level0, type0, active;
182 /* select logical device */
183 sio_write(device, 0x07);
184 active = sio_read(0x30);
185 level0 = sio_read(0x70);
186 type0 = sio_read(0x71);
187 if (level0 != level || type0 != type || !active) {
188 printk(KERN_WARNING "sio: %s irq level %d, type %d, %sactive: "
189 "remapping to level %d, type %d, active\n",
190 name, level0, type0, !active ? "in" : "", level, type);
191 sio_write(0x01, 0x30);
192 sio_write(level, 0x70);
193 sio_write(type, 0x71);
197 static void __init sio_init(void)
199 struct device_node *root;
201 if ((root = find_path_device("/")) &&
202 !strncmp(get_property(root, "model", NULL), "IBM,LongTrail", 13)) {
203 /* logical device 0 (KBC/Keyboard) */
204 sio_fixup_irq("keyboard", 0, 1, 2);
205 /* select logical device 1 (KBC/Mouse) */
206 sio_fixup_irq("mouse", 1, 12, 2);
211 static void __init pegasos_set_l2cr(void)
213 struct device_node *np;
215 /* On Pegasos, enable the l2 cache if needed, as the OF forgets it */
216 if (_chrp_type != _CHRP_Pegasos)
219 /* Enable L2 cache if needed */
220 np = find_type_devices("cpu");
222 unsigned int *l2cr = (unsigned int *)
223 get_property (np, "l2cr", NULL);
225 printk ("Pegasos l2cr : no cpu l2cr property found\n");
228 if (!((*l2cr) & 0x80000000)) {
229 printk ("Pegasos l2cr : L2 cache was not active, "
232 _set_L2CR((*l2cr) | 0x80000000);
237 void __init chrp_setup_arch(void)
239 struct device_node *root = find_path_device ("/");
240 char *machine = NULL;
241 struct device_node *device;
242 unsigned int *p = NULL;
244 /* init to some ~sane value until calibrate_delay() runs */
245 loops_per_jiffy = 50000000/HZ;
248 machine = get_property(root, "model", NULL);
249 if (machine && strncmp(machine, "Pegasos", 7) == 0) {
250 _chrp_type = _CHRP_Pegasos;
251 } else if (machine && strncmp(machine, "IBM", 3) == 0) {
252 _chrp_type = _CHRP_IBM;
253 } else if (machine && strncmp(machine, "MOT", 3) == 0) {
254 _chrp_type = _CHRP_Motorola;
256 /* Let's assume it is an IBM chrp if all else fails */
257 _chrp_type = _CHRP_IBM;
259 printk("chrp type = %x\n", _chrp_type);
262 if (rtas_token("display-character") >= 0)
263 ppc_md.progress = rtas_progress;
265 #ifdef CONFIG_BOOTX_TEXT
266 if (ppc_md.progress == NULL && boot_text_mapped)
267 ppc_md.progress = btext_progress;
270 #ifdef CONFIG_BLK_DEV_INITRD
271 /* this is fine for chrp */
272 initrd_below_start_ok = 1;
275 ROOT_DEV = Root_RAM0;
278 ROOT_DEV = Root_SDA2; /* sda2 (sda1 is for the kernel) */
280 /* On pegasos, enable the L2 cache if not already done by OF */
283 /* Lookup PCI host bridges */
287 * Temporary fixes for PCI devices.
290 hydra_init(); /* Mac I/O */
293 * Fix the Super I/O configuration
297 /* Get the event scan rate for the rtas so we know how
298 * often it expects a heartbeat. -- Cort
300 device = find_devices("rtas");
302 p = (unsigned int *) get_property
303 (device, "rtas-event-scan-rate", NULL);
305 ppc_md.heartbeat = chrp_event_scan;
306 ppc_md.heartbeat_reset = HZ / (*p * 30) - 1;
307 ppc_md.heartbeat_count = 1;
308 printk("RTAS Event Scan Rate: %u (%lu jiffies)\n",
309 *p, ppc_md.heartbeat_reset);
312 pci_create_OF_bus_map();
315 * Print the banner, then scroll down so boot progress
316 * can be printed. -- Cort
318 if (ppc_md.progress) ppc_md.progress("Linux/PPC "UTS_RELEASE"\n", 0x0);
322 chrp_event_scan(void)
324 unsigned char log[1024];
327 /* XXX: we should loop until the hardware says no more error logs -- Cort */
328 rtas_call(rtas_token("event-scan"), 4, 1, &ret, 0xffffffff, 0,
330 ppc_md.heartbeat_count = ppc_md.heartbeat_reset;
334 * Finds the open-pic node and sets up the mpic driver.
336 static void __init chrp_find_openpic(void)
338 struct device_node *np, *root;
339 int len, i, j, irq_count;
340 int isu_size, idu_size;
341 unsigned int *iranges, *opprop = NULL;
343 unsigned long opaddr;
345 unsigned char init_senses[NR_IRQS - NUM_8259_INTERRUPTS];
347 np = find_type_devices("open-pic");
350 root = find_path_device("/");
352 opprop = (unsigned int *) get_property
353 (root, "platform-open-pic", &oplen);
354 na = prom_n_addr_cells(root);
356 if (opprop && oplen >= na * sizeof(unsigned int)) {
357 opaddr = opprop[na-1]; /* assume 32-bit */
358 oplen /= na * sizeof(unsigned int);
360 if (np->n_addrs == 0)
362 opaddr = np->addrs[0].address;
366 printk(KERN_INFO "OpenPIC at %lx\n", opaddr);
368 irq_count = NR_IRQS - NUM_ISA_INTERRUPTS - 4; /* leave room for IPIs */
369 prom_get_irq_senses(init_senses, NUM_8259_INTERRUPTS, NR_IRQS - 4);
371 iranges = (unsigned int *) get_property(np, "interrupt-ranges", &len);
373 len = 0; /* non-distributed mpic */
375 len /= 2 * sizeof(unsigned int);
378 * The first pair of cells in interrupt-ranges refers to the
379 * IDU; subsequent pairs refer to the ISUs.
382 printk(KERN_ERR "Insufficient addresses for distributed"
383 " OpenPIC (%d < %d)\n", np->n_addrs, len);
389 if (len > 0 && iranges[1] != 0) {
390 printk(KERN_INFO "OpenPIC irqs %d..%d in IDU\n",
391 iranges[0], iranges[0] + iranges[1] - 1);
392 idu_size = iranges[1];
395 isu_size = iranges[3];
397 chrp_mpic = mpic_alloc(opaddr, MPIC_PRIMARY,
398 isu_size, NUM_ISA_INTERRUPTS, irq_count,
399 NR_IRQS - 4, init_senses, irq_count,
401 if (chrp_mpic == NULL) {
402 printk(KERN_ERR "Failed to allocate MPIC structure\n");
407 for (i = 1; i < len; ++i) {
410 printk(KERN_INFO "OpenPIC irqs %d..%d in ISU at %x\n",
411 iranges[0], iranges[0] + iranges[1] - 1,
413 mpic_assign_isu(chrp_mpic, i - 1, opprop[j]);
416 mpic_init(chrp_mpic);
417 mpic_setup_cascade(NUM_ISA_INTERRUPTS, i8259_irq_cascade, NULL);
420 #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
421 static struct irqaction xmon_irqaction = {
423 .mask = CPU_MASK_NONE,
424 .name = "XMON break",
428 void __init chrp_init_IRQ(void)
430 struct device_node *np;
431 unsigned long chrp_int_ack = 0;
432 #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
433 struct device_node *kbd;
436 for (np = find_devices("pci"); np != NULL; np = np->next) {
437 unsigned int *addrp = (unsigned int *)
438 get_property(np, "8259-interrupt-acknowledge", NULL);
442 chrp_int_ack = addrp[prom_n_addr_cells(np)-1];
446 printk(KERN_ERR "Cannot find PCI interrupt acknowledge address\n");
450 i8259_init(chrp_int_ack, 0);
452 if (_chrp_type == _CHRP_Pegasos)
453 ppc_md.get_irq = i8259_irq;
455 ppc_md.get_irq = mpic_get_irq;
457 #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
458 /* see if there is a keyboard in the device tree
459 with a parent of type "adb" */
460 for (kbd = find_devices("keyboard"); kbd; kbd = kbd->next)
461 if (kbd->parent && kbd->parent->type
462 && strcmp(kbd->parent->type, "adb") == 0)
465 setup_irq(HYDRA_INT_ADB_NMI, &xmon_irqaction);
472 request_region(0x20,0x20,"pic1");
473 request_region(0xa0,0x20,"pic2");
474 request_region(0x00,0x20,"dma1");
475 request_region(0x40,0x20,"timer");
476 request_region(0x80,0x10,"dma page reg");
477 request_region(0xc0,0x20,"dma2");
480 ppc_md.progress(" Have fun! ", 0x7777);
483 void __init chrp_init(void)
485 ISA_DMA_THRESHOLD = ~0L;
486 DMA_MODE_READ = 0x44;
487 DMA_MODE_WRITE = 0x48;
488 isa_io_base = CHRP_ISA_IO_BASE; /* default value */
489 ppc_do_canonicalize_irqs = 1;
491 /* Assume we have an 8259... */
492 __irq_offset_value = NUM_ISA_INTERRUPTS;
494 ppc_md.setup_arch = chrp_setup_arch;
495 ppc_md.show_cpuinfo = chrp_show_cpuinfo;
497 ppc_md.init_IRQ = chrp_init_IRQ;
498 ppc_md.init = chrp_init2;
500 ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;
502 ppc_md.restart = rtas_restart;
503 ppc_md.power_off = rtas_power_off;
504 ppc_md.halt = rtas_halt;
506 ppc_md.time_init = chrp_time_init;
507 ppc_md.set_rtc_time = chrp_set_rtc_time;
508 ppc_md.get_rtc_time = chrp_get_rtc_time;
509 ppc_md.calibrate_decr = chrp_calibrate_decr;
512 smp_ops = &chrp_smp_ops;
513 #endif /* CONFIG_SMP */
516 #ifdef CONFIG_BOOTX_TEXT
518 btext_progress(char *s, unsigned short hex)
521 btext_drawstring("\n");
523 #endif /* CONFIG_BOOTX_TEXT */