2 * Copyright 2007, Michael Ellerman, IBM Corporation.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
11 #include <linux/interrupt.h>
12 #include <linux/irq.h>
13 #include <linux/kernel.h>
14 #include <linux/pci.h>
15 #include <linux/msi.h>
16 #include <linux/of_platform.h>
19 #include <asm/machdep.h>
24 * MSIC registers, specified as offsets from dcr_base
26 #define MSIC_CTRL_REG 0x0
28 /* Base Address registers specify FIFO location in BE memory */
29 #define MSIC_BASE_ADDR_HI_REG 0x3
30 #define MSIC_BASE_ADDR_LO_REG 0x4
32 /* Hold the read/write offsets into the FIFO */
33 #define MSIC_READ_OFFSET_REG 0x5
34 #define MSIC_WRITE_OFFSET_REG 0x6
37 /* MSIC control register flags */
38 #define MSIC_CTRL_ENABLE 0x0001
39 #define MSIC_CTRL_FIFO_FULL_ENABLE 0x0002
40 #define MSIC_CTRL_IRQ_ENABLE 0x0008
41 #define MSIC_CTRL_FULL_STOP_ENABLE 0x0010
44 * The MSIC can be configured to use a FIFO of 32KB, 64KB, 128KB or 256KB.
45 * Currently we're using a 64KB FIFO size.
47 #define MSIC_FIFO_SIZE_SHIFT 16
48 #define MSIC_FIFO_SIZE_BYTES (1 << MSIC_FIFO_SIZE_SHIFT)
51 * To configure the FIFO size as (1 << n) bytes, we write (n - 15) into bits
52 * 8-9 of the MSIC control reg.
54 #define MSIC_CTRL_FIFO_SIZE (((MSIC_FIFO_SIZE_SHIFT - 15) << 8) & 0x300)
57 * We need to mask the read/write offsets to make sure they stay within
58 * the bounds of the FIFO. Also they should always be 16-byte aligned.
60 #define MSIC_FIFO_SIZE_MASK ((MSIC_FIFO_SIZE_BYTES - 1) & ~0xFu)
62 /* Each entry in the FIFO is 16 bytes, the first 4 bytes hold the irq # */
63 #define MSIC_FIFO_ENTRY_SIZE 0x10
67 struct irq_host *irq_host;
73 static void msic_dcr_write(struct axon_msic *msic, unsigned int dcr_n, u32 val)
75 pr_debug("axon_msi: dcr_write(0x%x, 0x%x)\n", val, dcr_n);
77 dcr_write(msic->dcr_host, dcr_n, val);
80 static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc)
82 struct axon_msic *msic = get_irq_data(irq);
83 u32 write_offset, msi;
86 write_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG);
87 pr_debug("axon_msi: original write_offset 0x%x\n", write_offset);
89 /* write_offset doesn't wrap properly, so we have to mask it */
90 write_offset &= MSIC_FIFO_SIZE_MASK;
92 while (msic->read_offset != write_offset) {
93 idx = msic->read_offset / sizeof(__le32);
94 msi = le32_to_cpu(msic->fifo[idx]);
97 pr_debug("axon_msi: woff %x roff %x msi %x\n",
98 write_offset, msic->read_offset, msi);
100 msic->read_offset += MSIC_FIFO_ENTRY_SIZE;
101 msic->read_offset &= MSIC_FIFO_SIZE_MASK;
103 if (msi < NR_IRQS && irq_map[msi].host == msic->irq_host)
104 generic_handle_irq(msi);
106 pr_debug("axon_msi: invalid irq 0x%x!\n", msi);
109 desc->chip->eoi(irq);
112 static struct axon_msic *find_msi_translator(struct pci_dev *dev)
114 struct irq_host *irq_host;
115 struct device_node *dn, *tmp;
117 struct axon_msic *msic = NULL;
119 dn = of_node_get(pci_device_to_OF_node(dev));
121 dev_dbg(&dev->dev, "axon_msi: no pci_dn found\n");
125 for (; dn; tmp = of_get_parent(dn), of_node_put(dn), dn = tmp) {
126 ph = of_get_property(dn, "msi-translator", NULL);
133 "axon_msi: no msi-translator property found\n");
138 dn = of_find_node_by_phandle(*ph);
141 "axon_msi: msi-translator doesn't point to a node\n");
145 irq_host = irq_find_host(dn);
147 dev_dbg(&dev->dev, "axon_msi: no irq_host found for node %s\n",
152 msic = irq_host->host_data;
161 static int axon_msi_check_device(struct pci_dev *dev, int nvec, int type)
163 if (!find_msi_translator(dev))
169 static int setup_msi_msg_address(struct pci_dev *dev, struct msi_msg *msg)
171 struct device_node *dn, *tmp;
172 struct msi_desc *entry;
176 dn = of_node_get(pci_device_to_OF_node(dev));
178 dev_dbg(&dev->dev, "axon_msi: no pci_dn found\n");
182 entry = list_first_entry(&dev->msi_list, struct msi_desc, list);
184 for (; dn; tmp = of_get_parent(dn), of_node_put(dn), dn = tmp) {
185 if (entry->msi_attrib.is_64) {
186 prop = of_get_property(dn, "msi-address-64", &len);
191 prop = of_get_property(dn, "msi-address-32", &len);
198 "axon_msi: no msi-address-(32|64) properties found\n");
204 msg->address_hi = prop[0];
205 msg->address_lo = prop[1];
209 msg->address_lo = prop[0];
213 "axon_msi: malformed msi-address-(32|64) property\n");
223 static int axon_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
225 unsigned int virq, rc;
226 struct msi_desc *entry;
228 struct axon_msic *msic;
230 msic = find_msi_translator(dev);
234 rc = setup_msi_msg_address(dev, &msg);
238 /* We rely on being able to stash a virq in a u16 */
239 BUILD_BUG_ON(NR_IRQS > 65536);
241 list_for_each_entry(entry, &dev->msi_list, list) {
242 virq = irq_create_direct_mapping(msic->irq_host);
243 if (virq == NO_IRQ) {
245 "axon_msi: virq allocation failed!\n");
248 dev_dbg(&dev->dev, "axon_msi: allocated virq 0x%x\n", virq);
250 set_irq_msi(virq, entry);
252 write_msi_msg(virq, &msg);
258 static void axon_msi_teardown_msi_irqs(struct pci_dev *dev)
260 struct msi_desc *entry;
262 dev_dbg(&dev->dev, "axon_msi: tearing down msi irqs\n");
264 list_for_each_entry(entry, &dev->msi_list, list) {
265 if (entry->irq == NO_IRQ)
268 set_irq_msi(entry->irq, NULL);
269 irq_dispose_mapping(entry->irq);
273 static struct irq_chip msic_irq_chip = {
274 .mask = mask_msi_irq,
275 .unmask = unmask_msi_irq,
276 .shutdown = unmask_msi_irq,
277 .typename = "AXON-MSI",
280 static int msic_host_map(struct irq_host *h, unsigned int virq,
283 set_irq_chip_and_handler(virq, &msic_irq_chip, handle_simple_irq);
288 static struct irq_host_ops msic_host_ops = {
289 .map = msic_host_map,
292 static int axon_msi_shutdown(struct of_device *device)
294 struct axon_msic *msic = device->dev.platform_data;
297 pr_debug("axon_msi: disabling %s\n",
298 msic->irq_host->of_node->full_name);
299 tmp = dcr_read(msic->dcr_host, MSIC_CTRL_REG);
300 tmp &= ~MSIC_CTRL_ENABLE & ~MSIC_CTRL_IRQ_ENABLE;
301 msic_dcr_write(msic, MSIC_CTRL_REG, tmp);
306 static int axon_msi_probe(struct of_device *device,
307 const struct of_device_id *device_id)
310 struct device_node *dn = device->node;
311 struct axon_msic *msic;
313 int dcr_base, dcr_len;
315 pr_debug("axon_msi: setting up dn %s\n", dn->full_name);
317 msic = kzalloc(sizeof(struct axon_msic), GFP_KERNEL);
319 printk(KERN_ERR "axon_msi: couldn't allocate msic for %s\n",
324 dcr_base = dcr_resource_start(dn, 0);
325 dcr_len = dcr_resource_len(dn, 0);
327 if (dcr_base == 0 || dcr_len == 0) {
329 "axon_msi: couldn't parse dcr properties on %s\n",
334 msic->dcr_host = dcr_map(dn, dcr_base, dcr_len);
335 if (!DCR_MAP_OK(msic->dcr_host)) {
336 printk(KERN_ERR "axon_msi: dcr_map failed for %s\n",
341 page = alloc_pages_node(of_node_to_nid(dn), GFP_KERNEL,
342 get_order(MSIC_FIFO_SIZE_BYTES));
344 printk(KERN_ERR "axon_msi: couldn't allocate fifo for %s\n",
349 msic->fifo = page_address(page);
351 msic->irq_host = irq_alloc_host(of_node_get(dn), IRQ_HOST_MAP_NOMAP,
352 NR_IRQS, &msic_host_ops, 0);
353 if (!msic->irq_host) {
354 printk(KERN_ERR "axon_msi: couldn't allocate irq_host for %s\n",
359 msic->irq_host->host_data = msic;
361 virq = irq_of_parse_and_map(dn, 0);
362 if (virq == NO_IRQ) {
363 printk(KERN_ERR "axon_msi: irq parse and map failed for %s\n",
368 set_irq_data(virq, msic);
369 set_irq_chained_handler(virq, axon_msi_cascade);
370 pr_debug("axon_msi: irq 0x%x setup for axon_msi\n", virq);
372 /* Enable the MSIC hardware */
373 msic_dcr_write(msic, MSIC_BASE_ADDR_HI_REG, (u64)msic->fifo >> 32);
374 msic_dcr_write(msic, MSIC_BASE_ADDR_LO_REG,
375 (u64)msic->fifo & 0xFFFFFFFF);
376 msic_dcr_write(msic, MSIC_CTRL_REG,
377 MSIC_CTRL_IRQ_ENABLE | MSIC_CTRL_ENABLE |
378 MSIC_CTRL_FIFO_SIZE);
380 device->dev.platform_data = msic;
382 ppc_md.setup_msi_irqs = axon_msi_setup_msi_irqs;
383 ppc_md.teardown_msi_irqs = axon_msi_teardown_msi_irqs;
384 ppc_md.msi_check_device = axon_msi_check_device;
386 printk(KERN_DEBUG "axon_msi: setup MSIC on %s\n", dn->full_name);
391 kfree(msic->irq_host);
393 __free_pages(virt_to_page(msic->fifo), get_order(MSIC_FIFO_SIZE_BYTES));
401 static const struct of_device_id axon_msi_device_id[] = {
403 .compatible = "ibm,axon-msic"
408 static struct of_platform_driver axon_msi_driver = {
409 .match_table = axon_msi_device_id,
410 .probe = axon_msi_probe,
411 .shutdown = axon_msi_shutdown,
417 static int __init axon_msi_init(void)
419 return of_register_platform_driver(&axon_msi_driver);
421 subsys_initcall(axon_msi_init);