2 * Copyright 2007, Michael Ellerman, IBM Corporation.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
11 #include <linux/interrupt.h>
12 #include <linux/irq.h>
13 #include <linux/kernel.h>
14 #include <linux/pci.h>
15 #include <linux/msi.h>
16 #include <linux/reboot.h>
19 #include <asm/machdep.h>
24 * MSIC registers, specified as offsets from dcr_base
26 #define MSIC_CTRL_REG 0x0
28 /* Base Address registers specify FIFO location in BE memory */
29 #define MSIC_BASE_ADDR_HI_REG 0x3
30 #define MSIC_BASE_ADDR_LO_REG 0x4
32 /* Hold the read/write offsets into the FIFO */
33 #define MSIC_READ_OFFSET_REG 0x5
34 #define MSIC_WRITE_OFFSET_REG 0x6
37 /* MSIC control register flags */
38 #define MSIC_CTRL_ENABLE 0x0001
39 #define MSIC_CTRL_FIFO_FULL_ENABLE 0x0002
40 #define MSIC_CTRL_IRQ_ENABLE 0x0008
41 #define MSIC_CTRL_FULL_STOP_ENABLE 0x0010
44 * The MSIC can be configured to use a FIFO of 32KB, 64KB, 128KB or 256KB.
45 * Currently we're using a 64KB FIFO size.
47 #define MSIC_FIFO_SIZE_SHIFT 16
48 #define MSIC_FIFO_SIZE_BYTES (1 << MSIC_FIFO_SIZE_SHIFT)
51 * To configure the FIFO size as (1 << n) bytes, we write (n - 15) into bits
52 * 8-9 of the MSIC control reg.
54 #define MSIC_CTRL_FIFO_SIZE (((MSIC_FIFO_SIZE_SHIFT - 15) << 8) & 0x300)
57 * We need to mask the read/write offsets to make sure they stay within
58 * the bounds of the FIFO. Also they should always be 16-byte aligned.
60 #define MSIC_FIFO_SIZE_MASK ((MSIC_FIFO_SIZE_BYTES - 1) & ~0xFu)
62 /* Each entry in the FIFO is 16 bytes, the first 4 bytes hold the irq # */
63 #define MSIC_FIFO_ENTRY_SIZE 0x10
67 struct irq_host *irq_host;
70 struct list_head list;
75 static LIST_HEAD(axon_msic_list);
77 static void msic_dcr_write(struct axon_msic *msic, unsigned int dcr_n, u32 val)
79 pr_debug("axon_msi: dcr_write(0x%x, 0x%x)\n", val, dcr_n);
81 dcr_write(msic->dcr_host, msic->dcr_base + dcr_n, val);
84 static u32 msic_dcr_read(struct axon_msic *msic, unsigned int dcr_n)
86 return dcr_read(msic->dcr_host, msic->dcr_base + dcr_n);
89 static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc)
91 struct axon_msic *msic = get_irq_data(irq);
92 u32 write_offset, msi;
95 write_offset = msic_dcr_read(msic, MSIC_WRITE_OFFSET_REG);
96 pr_debug("axon_msi: original write_offset 0x%x\n", write_offset);
98 /* write_offset doesn't wrap properly, so we have to mask it */
99 write_offset &= MSIC_FIFO_SIZE_MASK;
101 while (msic->read_offset != write_offset) {
102 idx = msic->read_offset / sizeof(__le32);
103 msi = le32_to_cpu(msic->fifo[idx]);
106 pr_debug("axon_msi: woff %x roff %x msi %x\n",
107 write_offset, msic->read_offset, msi);
109 msic->read_offset += MSIC_FIFO_ENTRY_SIZE;
110 msic->read_offset &= MSIC_FIFO_SIZE_MASK;
112 if (msi < NR_IRQS && irq_map[msi].host == msic->irq_host)
113 generic_handle_irq(msi);
115 pr_debug("axon_msi: invalid irq 0x%x!\n", msi);
118 desc->chip->eoi(irq);
121 static struct axon_msic *find_msi_translator(struct pci_dev *dev)
123 struct irq_host *irq_host;
124 struct device_node *dn, *tmp;
126 struct axon_msic *msic = NULL;
128 dn = pci_device_to_OF_node(dev);
130 dev_dbg(&dev->dev, "axon_msi: no pci_dn found\n");
134 for (; dn; tmp = of_get_parent(dn), of_node_put(dn), dn = tmp) {
135 ph = of_get_property(dn, "msi-translator", NULL);
142 "axon_msi: no msi-translator property found\n");
147 dn = of_find_node_by_phandle(*ph);
150 "axon_msi: msi-translator doesn't point to a node\n");
154 irq_host = irq_find_host(dn);
156 dev_dbg(&dev->dev, "axon_msi: no irq_host found for node %s\n",
161 msic = irq_host->host_data;
170 static int axon_msi_check_device(struct pci_dev *dev, int nvec, int type)
172 if (!find_msi_translator(dev))
178 static int setup_msi_msg_address(struct pci_dev *dev, struct msi_msg *msg)
180 struct device_node *dn, *tmp;
181 struct msi_desc *entry;
185 dn = pci_device_to_OF_node(dev);
187 dev_dbg(&dev->dev, "axon_msi: no pci_dn found\n");
191 entry = list_first_entry(&dev->msi_list, struct msi_desc, list);
193 for (; dn; tmp = of_get_parent(dn), of_node_put(dn), dn = tmp) {
194 if (entry->msi_attrib.is_64) {
195 prop = of_get_property(dn, "msi-address-64", &len);
200 prop = of_get_property(dn, "msi-address-32", &len);
207 "axon_msi: no msi-address-(32|64) properties found\n");
213 msg->address_hi = prop[0];
214 msg->address_lo = prop[1];
218 msg->address_lo = prop[0];
222 "axon_msi: malformed msi-address-(32|64) property\n");
232 static int axon_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
234 unsigned int virq, rc;
235 struct msi_desc *entry;
237 struct axon_msic *msic;
239 msic = find_msi_translator(dev);
243 rc = setup_msi_msg_address(dev, &msg);
247 /* We rely on being able to stash a virq in a u16 */
248 BUILD_BUG_ON(NR_IRQS > 65536);
250 list_for_each_entry(entry, &dev->msi_list, list) {
251 virq = irq_create_direct_mapping(msic->irq_host);
252 if (virq == NO_IRQ) {
254 "axon_msi: virq allocation failed!\n");
257 dev_dbg(&dev->dev, "axon_msi: allocated virq 0x%x\n", virq);
259 set_irq_msi(virq, entry);
261 write_msi_msg(virq, &msg);
267 static void axon_msi_teardown_msi_irqs(struct pci_dev *dev)
269 struct msi_desc *entry;
271 dev_dbg(&dev->dev, "axon_msi: tearing down msi irqs\n");
273 list_for_each_entry(entry, &dev->msi_list, list) {
274 if (entry->irq == NO_IRQ)
277 set_irq_msi(entry->irq, NULL);
278 irq_dispose_mapping(entry->irq);
282 static struct irq_chip msic_irq_chip = {
283 .mask = mask_msi_irq,
284 .unmask = unmask_msi_irq,
285 .shutdown = unmask_msi_irq,
286 .typename = "AXON-MSI",
289 static int msic_host_map(struct irq_host *h, unsigned int virq,
292 set_irq_chip_and_handler(virq, &msic_irq_chip, handle_simple_irq);
297 static struct irq_host_ops msic_host_ops = {
298 .map = msic_host_map,
301 static int axon_msi_notify_reboot(struct notifier_block *nb,
302 unsigned long code, void *data)
304 struct axon_msic *msic;
307 list_for_each_entry(msic, &axon_msic_list, list) {
308 pr_debug("axon_msi: disabling %s\n",
309 msic->irq_host->of_node->full_name);
310 tmp = msic_dcr_read(msic, MSIC_CTRL_REG);
311 tmp &= ~MSIC_CTRL_ENABLE & ~MSIC_CTRL_IRQ_ENABLE;
312 msic_dcr_write(msic, MSIC_CTRL_REG, tmp);
318 static struct notifier_block axon_msi_reboot_notifier = {
319 .notifier_call = axon_msi_notify_reboot
322 static int axon_msi_setup_one(struct device_node *dn)
325 struct axon_msic *msic;
329 pr_debug("axon_msi: setting up dn %s\n", dn->full_name);
331 msic = kzalloc(sizeof(struct axon_msic), GFP_KERNEL);
333 printk(KERN_ERR "axon_msi: couldn't allocate msic for %s\n",
338 msic->dcr_base = dcr_resource_start(dn, 0);
339 dcr_len = dcr_resource_len(dn, 0);
341 if (msic->dcr_base == 0 || dcr_len == 0) {
343 "axon_msi: couldn't parse dcr properties on %s\n",
348 msic->dcr_host = dcr_map(dn, msic->dcr_base, dcr_len);
349 if (!DCR_MAP_OK(msic->dcr_host)) {
350 printk(KERN_ERR "axon_msi: dcr_map failed for %s\n",
355 page = alloc_pages_node(of_node_to_nid(dn), GFP_KERNEL,
356 get_order(MSIC_FIFO_SIZE_BYTES));
358 printk(KERN_ERR "axon_msi: couldn't allocate fifo for %s\n",
363 msic->fifo = page_address(page);
365 msic->irq_host = irq_alloc_host(of_node_get(dn), IRQ_HOST_MAP_NOMAP,
366 NR_IRQS, &msic_host_ops, 0);
367 if (!msic->irq_host) {
368 printk(KERN_ERR "axon_msi: couldn't allocate irq_host for %s\n",
373 msic->irq_host->host_data = msic;
375 virq = irq_of_parse_and_map(dn, 0);
376 if (virq == NO_IRQ) {
377 printk(KERN_ERR "axon_msi: irq parse and map failed for %s\n",
382 set_irq_data(virq, msic);
383 set_irq_chained_handler(virq, axon_msi_cascade);
384 pr_debug("axon_msi: irq 0x%x setup for axon_msi\n", virq);
386 /* Enable the MSIC hardware */
387 msic_dcr_write(msic, MSIC_BASE_ADDR_HI_REG, (u64)msic->fifo >> 32);
388 msic_dcr_write(msic, MSIC_BASE_ADDR_LO_REG,
389 (u64)msic->fifo & 0xFFFFFFFF);
390 msic_dcr_write(msic, MSIC_CTRL_REG,
391 MSIC_CTRL_IRQ_ENABLE | MSIC_CTRL_ENABLE |
392 MSIC_CTRL_FIFO_SIZE);
394 list_add(&msic->list, &axon_msic_list);
396 printk(KERN_DEBUG "axon_msi: setup MSIC on %s\n", dn->full_name);
401 kfree(msic->irq_host);
403 __free_pages(virt_to_page(msic->fifo), get_order(MSIC_FIFO_SIZE_BYTES));
411 static int axon_msi_init(void)
413 struct device_node *dn;
416 pr_debug("axon_msi: initialising ...\n");
418 for_each_compatible_node(dn, NULL, "ibm,axon-msic") {
419 if (axon_msi_setup_one(dn) == 0)
424 ppc_md.setup_msi_irqs = axon_msi_setup_msi_irqs;
425 ppc_md.teardown_msi_irqs = axon_msi_teardown_msi_irqs;
426 ppc_md.msi_check_device = axon_msi_check_device;
428 register_reboot_notifier(&axon_msi_reboot_notifier);
430 pr_debug("axon_msi: registered callbacks!\n");
435 arch_initcall(axon_msi_init);