2 * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
4 * Authors: Shlomi Gridish <gridish@freescale.com>
5 * Li Yang <leoli@freescale.com>
8 * QUICC Engine (QE) external definitions and structure.
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
15 #ifndef _ASM_POWERPC_QE_H
16 #define _ASM_POWERPC_QE_H
19 #include <linux/spinlock.h>
20 #include <linux/errno.h>
21 #include <linux/err.h>
23 #include <asm/immap_qe.h>
25 #define QE_NUM_OF_SNUM 256 /* There are 256 serial number in QE */
26 #define QE_NUM_OF_BRGS 16
27 #define QE_NUM_OF_PORTS 1024
31 #define MEM_PART_SYSTEM 0
32 #define MEM_PART_SECONDARY 1
33 #define MEM_PART_MURAM 2
38 QE_BRG1, /* Baud Rate Generator 1 */
39 QE_BRG2, /* Baud Rate Generator 2 */
40 QE_BRG3, /* Baud Rate Generator 3 */
41 QE_BRG4, /* Baud Rate Generator 4 */
42 QE_BRG5, /* Baud Rate Generator 5 */
43 QE_BRG6, /* Baud Rate Generator 6 */
44 QE_BRG7, /* Baud Rate Generator 7 */
45 QE_BRG8, /* Baud Rate Generator 8 */
46 QE_BRG9, /* Baud Rate Generator 9 */
47 QE_BRG10, /* Baud Rate Generator 10 */
48 QE_BRG11, /* Baud Rate Generator 11 */
49 QE_BRG12, /* Baud Rate Generator 12 */
50 QE_BRG13, /* Baud Rate Generator 13 */
51 QE_BRG14, /* Baud Rate Generator 14 */
52 QE_BRG15, /* Baud Rate Generator 15 */
53 QE_BRG16, /* Baud Rate Generator 16 */
54 QE_CLK1, /* Clock 1 */
55 QE_CLK2, /* Clock 2 */
56 QE_CLK3, /* Clock 3 */
57 QE_CLK4, /* Clock 4 */
58 QE_CLK5, /* Clock 5 */
59 QE_CLK6, /* Clock 6 */
60 QE_CLK7, /* Clock 7 */
61 QE_CLK8, /* Clock 8 */
62 QE_CLK9, /* Clock 9 */
63 QE_CLK10, /* Clock 10 */
64 QE_CLK11, /* Clock 11 */
65 QE_CLK12, /* Clock 12 */
66 QE_CLK13, /* Clock 13 */
67 QE_CLK14, /* Clock 14 */
68 QE_CLK15, /* Clock 15 */
69 QE_CLK16, /* Clock 16 */
70 QE_CLK17, /* Clock 17 */
71 QE_CLK18, /* Clock 18 */
72 QE_CLK19, /* Clock 19 */
73 QE_CLK20, /* Clock 20 */
74 QE_CLK21, /* Clock 21 */
75 QE_CLK22, /* Clock 22 */
76 QE_CLK23, /* Clock 23 */
77 QE_CLK24, /* Clock 24 */
81 static inline bool qe_clock_is_brg(enum qe_clock clk)
83 return clk >= QE_BRG1 && clk <= QE_BRG16;
86 extern spinlock_t cmxgcr_lock;
88 /* Export QE common operations */
89 #ifdef CONFIG_QUICC_ENGINE
90 extern void qe_reset(void);
92 static inline void qe_reset(void) {}
96 #define QE_PIO_PINS 32
99 __be32 cpodr; /* Open drain register */
100 __be32 cpdata; /* Data register */
101 __be32 cpdir1; /* Direction register */
102 __be32 cpdir2; /* Direction register */
103 __be32 cppar1; /* Pin assignment register */
104 __be32 cppar2; /* Pin assignment register */
105 #ifdef CONFIG_PPC_85xx
110 #define QE_PIO_DIR_IN 2
111 #define QE_PIO_DIR_OUT 1
112 extern void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin,
113 int dir, int open_drain, int assignment,
115 #ifdef CONFIG_QUICC_ENGINE
116 extern int par_io_init(struct device_node *np);
117 extern int par_io_of_config(struct device_node *np);
118 extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
119 int assignment, int has_irq);
120 extern int par_io_data_set(u8 port, u8 pin, u8 val);
122 static inline int par_io_init(struct device_node *np) { return -ENOSYS; }
123 static inline int par_io_of_config(struct device_node *np) { return -ENOSYS; }
124 static inline int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
125 int assignment, int has_irq) { return -ENOSYS; }
126 static inline int par_io_data_set(u8 port, u8 pin, u8 val) { return -ENOSYS; }
127 #endif /* CONFIG_QUICC_ENGINE */
130 * Pin multiplexing functions.
133 #ifdef CONFIG_QE_GPIO
134 extern struct qe_pin *qe_pin_request(struct device_node *np, int index);
135 extern void qe_pin_free(struct qe_pin *qe_pin);
136 extern void qe_pin_set_gpio(struct qe_pin *qe_pin);
137 extern void qe_pin_set_dedicated(struct qe_pin *pin);
139 static inline struct qe_pin *qe_pin_request(struct device_node *np, int index)
141 return ERR_PTR(-ENOSYS);
143 static inline void qe_pin_free(struct qe_pin *qe_pin) {}
144 static inline void qe_pin_set_gpio(struct qe_pin *qe_pin) {}
145 static inline void qe_pin_set_dedicated(struct qe_pin *pin) {}
146 #endif /* CONFIG_QE_GPIO */
148 /* QE internal API */
149 int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input);
150 enum qe_clock qe_clock_source(const char *source);
151 unsigned int qe_get_brg_clk(void);
152 int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier);
153 int qe_get_snum(void);
154 void qe_put_snum(u8 snum);
155 unsigned int qe_get_num_of_risc(void);
156 unsigned int qe_get_num_of_snums(void);
158 static inline int qe_alive_during_sleep(void)
161 * MPC8568E reference manual says:
163 * "...power down sequence waits for all I/O interfaces to become idle.
164 * In some applications this may happen eventually without actively
165 * shutting down interfaces, but most likely, software will have to
166 * take steps to shut down the eTSEC, QUICC Engine Block, and PCI
167 * interfaces before issuing the command (either the write to the core
168 * MSR[WE] as described above or writing to POWMGTCSR) to put the
169 * device into sleep state."
171 * MPC8569E reference manual has a similar paragraph.
173 #ifdef CONFIG_PPC_85xx
180 /* we actually use cpm_muram implementation, define this for convenience */
181 #define qe_muram_init cpm_muram_init
182 #define qe_muram_alloc cpm_muram_alloc
183 #define qe_muram_alloc_fixed cpm_muram_alloc_fixed
184 #define qe_muram_free cpm_muram_free
185 #define qe_muram_addr cpm_muram_addr
186 #define qe_muram_offset cpm_muram_offset
188 /* Structure that defines QE firmware binary files.
190 * See Documentation/powerpc/qe-firmware.txt for a description of these
195 __be32 length; /* Length of the entire structure, in bytes */
196 u8 magic[3]; /* Set to { 'Q', 'E', 'F' } */
197 u8 version; /* Version of this layout. First ver is '1' */
199 u8 id[62]; /* Null-terminated identifier string */
200 u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */
201 u8 count; /* Number of microcode[] structures */
203 __be16 model; /* The SOC model */
204 u8 major; /* The SOC revision major */
205 u8 minor; /* The SOC revision minor */
206 } __attribute__ ((packed)) soc;
207 u8 padding[4]; /* Reserved, for alignment */
208 __be64 extended_modes; /* Extended modes */
209 __be32 vtraps[8]; /* Virtual trap addresses */
210 u8 reserved[4]; /* Reserved, for future expansion */
211 struct qe_microcode {
212 u8 id[32]; /* Null-terminated identifier */
213 __be32 traps[16]; /* Trap addresses, 0 == ignore */
214 __be32 eccr; /* The value for the ECCR register */
215 __be32 iram_offset; /* Offset into I-RAM for the code */
216 __be32 count; /* Number of 32-bit words of the code */
217 __be32 code_offset; /* Offset of the actual microcode */
218 u8 major; /* The microcode version major */
219 u8 minor; /* The microcode version minor */
220 u8 revision; /* The microcode version revision */
221 u8 padding; /* Reserved, for alignment */
222 u8 reserved[4]; /* Reserved, for future expansion */
223 } __attribute__ ((packed)) microcode[1];
224 /* All microcode binaries should be located here */
225 /* CRC32 should be located here, after the microcode binaries */
226 } __attribute__ ((packed));
228 struct qe_firmware_info {
229 char id[64]; /* Firmware name */
230 u32 vtraps[8]; /* Virtual trap addresses */
231 u64 extended_modes; /* Extended modes */
234 #ifdef CONFIG_QUICC_ENGINE
235 /* Upload a firmware to the QE */
236 int qe_upload_firmware(const struct qe_firmware *firmware);
238 static inline int qe_upload_firmware(const struct qe_firmware *firmware)
242 #endif /* CONFIG_QUICC_ENGINE */
244 /* Obtain information on the uploaded firmware */
245 struct qe_firmware_info *qe_get_firmware_info(void);
248 int qe_usb_clock_set(enum qe_clock clk, int rate);
250 /* Buffer descriptors */
255 } __attribute__ ((packed));
257 #define BD_STATUS_MASK 0xffff0000
258 #define BD_LENGTH_MASK 0x0000ffff
261 #define QE_INTR_TABLE_ALIGN 16 /* ??? */
262 #define QE_ALIGNMENT_OF_BD 8
263 #define QE_ALIGNMENT_OF_PRAM 64
265 /* RISC allocation */
266 #define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */
267 #define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */
268 #define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */
269 #define QE_RISC_ALLOCATION_RISC4 0x8 /* RISC 4 */
270 #define QE_RISC_ALLOCATION_RISC1_AND_RISC2 (QE_RISC_ALLOCATION_RISC1 | \
271 QE_RISC_ALLOCATION_RISC2)
272 #define QE_RISC_ALLOCATION_FOUR_RISCS (QE_RISC_ALLOCATION_RISC1 | \
273 QE_RISC_ALLOCATION_RISC2 | \
274 QE_RISC_ALLOCATION_RISC3 | \
275 QE_RISC_ALLOCATION_RISC4)
277 /* QE extended filtering Table Lookup Key Size */
278 enum qe_fltr_tbl_lookup_key_size {
279 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES
280 = 0x3f, /* LookupKey parsed by the Generate LookupKey
281 CMD is truncated to 8 bytes */
282 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES
283 = 0x5f, /* LookupKey parsed by the Generate LookupKey
284 CMD is truncated to 16 bytes */
287 /* QE FLTR extended filtering Largest External Table Lookup Key Size */
288 enum qe_fltr_largest_external_tbl_lookup_key_size {
289 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE
291 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES
292 = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES, /* 8 bytes */
293 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES
294 = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES, /* 16 bytes */
297 /* structure representing QE parameter RAM */
298 struct qe_timer_tables {
299 u16 tm_base; /* QE timer table base adr */
300 u16 tm_ptr; /* QE timer table pointer */
301 u16 r_tmr; /* QE timer mode register */
302 u16 r_tmv; /* QE timer valid register */
303 u32 tm_cmd; /* QE timer cmd register */
304 u32 tm_cnt; /* QE timer internal cnt */
305 } __attribute__ ((packed));
307 #define QE_FLTR_TAD_SIZE 8
309 /* QE extended filtering Termination Action Descriptor (TAD) */
311 u8 serialized[QE_FLTR_TAD_SIZE];
312 } __attribute__ ((packed));
314 /* Communication Direction */
319 COMM_DIR_RX_AND_TX = 3
322 /* QE CMXUCR Registers.
323 * There are two UCCs represented in each of the four CMXUCR registers.
324 * These values are for the UCC in the LSBs
326 #define QE_CMXUCR_MII_ENET_MNG 0x00007000
327 #define QE_CMXUCR_MII_ENET_MNG_SHIFT 12
328 #define QE_CMXUCR_GRANT 0x00008000
329 #define QE_CMXUCR_TSA 0x00004000
330 #define QE_CMXUCR_BKPT 0x00000100
331 #define QE_CMXUCR_TX_CLK_SRC_MASK 0x0000000F
333 /* QE CMXGCR Registers.
335 #define QE_CMXGCR_MII_ENET_MNG 0x00007000
336 #define QE_CMXGCR_MII_ENET_MNG_SHIFT 12
337 #define QE_CMXGCR_USBCS 0x0000000f
338 #define QE_CMXGCR_USBCS_CLK3 0x1
339 #define QE_CMXGCR_USBCS_CLK5 0x2
340 #define QE_CMXGCR_USBCS_CLK7 0x3
341 #define QE_CMXGCR_USBCS_CLK9 0x4
342 #define QE_CMXGCR_USBCS_CLK13 0x5
343 #define QE_CMXGCR_USBCS_CLK17 0x6
344 #define QE_CMXGCR_USBCS_CLK19 0x7
345 #define QE_CMXGCR_USBCS_CLK21 0x8
346 #define QE_CMXGCR_USBCS_BRG9 0x9
347 #define QE_CMXGCR_USBCS_BRG10 0xa
351 #define QE_CR_FLG 0x00010000
352 #define QE_RESET 0x80000000
353 #define QE_INIT_TX_RX 0x00000000
354 #define QE_INIT_RX 0x00000001
355 #define QE_INIT_TX 0x00000002
356 #define QE_ENTER_HUNT_MODE 0x00000003
357 #define QE_STOP_TX 0x00000004
358 #define QE_GRACEFUL_STOP_TX 0x00000005
359 #define QE_RESTART_TX 0x00000006
360 #define QE_CLOSE_RX_BD 0x00000007
361 #define QE_SWITCH_COMMAND 0x00000007
362 #define QE_SET_GROUP_ADDRESS 0x00000008
363 #define QE_START_IDMA 0x00000009
364 #define QE_MCC_STOP_RX 0x00000009
365 #define QE_ATM_TRANSMIT 0x0000000a
366 #define QE_HPAC_CLEAR_ALL 0x0000000b
367 #define QE_GRACEFUL_STOP_RX 0x0000001a
368 #define QE_RESTART_RX 0x0000001b
369 #define QE_HPAC_SET_PRIORITY 0x0000010b
370 #define QE_HPAC_STOP_TX 0x0000020b
371 #define QE_HPAC_STOP_RX 0x0000030b
372 #define QE_HPAC_GRACEFUL_STOP_TX 0x0000040b
373 #define QE_HPAC_GRACEFUL_STOP_RX 0x0000050b
374 #define QE_HPAC_START_TX 0x0000060b
375 #define QE_HPAC_START_RX 0x0000070b
376 #define QE_USB_STOP_TX 0x0000000a
377 #define QE_USB_RESTART_TX 0x0000000c
378 #define QE_QMC_STOP_TX 0x0000000c
379 #define QE_QMC_STOP_RX 0x0000000d
380 #define QE_SS7_SU_FIL_RESET 0x0000000e
381 /* jonathbr added from here down for 83xx */
382 #define QE_RESET_BCS 0x0000000a
383 #define QE_MCC_INIT_TX_RX_16 0x00000003
384 #define QE_MCC_STOP_TX 0x00000004
385 #define QE_MCC_INIT_TX_1 0x00000005
386 #define QE_MCC_INIT_RX_1 0x00000006
387 #define QE_MCC_RESET 0x00000007
388 #define QE_SET_TIMER 0x00000008
389 #define QE_RANDOM_NUMBER 0x0000000c
390 #define QE_ATM_MULTI_THREAD_INIT 0x00000011
391 #define QE_ASSIGN_PAGE 0x00000012
392 #define QE_ADD_REMOVE_HASH_ENTRY 0x00000013
393 #define QE_START_FLOW_CONTROL 0x00000014
394 #define QE_STOP_FLOW_CONTROL 0x00000015
395 #define QE_ASSIGN_PAGE_TO_DEVICE 0x00000016
397 #define QE_ASSIGN_RISC 0x00000010
398 #define QE_CR_MCN_NORMAL_SHIFT 6
399 #define QE_CR_MCN_USB_SHIFT 4
400 #define QE_CR_MCN_RISC_ASSIGN_SHIFT 8
401 #define QE_CR_SNUM_SHIFT 17
403 /* QE CECR Sub Block - sub block of QE command.
405 #define QE_CR_SUBBLOCK_INVALID 0x00000000
406 #define QE_CR_SUBBLOCK_USB 0x03200000
407 #define QE_CR_SUBBLOCK_UCCFAST1 0x02000000
408 #define QE_CR_SUBBLOCK_UCCFAST2 0x02200000
409 #define QE_CR_SUBBLOCK_UCCFAST3 0x02400000
410 #define QE_CR_SUBBLOCK_UCCFAST4 0x02600000
411 #define QE_CR_SUBBLOCK_UCCFAST5 0x02800000
412 #define QE_CR_SUBBLOCK_UCCFAST6 0x02a00000
413 #define QE_CR_SUBBLOCK_UCCFAST7 0x02c00000
414 #define QE_CR_SUBBLOCK_UCCFAST8 0x02e00000
415 #define QE_CR_SUBBLOCK_UCCSLOW1 0x00000000
416 #define QE_CR_SUBBLOCK_UCCSLOW2 0x00200000
417 #define QE_CR_SUBBLOCK_UCCSLOW3 0x00400000
418 #define QE_CR_SUBBLOCK_UCCSLOW4 0x00600000
419 #define QE_CR_SUBBLOCK_UCCSLOW5 0x00800000
420 #define QE_CR_SUBBLOCK_UCCSLOW6 0x00a00000
421 #define QE_CR_SUBBLOCK_UCCSLOW7 0x00c00000
422 #define QE_CR_SUBBLOCK_UCCSLOW8 0x00e00000
423 #define QE_CR_SUBBLOCK_MCC1 0x03800000
424 #define QE_CR_SUBBLOCK_MCC2 0x03a00000
425 #define QE_CR_SUBBLOCK_MCC3 0x03000000
426 #define QE_CR_SUBBLOCK_IDMA1 0x02800000
427 #define QE_CR_SUBBLOCK_IDMA2 0x02a00000
428 #define QE_CR_SUBBLOCK_IDMA3 0x02c00000
429 #define QE_CR_SUBBLOCK_IDMA4 0x02e00000
430 #define QE_CR_SUBBLOCK_HPAC 0x01e00000
431 #define QE_CR_SUBBLOCK_SPI1 0x01400000
432 #define QE_CR_SUBBLOCK_SPI2 0x01600000
433 #define QE_CR_SUBBLOCK_RAND 0x01c00000
434 #define QE_CR_SUBBLOCK_TIMER 0x01e00000
435 #define QE_CR_SUBBLOCK_GENERAL 0x03c00000
437 /* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command */
438 #define QE_CR_PROTOCOL_UNSPECIFIED 0x00 /* For all other protocols */
439 #define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00
440 #define QE_CR_PROTOCOL_QMC 0x02
441 #define QE_CR_PROTOCOL_UART 0x04
442 #define QE_CR_PROTOCOL_ATM_POS 0x0A
443 #define QE_CR_PROTOCOL_ETHERNET 0x0C
444 #define QE_CR_PROTOCOL_L2_SWITCH 0x0D
446 /* BRG configuration register */
447 #define QE_BRGC_ENABLE 0x00010000
448 #define QE_BRGC_DIVISOR_SHIFT 1
449 #define QE_BRGC_DIVISOR_MAX 0xFFF
450 #define QE_BRGC_DIV16 1
452 /* QE Timers registers */
453 #define QE_GTCFR1_PCAS 0x80
454 #define QE_GTCFR1_STP2 0x20
455 #define QE_GTCFR1_RST2 0x10
456 #define QE_GTCFR1_GM2 0x08
457 #define QE_GTCFR1_GM1 0x04
458 #define QE_GTCFR1_STP1 0x02
459 #define QE_GTCFR1_RST1 0x01
462 #define QE_SDSR_BER1 0x02000000
463 #define QE_SDSR_BER2 0x01000000
465 #define QE_SDMR_GLB_1_MSK 0x80000000
466 #define QE_SDMR_ADR_SEL 0x20000000
467 #define QE_SDMR_BER1_MSK 0x02000000
468 #define QE_SDMR_BER2_MSK 0x01000000
469 #define QE_SDMR_EB1_MSK 0x00800000
470 #define QE_SDMR_ER1_MSK 0x00080000
471 #define QE_SDMR_ER2_MSK 0x00040000
472 #define QE_SDMR_CEN_MASK 0x0000E000
473 #define QE_SDMR_SBER_1 0x00000200
474 #define QE_SDMR_SBER_2 0x00000200
475 #define QE_SDMR_EB1_PR_MASK 0x000000C0
476 #define QE_SDMR_ER1_PR 0x00000008
478 #define QE_SDMR_CEN_SHIFT 13
479 #define QE_SDMR_EB1_PR_SHIFT 6
481 #define QE_SDTM_MSNUM_SHIFT 24
483 #define QE_SDEBCR_BA_MASK 0x01FFFFFF
485 /* Communication Processor */
486 #define QE_CP_CERCR_MEE 0x8000 /* Multi-user RAM ECC enable */
487 #define QE_CP_CERCR_IEE 0x4000 /* Instruction RAM ECC enable */
488 #define QE_CP_CERCR_CIR 0x0800 /* Common instruction RAM */
491 #define QE_IRAM_IADD_AIE 0x80000000 /* Auto Increment Enable */
492 #define QE_IRAM_IADD_BADDR 0x00080000 /* Base Address */
495 #define UPGCR_PROTOCOL 0x80000000 /* protocol ul2 or pl2 */
496 #define UPGCR_TMS 0x40000000 /* Transmit master/slave mode */
497 #define UPGCR_RMS 0x20000000 /* Receive master/slave mode */
498 #define UPGCR_ADDR 0x10000000 /* Master MPHY Addr multiplexing */
499 #define UPGCR_DIAG 0x01000000 /* Diagnostic mode */
501 /* UCC GUEMR register */
502 #define UCC_GUEMR_MODE_MASK_RX 0x02
503 #define UCC_GUEMR_MODE_FAST_RX 0x02
504 #define UCC_GUEMR_MODE_SLOW_RX 0x00
505 #define UCC_GUEMR_MODE_MASK_TX 0x01
506 #define UCC_GUEMR_MODE_FAST_TX 0x01
507 #define UCC_GUEMR_MODE_SLOW_TX 0x00
508 #define UCC_GUEMR_MODE_MASK (UCC_GUEMR_MODE_MASK_RX | UCC_GUEMR_MODE_MASK_TX)
509 #define UCC_GUEMR_SET_RESERVED3 0x10 /* Bit 3 in the guemr is reserved but
512 /* structure representing UCC SLOW parameter RAM */
513 struct ucc_slow_pram {
514 __be16 rbase; /* RX BD base address */
515 __be16 tbase; /* TX BD base address */
516 u8 rbmr; /* RX bus mode register (same as CPM's RFCR) */
517 u8 tbmr; /* TX bus mode register (same as CPM's TFCR) */
518 __be16 mrblr; /* Rx buffer length */
519 __be32 rstate; /* Rx internal state */
520 __be32 rptr; /* Rx internal data pointer */
521 __be16 rbptr; /* rb BD Pointer */
522 __be16 rcount; /* Rx internal byte count */
523 __be32 rtemp; /* Rx temp */
524 __be32 tstate; /* Tx internal state */
525 __be32 tptr; /* Tx internal data pointer */
526 __be16 tbptr; /* Tx BD pointer */
527 __be16 tcount; /* Tx byte count */
528 __be32 ttemp; /* Tx temp */
529 __be32 rcrc; /* temp receive CRC */
530 __be32 tcrc; /* temp transmit CRC */
531 } __attribute__ ((packed));
533 /* General UCC SLOW Mode Register (GUMRH & GUMRL) */
534 #define UCC_SLOW_GUMR_H_SAM_QMC 0x00000000
535 #define UCC_SLOW_GUMR_H_SAM_SATM 0x00008000
536 #define UCC_SLOW_GUMR_H_REVD 0x00002000
537 #define UCC_SLOW_GUMR_H_TRX 0x00001000
538 #define UCC_SLOW_GUMR_H_TTX 0x00000800
539 #define UCC_SLOW_GUMR_H_CDP 0x00000400
540 #define UCC_SLOW_GUMR_H_CTSP 0x00000200
541 #define UCC_SLOW_GUMR_H_CDS 0x00000100
542 #define UCC_SLOW_GUMR_H_CTSS 0x00000080
543 #define UCC_SLOW_GUMR_H_TFL 0x00000040
544 #define UCC_SLOW_GUMR_H_RFW 0x00000020
545 #define UCC_SLOW_GUMR_H_TXSY 0x00000010
546 #define UCC_SLOW_GUMR_H_4SYNC 0x00000004
547 #define UCC_SLOW_GUMR_H_8SYNC 0x00000008
548 #define UCC_SLOW_GUMR_H_16SYNC 0x0000000c
549 #define UCC_SLOW_GUMR_H_RTSM 0x00000002
550 #define UCC_SLOW_GUMR_H_RSYN 0x00000001
552 #define UCC_SLOW_GUMR_L_TCI 0x10000000
553 #define UCC_SLOW_GUMR_L_RINV 0x02000000
554 #define UCC_SLOW_GUMR_L_TINV 0x01000000
555 #define UCC_SLOW_GUMR_L_TEND 0x00040000
556 #define UCC_SLOW_GUMR_L_TDCR_MASK 0x00030000
557 #define UCC_SLOW_GUMR_L_TDCR_32 0x00030000
558 #define UCC_SLOW_GUMR_L_TDCR_16 0x00020000
559 #define UCC_SLOW_GUMR_L_TDCR_8 0x00010000
560 #define UCC_SLOW_GUMR_L_TDCR_1 0x00000000
561 #define UCC_SLOW_GUMR_L_RDCR_MASK 0x0000c000
562 #define UCC_SLOW_GUMR_L_RDCR_32 0x0000c000
563 #define UCC_SLOW_GUMR_L_RDCR_16 0x00008000
564 #define UCC_SLOW_GUMR_L_RDCR_8 0x00004000
565 #define UCC_SLOW_GUMR_L_RDCR_1 0x00000000
566 #define UCC_SLOW_GUMR_L_RENC_NRZI 0x00000800
567 #define UCC_SLOW_GUMR_L_RENC_NRZ 0x00000000
568 #define UCC_SLOW_GUMR_L_TENC_NRZI 0x00000100
569 #define UCC_SLOW_GUMR_L_TENC_NRZ 0x00000000
570 #define UCC_SLOW_GUMR_L_DIAG_MASK 0x000000c0
571 #define UCC_SLOW_GUMR_L_DIAG_LE 0x000000c0
572 #define UCC_SLOW_GUMR_L_DIAG_ECHO 0x00000080
573 #define UCC_SLOW_GUMR_L_DIAG_LOOP 0x00000040
574 #define UCC_SLOW_GUMR_L_DIAG_NORM 0x00000000
575 #define UCC_SLOW_GUMR_L_ENR 0x00000020
576 #define UCC_SLOW_GUMR_L_ENT 0x00000010
577 #define UCC_SLOW_GUMR_L_MODE_MASK 0x0000000F
578 #define UCC_SLOW_GUMR_L_MODE_BISYNC 0x00000008
579 #define UCC_SLOW_GUMR_L_MODE_AHDLC 0x00000006
580 #define UCC_SLOW_GUMR_L_MODE_UART 0x00000004
581 #define UCC_SLOW_GUMR_L_MODE_QMC 0x00000002
583 /* General UCC FAST Mode Register */
584 #define UCC_FAST_GUMR_TCI 0x20000000
585 #define UCC_FAST_GUMR_TRX 0x10000000
586 #define UCC_FAST_GUMR_TTX 0x08000000
587 #define UCC_FAST_GUMR_CDP 0x04000000
588 #define UCC_FAST_GUMR_CTSP 0x02000000
589 #define UCC_FAST_GUMR_CDS 0x01000000
590 #define UCC_FAST_GUMR_CTSS 0x00800000
591 #define UCC_FAST_GUMR_TXSY 0x00020000
592 #define UCC_FAST_GUMR_RSYN 0x00010000
593 #define UCC_FAST_GUMR_RTSM 0x00002000
594 #define UCC_FAST_GUMR_REVD 0x00000400
595 #define UCC_FAST_GUMR_ENR 0x00000020
596 #define UCC_FAST_GUMR_ENT 0x00000010
598 /* UART Slow UCC Event Register (UCCE) */
599 #define UCC_UART_UCCE_AB 0x0200
600 #define UCC_UART_UCCE_IDLE 0x0100
601 #define UCC_UART_UCCE_GRA 0x0080
602 #define UCC_UART_UCCE_BRKE 0x0040
603 #define UCC_UART_UCCE_BRKS 0x0020
604 #define UCC_UART_UCCE_CCR 0x0008
605 #define UCC_UART_UCCE_BSY 0x0004
606 #define UCC_UART_UCCE_TX 0x0002
607 #define UCC_UART_UCCE_RX 0x0001
609 /* HDLC Slow UCC Event Register (UCCE) */
610 #define UCC_HDLC_UCCE_GLR 0x1000
611 #define UCC_HDLC_UCCE_GLT 0x0800
612 #define UCC_HDLC_UCCE_IDLE 0x0100
613 #define UCC_HDLC_UCCE_BRKE 0x0040
614 #define UCC_HDLC_UCCE_BRKS 0x0020
615 #define UCC_HDLC_UCCE_TXE 0x0010
616 #define UCC_HDLC_UCCE_RXF 0x0008
617 #define UCC_HDLC_UCCE_BSY 0x0004
618 #define UCC_HDLC_UCCE_TXB 0x0002
619 #define UCC_HDLC_UCCE_RXB 0x0001
621 /* BISYNC Slow UCC Event Register (UCCE) */
622 #define UCC_BISYNC_UCCE_GRA 0x0080
623 #define UCC_BISYNC_UCCE_TXE 0x0010
624 #define UCC_BISYNC_UCCE_RCH 0x0008
625 #define UCC_BISYNC_UCCE_BSY 0x0004
626 #define UCC_BISYNC_UCCE_TXB 0x0002
627 #define UCC_BISYNC_UCCE_RXB 0x0001
629 /* Gigabit Ethernet Fast UCC Event Register (UCCE) */
630 #define UCC_GETH_UCCE_MPD 0x80000000
631 #define UCC_GETH_UCCE_SCAR 0x40000000
632 #define UCC_GETH_UCCE_GRA 0x20000000
633 #define UCC_GETH_UCCE_CBPR 0x10000000
634 #define UCC_GETH_UCCE_BSY 0x08000000
635 #define UCC_GETH_UCCE_RXC 0x04000000
636 #define UCC_GETH_UCCE_TXC 0x02000000
637 #define UCC_GETH_UCCE_TXE 0x01000000
638 #define UCC_GETH_UCCE_TXB7 0x00800000
639 #define UCC_GETH_UCCE_TXB6 0x00400000
640 #define UCC_GETH_UCCE_TXB5 0x00200000
641 #define UCC_GETH_UCCE_TXB4 0x00100000
642 #define UCC_GETH_UCCE_TXB3 0x00080000
643 #define UCC_GETH_UCCE_TXB2 0x00040000
644 #define UCC_GETH_UCCE_TXB1 0x00020000
645 #define UCC_GETH_UCCE_TXB0 0x00010000
646 #define UCC_GETH_UCCE_RXB7 0x00008000
647 #define UCC_GETH_UCCE_RXB6 0x00004000
648 #define UCC_GETH_UCCE_RXB5 0x00002000
649 #define UCC_GETH_UCCE_RXB4 0x00001000
650 #define UCC_GETH_UCCE_RXB3 0x00000800
651 #define UCC_GETH_UCCE_RXB2 0x00000400
652 #define UCC_GETH_UCCE_RXB1 0x00000200
653 #define UCC_GETH_UCCE_RXB0 0x00000100
654 #define UCC_GETH_UCCE_RXF7 0x00000080
655 #define UCC_GETH_UCCE_RXF6 0x00000040
656 #define UCC_GETH_UCCE_RXF5 0x00000020
657 #define UCC_GETH_UCCE_RXF4 0x00000010
658 #define UCC_GETH_UCCE_RXF3 0x00000008
659 #define UCC_GETH_UCCE_RXF2 0x00000004
660 #define UCC_GETH_UCCE_RXF1 0x00000002
661 #define UCC_GETH_UCCE_RXF0 0x00000001
663 /* UCC Protocol Specific Mode Register (UPSMR), when used for UART */
664 #define UCC_UART_UPSMR_FLC 0x8000
665 #define UCC_UART_UPSMR_SL 0x4000
666 #define UCC_UART_UPSMR_CL_MASK 0x3000
667 #define UCC_UART_UPSMR_CL_8 0x3000
668 #define UCC_UART_UPSMR_CL_7 0x2000
669 #define UCC_UART_UPSMR_CL_6 0x1000
670 #define UCC_UART_UPSMR_CL_5 0x0000
671 #define UCC_UART_UPSMR_UM_MASK 0x0c00
672 #define UCC_UART_UPSMR_UM_NORMAL 0x0000
673 #define UCC_UART_UPSMR_UM_MAN_MULTI 0x0400
674 #define UCC_UART_UPSMR_UM_AUTO_MULTI 0x0c00
675 #define UCC_UART_UPSMR_FRZ 0x0200
676 #define UCC_UART_UPSMR_RZS 0x0100
677 #define UCC_UART_UPSMR_SYN 0x0080
678 #define UCC_UART_UPSMR_DRT 0x0040
679 #define UCC_UART_UPSMR_PEN 0x0010
680 #define UCC_UART_UPSMR_RPM_MASK 0x000c
681 #define UCC_UART_UPSMR_RPM_ODD 0x0000
682 #define UCC_UART_UPSMR_RPM_LOW 0x0004
683 #define UCC_UART_UPSMR_RPM_EVEN 0x0008
684 #define UCC_UART_UPSMR_RPM_HIGH 0x000C
685 #define UCC_UART_UPSMR_TPM_MASK 0x0003
686 #define UCC_UART_UPSMR_TPM_ODD 0x0000
687 #define UCC_UART_UPSMR_TPM_LOW 0x0001
688 #define UCC_UART_UPSMR_TPM_EVEN 0x0002
689 #define UCC_UART_UPSMR_TPM_HIGH 0x0003
691 /* UCC Protocol Specific Mode Register (UPSMR), when used for Ethernet */
692 #define UCC_GETH_UPSMR_FTFE 0x80000000
693 #define UCC_GETH_UPSMR_PTPE 0x40000000
694 #define UCC_GETH_UPSMR_ECM 0x04000000
695 #define UCC_GETH_UPSMR_HSE 0x02000000
696 #define UCC_GETH_UPSMR_PRO 0x00400000
697 #define UCC_GETH_UPSMR_CAP 0x00200000
698 #define UCC_GETH_UPSMR_RSH 0x00100000
699 #define UCC_GETH_UPSMR_RPM 0x00080000
700 #define UCC_GETH_UPSMR_R10M 0x00040000
701 #define UCC_GETH_UPSMR_RLPB 0x00020000
702 #define UCC_GETH_UPSMR_TBIM 0x00010000
703 #define UCC_GETH_UPSMR_RES1 0x00002000
704 #define UCC_GETH_UPSMR_RMM 0x00001000
705 #define UCC_GETH_UPSMR_CAM 0x00000400
706 #define UCC_GETH_UPSMR_BRO 0x00000200
707 #define UCC_GETH_UPSMR_SMM 0x00000080
708 #define UCC_GETH_UPSMR_SGMM 0x00000020
710 /* UCC Transmit On Demand Register (UTODR) */
711 #define UCC_SLOW_TOD 0x8000
712 #define UCC_FAST_TOD 0x8000
714 /* UCC Bus Mode Register masks */
715 /* Not to be confused with the Bundle Mode Register */
716 #define UCC_BMR_GBL 0x20
717 #define UCC_BMR_BO_BE 0x10
718 #define UCC_BMR_CETM 0x04
719 #define UCC_BMR_DTB 0x02
720 #define UCC_BMR_BDB 0x01
722 /* Function code masks */
724 #define FC_DTB_LCL 0x02
725 #define UCC_FAST_FUNCTION_CODE_GBL 0x20
726 #define UCC_FAST_FUNCTION_CODE_DTB_LCL 0x02
727 #define UCC_FAST_FUNCTION_CODE_BDB_LCL 0x01
729 #endif /* __KERNEL__ */
730 #endif /* _ASM_POWERPC_QE_H */