SAFE public projects git trees. - safe/jmp/linux-2.6/blob - arch/mips/mm/c-r4k.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
   7  * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org)
   8  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
   9  */
  10 #include <linux/config.h>
  11 #include <linux/init.h>
  12 #include <linux/kernel.h>
  13 #include <linux/sched.h>
  14 #include <linux/mm.h>
  15 #include <linux/bitops.h>
  16
  17 #include <asm/bcache.h>
  18 #include <asm/bootinfo.h>
  19 #include <asm/cacheops.h>
  20 #include <asm/cpu.h>
  21 #include <asm/cpu-features.h>
  22 #include <asm/io.h>
  23 #include <asm/page.h>
  24 #include <asm/pgtable.h>
  25 #include <asm/r4kcache.h>
  26 #include <asm/system.h>
  27 #include <asm/mmu_context.h>
  28 #include <asm/war.h>
  29 #include <asm/cacheflush.h> /* for run_uncached() */
  30
  31 static unsigned long icache_size, dcache_size, scache_size;
  32
  33 /*
  34  * Dummy cache handling routines for machines without boardcaches
  35  */
  36 static void no_sc_noop(void) {}
  37
  38 static struct bcache_ops no_sc_ops = {
  39         .bc_enable = (void *)no_sc_noop,
  40         .bc_disable = (void *)no_sc_noop,
  41         .bc_wback_inv = (void *)no_sc_noop,
  42         .bc_inv = (void *)no_sc_noop
  43 };
  44
  45 struct bcache_ops *bcops = &no_sc_ops;
  46
  47 #define cpu_is_r4600_v1_x()     ((read_c0_prid() & 0xfffffff0) == 0x2010)
  48 #define cpu_is_r4600_v2_x()     ((read_c0_prid() & 0xfffffff0) == 0x2020)
  49
  50 #define R4600_HIT_CACHEOP_WAR_IMPL                                      \
  51 do {                                                                    \
  52         if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())            \
  53                 *(volatile unsigned long *)CKSEG1;                      \
  54         if (R4600_V1_HIT_CACHEOP_WAR)                                   \
  55                 __asm__ __volatile__("nop;nop;nop;nop");                \
  56 } while (0)
  57
  58 static void (*r4k_blast_dcache_page)(unsigned long addr);
  59
  60 static inline void r4k_blast_dcache_page_dc32(unsigned long addr)
  61 {
  62         R4600_HIT_CACHEOP_WAR_IMPL;
  63         blast_dcache32_page(addr);
  64 }
  65
  66 static inline void r4k_blast_dcache_page_setup(void)
  67 {
  68         unsigned long  dc_lsize = cpu_dcache_line_size();
  69
  70         if (dc_lsize == 16)
  71                 r4k_blast_dcache_page = blast_dcache16_page;
  72         else if (dc_lsize == 32)
  73                 r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
  74 }
  75
  76 static void (* r4k_blast_dcache_page_indexed)(unsigned long addr);
  77
  78 static inline void r4k_blast_dcache_page_indexed_setup(void)
  79 {
  80         unsigned long dc_lsize = cpu_dcache_line_size();
  81
  82         if (dc_lsize == 16)
  83                 r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed;
  84         else if (dc_lsize == 32)
  85                 r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
  86 }
  87
  88 static void (* r4k_blast_dcache)(void);
  89
  90 static inline void r4k_blast_dcache_setup(void)
  91 {
  92         unsigned long dc_lsize = cpu_dcache_line_size();
  93
  94         if (dc_lsize == 16)
  95                 r4k_blast_dcache = blast_dcache16;
  96         else if (dc_lsize == 32)
  97                 r4k_blast_dcache = blast_dcache32;
  98 }
  99
 100 /* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */
 101 #define JUMP_TO_ALIGN(order) \
 102         __asm__ __volatile__( \
 103                 "b\t1f\n\t" \
 104                 ".align\t" #order "\n\t" \
 105                 "1:\n\t" \
 106                 )
 107 #define CACHE32_UNROLL32_ALIGN  JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */
 108 #define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11)
 109
 110 static inline void blast_r4600_v1_icache32(void)
 111 {
 112         unsigned long flags;
 113
 114         local_irq_save(flags);
 115         blast_icache32();
 116         local_irq_restore(flags);
 117 }
 118
 119 static inline void tx49_blast_icache32(void)
 120 {
 121         unsigned long start = INDEX_BASE;
 122         unsigned long end = start + current_cpu_data.icache.waysize;
 123         unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
 124         unsigned long ws_end = current_cpu_data.icache.ways <<
 125                                current_cpu_data.icache.waybit;
 126         unsigned long ws, addr;
 127
 128         CACHE32_UNROLL32_ALIGN2;
 129         /* I'm in even chunk.  blast odd chunks */
 130         for (ws = 0; ws < ws_end; ws += ws_inc)
 131                 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
 132                         cache32_unroll32(addr|ws,Index_Invalidate_I);
 133         CACHE32_UNROLL32_ALIGN;
 134         /* I'm in odd chunk.  blast even chunks */
 135         for (ws = 0; ws < ws_end; ws += ws_inc)
 136                 for (addr = start; addr < end; addr += 0x400 * 2)
 137                         cache32_unroll32(addr|ws,Index_Invalidate_I);
 138 }
 139
 140 static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page)
 141 {
 142         unsigned long flags;
 143
 144         local_irq_save(flags);
 145         blast_icache32_page_indexed(page);
 146         local_irq_restore(flags);
 147 }
 148
 149 static inline void tx49_blast_icache32_page_indexed(unsigned long page)
 150 {
 151         unsigned long start = page;
 152         unsigned long end = start + PAGE_SIZE;
 153         unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
 154         unsigned long ws_end = current_cpu_data.icache.ways <<
 155                                current_cpu_data.icache.waybit;
 156         unsigned long ws, addr;
 157
 158         CACHE32_UNROLL32_ALIGN2;
 159         /* I'm in even chunk.  blast odd chunks */
 160         for (ws = 0; ws < ws_end; ws += ws_inc)
 161                 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
 162                         cache32_unroll32(addr|ws,Index_Invalidate_I);
 163         CACHE32_UNROLL32_ALIGN;
 164         /* I'm in odd chunk.  blast even chunks */
 165         for (ws = 0; ws < ws_end; ws += ws_inc)
 166                 for (addr = start; addr < end; addr += 0x400 * 2)
 167                         cache32_unroll32(addr|ws,Index_Invalidate_I);
 168 }
 169
 170 static void (* r4k_blast_icache_page)(unsigned long addr);
 171
 172 static inline void r4k_blast_icache_page_setup(void)
 173 {
 174         unsigned long ic_lsize = cpu_icache_line_size();
 175
 176         if (ic_lsize == 16)
 177                 r4k_blast_icache_page = blast_icache16_page;
 178         else if (ic_lsize == 32)
 179                 r4k_blast_icache_page = blast_icache32_page;
 180         else if (ic_lsize == 64)
 181                 r4k_blast_icache_page = blast_icache64_page;
 182 }
 183
 184
 185 static void (* r4k_blast_icache_page_indexed)(unsigned long addr);
 186
 187 static inline void r4k_blast_icache_page_indexed_setup(void)
 188 {
 189         unsigned long ic_lsize = cpu_icache_line_size();
 190
 191         if (ic_lsize == 16)
 192                 r4k_blast_icache_page_indexed = blast_icache16_page_indexed;
 193         else if (ic_lsize == 32) {
 194                 if (TX49XX_ICACHE_INDEX_INV_WAR)
 195                         r4k_blast_icache_page_indexed =
 196                                 tx49_blast_icache32_page_indexed;
 197                 else if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
 198                         r4k_blast_icache_page_indexed =
 199                                 blast_icache32_r4600_v1_page_indexed;
 200                 else
 201                         r4k_blast_icache_page_indexed =
 202                                 blast_icache32_page_indexed;
 203         } else if (ic_lsize == 64)
 204                 r4k_blast_icache_page_indexed = blast_icache64_page_indexed;
 205 }
 206
 207 static void (* r4k_blast_icache)(void);
 208
 209 static inline void r4k_blast_icache_setup(void)
 210 {
 211         unsigned long ic_lsize = cpu_icache_line_size();
 212
 213         if (ic_lsize == 16)
 214                 r4k_blast_icache = blast_icache16;
 215         else if (ic_lsize == 32) {
 216                 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
 217                         r4k_blast_icache = blast_r4600_v1_icache32;
 218                 else if (TX49XX_ICACHE_INDEX_INV_WAR)
 219                         r4k_blast_icache = tx49_blast_icache32;
 220                 else
 221                         r4k_blast_icache = blast_icache32;
 222         } else if (ic_lsize == 64)
 223                 r4k_blast_icache = blast_icache64;
 224 }
 225
 226 static void (* r4k_blast_scache_page)(unsigned long addr);
 227
 228 static inline void r4k_blast_scache_page_setup(void)
 229 {
 230         unsigned long sc_lsize = cpu_scache_line_size();
 231
 232         if (sc_lsize == 16)
 233                 r4k_blast_scache_page = blast_scache16_page;
 234         else if (sc_lsize == 32)
 235                 r4k_blast_scache_page = blast_scache32_page;
 236         else if (sc_lsize == 64)
 237                 r4k_blast_scache_page = blast_scache64_page;
 238         else if (sc_lsize == 128)
 239                 r4k_blast_scache_page = blast_scache128_page;
 240 }
 241
 242 static void (* r4k_blast_scache_page_indexed)(unsigned long addr);
 243
 244 static inline void r4k_blast_scache_page_indexed_setup(void)
 245 {
 246         unsigned long sc_lsize = cpu_scache_line_size();
 247
 248         if (sc_lsize == 16)
 249                 r4k_blast_scache_page_indexed = blast_scache16_page_indexed;
 250         else if (sc_lsize == 32)
 251                 r4k_blast_scache_page_indexed = blast_scache32_page_indexed;
 252         else if (sc_lsize == 64)
 253                 r4k_blast_scache_page_indexed = blast_scache64_page_indexed;
 254         else if (sc_lsize == 128)
 255                 r4k_blast_scache_page_indexed = blast_scache128_page_indexed;
 256 }
 257
 258 static void (* r4k_blast_scache)(void);
 259
 260 static inline void r4k_blast_scache_setup(void)
 261 {
 262         unsigned long sc_lsize = cpu_scache_line_size();
 263
 264         if (sc_lsize == 16)
 265                 r4k_blast_scache = blast_scache16;
 266         else if (sc_lsize == 32)
 267                 r4k_blast_scache = blast_scache32;
 268         else if (sc_lsize == 64)
 269                 r4k_blast_scache = blast_scache64;
 270         else if (sc_lsize == 128)
 271                 r4k_blast_scache = blast_scache128;
 272 }
 273
 274 /*
 275  * This is former mm's flush_cache_all() which really should be
 276  * flush_cache_vunmap these days ...
 277  */
 278 static inline void local_r4k_flush_cache_all(void * args)
 279 {
 280         r4k_blast_dcache();
 281         r4k_blast_icache();
 282 }
 283
 284 static void r4k_flush_cache_all(void)
 285 {
 286         if (!cpu_has_dc_aliases)
 287                 return;
 288
 289         on_each_cpu(local_r4k_flush_cache_all, NULL, 1, 1);
 290 }
 291
 292 static inline void local_r4k___flush_cache_all(void * args)
 293 {
 294         r4k_blast_dcache();
 295         r4k_blast_icache();
 296
 297         switch (current_cpu_data.cputype) {
 298         case CPU_R4000SC:
 299         case CPU_R4000MC:
 300         case CPU_R4400SC:
 301         case CPU_R4400MC:
 302         case CPU_R10000:
 303         case CPU_R12000:
 304                 r4k_blast_scache();
 305         }
 306 }
 307
 308 static void r4k___flush_cache_all(void)
 309 {
 310         on_each_cpu(local_r4k___flush_cache_all, NULL, 1, 1);
 311 }
 312
 313 static inline void local_r4k_flush_cache_range(void * args)
 314 {
 315         struct vm_area_struct *vma = args;
 316         int exec;
 317
 318         if (!(cpu_context(smp_processor_id(), vma->vm_mm)))
 319                 return;
 320
 321         exec = vma->vm_flags & VM_EXEC;
 322         if (cpu_has_dc_aliases || exec)
 323                 r4k_blast_dcache();
 324         if (exec)
 325                 r4k_blast_icache();
 326 }
 327
 328 static void r4k_flush_cache_range(struct vm_area_struct *vma,
 329         unsigned long start, unsigned long end)
 330 {
 331         on_each_cpu(local_r4k_flush_cache_range, vma, 1, 1);
 332 }
 333
 334 static inline void local_r4k_flush_cache_mm(void * args)
 335 {
 336         struct mm_struct *mm = args;
 337
 338         if (!cpu_context(smp_processor_id(), mm))
 339                 return;
 340
 341         r4k_blast_dcache();
 342         r4k_blast_icache();
 343
 344         /*
 345          * Kludge alert.  For obscure reasons R4000SC and R4400SC go nuts if we
 346          * only flush the primary caches but R10000 and R12000 behave sane ...
 347          */
 348         if (current_cpu_data.cputype == CPU_R4000SC ||
 349             current_cpu_data.cputype == CPU_R4000MC ||
 350             current_cpu_data.cputype == CPU_R4400SC ||
 351             current_cpu_data.cputype == CPU_R4400MC)
 352                 r4k_blast_scache();
 353 }
 354
 355 static void r4k_flush_cache_mm(struct mm_struct *mm)
 356 {
 357         if (!cpu_has_dc_aliases)
 358                 return;
 359
 360         on_each_cpu(local_r4k_flush_cache_mm, mm, 1, 1);
 361 }
 362
 363 struct flush_cache_page_args {
 364         struct vm_area_struct *vma;
 365         unsigned long page;
 366 };
 367
 368 static inline void local_r4k_flush_cache_page(void *args)
 369 {
 370         struct flush_cache_page_args *fcp_args = args;
 371         struct vm_area_struct *vma = fcp_args->vma;
 372         unsigned long page = fcp_args->page;
 373         int exec = vma->vm_flags & VM_EXEC;
 374         struct mm_struct *mm = vma->vm_mm;
 375         pgd_t *pgdp;
 376         pud_t *pudp;
 377         pmd_t *pmdp;
 378         pte_t *ptep;
 379
 380         /*
 381          * If ownes no valid ASID yet, cannot possibly have gotten
 382          * this page into the cache.
 383          */
 384         if (cpu_context(smp_processor_id(), mm) == 0)
 385                 return;
 386
 387         page &= PAGE_MASK;
 388         pgdp = pgd_offset(mm, page);
 389         pudp = pud_offset(pgdp, page);
 390         pmdp = pmd_offset(pudp, page);
 391         ptep = pte_offset(pmdp, page);
 392
 393         /*
 394          * If the page isn't marked valid, the page cannot possibly be
 395          * in the cache.
 396          */
 397         if (!(pte_val(*ptep) & _PAGE_PRESENT))
 398                 return;
 399
 400         /*
 401          * Doing flushes for another ASID than the current one is
 402          * too difficult since stupid R4k caches do a TLB translation
 403          * for every cache flush operation.  So we do indexed flushes
 404          * in that case, which doesn't overly flush the cache too much.
 405          */
 406         if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) {
 407                 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
 408                         r4k_blast_dcache_page(page);
 409                         if (exec && !cpu_icache_snoops_remote_store)
 410                                 r4k_blast_scache_page(page);
 411                 }
 412                 if (exec)
 413                         r4k_blast_icache_page(page);
 414
 415                 return;
 416         }
 417
 418         /*
 419          * Do indexed flush, too much work to get the (possible) TLB refills
 420          * to work correctly.
 421          */
 422         page = INDEX_BASE + (page & (dcache_size - 1));
 423         if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
 424                 r4k_blast_dcache_page_indexed(page);
 425                 if (exec && !cpu_icache_snoops_remote_store)
 426                         r4k_blast_scache_page_indexed(page);
 427         }
 428         if (exec) {
 429                 if (cpu_has_vtag_icache) {
 430                         int cpu = smp_processor_id();
 431
 432                         if (cpu_context(cpu, mm) != 0)
 433                                 drop_mmu_context(mm, cpu);
 434                 } else
 435                         r4k_blast_icache_page_indexed(page);
 436         }
 437 }
 438
 439 static void r4k_flush_cache_page(struct vm_area_struct *vma, unsigned long page, unsigned long pfn)
 440 {
 441         struct flush_cache_page_args args;
 442
 443         args.vma = vma;
 444         args.page = page;
 445
 446         on_each_cpu(local_r4k_flush_cache_page, &args, 1, 1);
 447 }
 448
 449 static inline void local_r4k_flush_data_cache_page(void * addr)
 450 {
 451         r4k_blast_dcache_page((unsigned long) addr);
 452 }
 453
 454 static void r4k_flush_data_cache_page(unsigned long addr)
 455 {
 456         on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr, 1, 1);
 457 }
 458
 459 struct flush_icache_range_args {
 460         unsigned long __user start;
 461         unsigned long __user end;
 462 };
 463
 464 static inline void local_r4k_flush_icache_range(void *args)
 465 {
 466         struct flush_icache_range_args *fir_args = args;
 467         unsigned long dc_lsize = current_cpu_data.dcache.linesz;
 468         unsigned long ic_lsize = current_cpu_data.icache.linesz;
 469         unsigned long sc_lsize = current_cpu_data.scache.linesz;
 470         unsigned long start = fir_args->start;
 471         unsigned long end = fir_args->end;
 472         unsigned long addr, aend;
 473
 474         if (!cpu_has_ic_fills_f_dc) {
 475                 if (end - start > dcache_size) {
 476                         r4k_blast_dcache();
 477                 } else {
 478                         addr = start & ~(dc_lsize - 1);
 479                         aend = (end - 1) & ~(dc_lsize - 1);
 480
 481                         while (1) {
 482                                 /* Hit_Writeback_Inv_D */
 483                                 protected_writeback_dcache_line(addr);
 484                                 if (addr == aend)
 485                                         break;
 486                                 addr += dc_lsize;
 487                         }
 488                 }
 489
 490                 if (!cpu_icache_snoops_remote_store) {
 491                         if (end - start > scache_size) {
 492                                 r4k_blast_scache();
 493                         } else {
 494                                 addr = start & ~(sc_lsize - 1);
 495                                 aend = (end - 1) & ~(sc_lsize - 1);
 496
 497                                 while (1) {
 498                                         /* Hit_Writeback_Inv_D */
 499                                         protected_writeback_scache_line(addr);
 500                                         if (addr == aend)
 501                                                 break;
 502                                         addr += sc_lsize;
 503                                 }
 504                         }
 505                 }
 506         }
 507
 508         if (end - start > icache_size)
 509                 r4k_blast_icache();
 510         else {
 511                 addr = start & ~(ic_lsize - 1);
 512                 aend = (end - 1) & ~(ic_lsize - 1);
 513                 while (1) {
 514                         /* Hit_Invalidate_I */
 515                         protected_flush_icache_line(addr);
 516                         if (addr == aend)
 517                                 break;
 518                         addr += ic_lsize;
 519                 }
 520         }
 521 }
 522
 523 static void r4k_flush_icache_range(unsigned long __user start,
 524         unsigned long __user end)
 525 {
 526         struct flush_icache_range_args args;
 527
 528         args.start = start;
 529         args.end = end;
 530
 531         on_each_cpu(local_r4k_flush_icache_range, &args, 1, 1);
 532 }
 533
 534 /*
 535  * Ok, this seriously sucks.  We use them to flush a user page but don't
 536  * know the virtual address, so we have to blast away the whole icache
 537  * which is significantly more expensive than the real thing.  Otoh we at
 538  * least know the kernel address of the page so we can flush it
 539  * selectivly.
 540  */
 541
 542 struct flush_icache_page_args {
 543         struct vm_area_struct *vma;
 544         struct page *page;
 545 };
 546
 547 static inline void local_r4k_flush_icache_page(void *args)
 548 {
 549         struct flush_icache_page_args *fip_args = args;
 550         struct vm_area_struct *vma = fip_args->vma;
 551         struct page *page = fip_args->page;
 552
 553         /*
 554          * Tricky ...  Because we don't know the virtual address we've got the
 555          * choice of either invalidating the entire primary and secondary
 556          * caches or invalidating the secondary caches also.  With the subset
 557          * enforcment on R4000SC, R4400SC, R10000 and R12000 invalidating the
 558          * secondary cache will result in any entries in the primary caches
 559          * also getting invalidated which hopefully is a bit more economical.
 560          */
 561         if (cpu_has_subset_pcaches) {
 562                 unsigned long addr = (unsigned long) page_address(page);
 563
 564                 r4k_blast_scache_page(addr);
 565                 ClearPageDcacheDirty(page);
 566
 567                 return;
 568         }
 569
 570         if (!cpu_has_ic_fills_f_dc) {
 571                 unsigned long addr = (unsigned long) page_address(page);
 572                 r4k_blast_dcache_page(addr);
 573                 if (!cpu_icache_snoops_remote_store)
 574                         r4k_blast_scache_page(addr);
 575                 ClearPageDcacheDirty(page);
 576         }
 577
 578         /*
 579          * We're not sure of the virtual address(es) involved here, so
 580          * we have to flush the entire I-cache.
 581          */
 582         if (cpu_has_vtag_icache) {
 583                 int cpu = smp_processor_id();
 584
 585                 if (cpu_context(cpu, vma->vm_mm) != 0)
 586                         drop_mmu_context(vma->vm_mm, cpu);
 587         } else
 588                 r4k_blast_icache();
 589 }
 590
 591 static void r4k_flush_icache_page(struct vm_area_struct *vma,
 592         struct page *page)
 593 {
 594         struct flush_icache_page_args args;
 595
 596         /*
 597          * If there's no context yet, or the page isn't executable, no I-cache
 598          * flush is needed.
 599          */
 600         if (!(vma->vm_flags & VM_EXEC))
 601                 return;
 602
 603         args.vma = vma;
 604         args.page = page;
 605
 606         on_each_cpu(local_r4k_flush_icache_page, &args, 1, 1);
 607 }
 608
 609
 610 #ifdef CONFIG_DMA_NONCOHERENT
 611
 612 static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
 613 {
 614         unsigned long end, a;
 615
 616         /* Catch bad driver code */
 617         BUG_ON(size == 0);
 618
 619         if (cpu_has_subset_pcaches) {
 620                 unsigned long sc_lsize = current_cpu_data.scache.linesz;
 621
 622                 if (size >= scache_size) {
 623                         r4k_blast_scache();
 624                         return;
 625                 }
 626
 627                 a = addr & ~(sc_lsize - 1);
 628                 end = (addr + size - 1) & ~(sc_lsize - 1);
 629                 while (1) {
 630                         flush_scache_line(a);   /* Hit_Writeback_Inv_SD */
 631                         if (a == end)
 632                                 break;
 633                         a += sc_lsize;
 634                 }
 635                 return;
 636         }
 637
 638         /*
 639          * Either no secondary cache or the available caches don't have the
 640          * subset property so we have to flush the primary caches
 641          * explicitly
 642          */
 643         if (size >= dcache_size) {
 644                 r4k_blast_dcache();
 645         } else {
 646                 unsigned long dc_lsize = current_cpu_data.dcache.linesz;
 647
 648                 R4600_HIT_CACHEOP_WAR_IMPL;
 649                 a = addr & ~(dc_lsize - 1);
 650                 end = (addr + size - 1) & ~(dc_lsize - 1);
 651                 while (1) {
 652                         flush_dcache_line(a);   /* Hit_Writeback_Inv_D */
 653                         if (a == end)
 654                                 break;
 655                         a += dc_lsize;
 656                 }
 657         }
 658
 659         bc_wback_inv(addr, size);
 660 }
 661
 662 static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
 663 {
 664         unsigned long end, a;
 665
 666         /* Catch bad driver code */
 667         BUG_ON(size == 0);
 668
 669         if (cpu_has_subset_pcaches) {
 670                 unsigned long sc_lsize = current_cpu_data.scache.linesz;
 671
 672                 if (size >= scache_size) {
 673                         r4k_blast_scache();
 674                         return;
 675                 }
 676
 677                 a = addr & ~(sc_lsize - 1);
 678                 end = (addr + size - 1) & ~(sc_lsize - 1);
 679                 while (1) {
 680                         flush_scache_line(a);   /* Hit_Writeback_Inv_SD */
 681                         if (a == end)
 682                                 break;
 683                         a += sc_lsize;
 684                 }
 685                 return;
 686         }
 687
 688         if (size >= dcache_size) {
 689                 r4k_blast_dcache();
 690         } else {
 691                 unsigned long dc_lsize = current_cpu_data.dcache.linesz;
 692
 693                 R4600_HIT_CACHEOP_WAR_IMPL;
 694                 a = addr & ~(dc_lsize - 1);
 695                 end = (addr + size - 1) & ~(dc_lsize - 1);
 696                 while (1) {
 697                         flush_dcache_line(a);   /* Hit_Writeback_Inv_D */
 698                         if (a == end)
 699                                 break;
 700                         a += dc_lsize;
 701                 }
 702         }
 703
 704         bc_inv(addr, size);
 705 }
 706 #endif /* CONFIG_DMA_NONCOHERENT */
 707
 708 /*
 709  * While we're protected against bad userland addresses we don't care
 710  * very much about what happens in that case.  Usually a segmentation
 711  * fault will dump the process later on anyway ...
 712  */
 713 static void local_r4k_flush_cache_sigtramp(void * arg)
 714 {
 715         unsigned long ic_lsize = current_cpu_data.icache.linesz;
 716         unsigned long dc_lsize = current_cpu_data.dcache.linesz;
 717         unsigned long sc_lsize = current_cpu_data.scache.linesz;
 718         unsigned long addr = (unsigned long) arg;
 719
 720         R4600_HIT_CACHEOP_WAR_IMPL;
 721         protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
 722         if (!cpu_icache_snoops_remote_store)
 723                 protected_writeback_scache_line(addr & ~(sc_lsize - 1));
 724         protected_flush_icache_line(addr & ~(ic_lsize - 1));
 725         if (MIPS4K_ICACHE_REFILL_WAR) {
 726                 __asm__ __volatile__ (
 727                         ".set push\n\t"
 728                         ".set noat\n\t"
 729                         ".set mips3\n\t"
 730 #ifdef CONFIG_32BIT
 731                         "la     $at,1f\n\t"
 732 #endif
 733 #ifdef CONFIG_64BIT
 734                         "dla    $at,1f\n\t"
 735 #endif
 736                         "cache  %0,($at)\n\t"
 737                         "nop; nop; nop\n"
 738                         "1:\n\t"
 739                         ".set pop"
 740                         :
 741                         : "i" (Hit_Invalidate_I));
 742         }
 743         if (MIPS_CACHE_SYNC_WAR)
 744                 __asm__ __volatile__ ("sync");
 745 }
 746
 747 static void r4k_flush_cache_sigtramp(unsigned long addr)
 748 {
 749         on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr, 1, 1);
 750 }
 751
 752 static void r4k_flush_icache_all(void)
 753 {
 754         if (cpu_has_vtag_icache)
 755                 r4k_blast_icache();
 756 }
 757
 758 static inline void rm7k_erratum31(void)
 759 {
 760         const unsigned long ic_lsize = 32;
 761         unsigned long addr;
 762
 763         /* RM7000 erratum #31. The icache is screwed at startup. */
 764         write_c0_taglo(0);
 765         write_c0_taghi(0);
 766
 767         for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) {
 768                 __asm__ __volatile__ (
 769                         ".set noreorder\n\t"
 770                         ".set mips3\n\t"
 771                         "cache\t%1, 0(%0)\n\t"
 772                         "cache\t%1, 0x1000(%0)\n\t"
 773                         "cache\t%1, 0x2000(%0)\n\t"
 774                         "cache\t%1, 0x3000(%0)\n\t"
 775                         "cache\t%2, 0(%0)\n\t"
 776                         "cache\t%2, 0x1000(%0)\n\t"
 777                         "cache\t%2, 0x2000(%0)\n\t"
 778                         "cache\t%2, 0x3000(%0)\n\t"
 779                         "cache\t%1, 0(%0)\n\t"
 780                         "cache\t%1, 0x1000(%0)\n\t"
 781                         "cache\t%1, 0x2000(%0)\n\t"
 782                         "cache\t%1, 0x3000(%0)\n\t"
 783                         ".set\tmips0\n\t"
 784                         ".set\treorder\n\t"
 785                         :
 786                         : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill));
 787         }
 788 }
 789
 790 static char *way_string[] __initdata = { NULL, "direct mapped", "2-way",
 791         "3-way", "4-way", "5-way", "6-way", "7-way", "8-way"
 792 };
 793
 794 static void __init probe_pcache(void)
 795 {
 796         struct cpuinfo_mips *c = &current_cpu_data;
 797         unsigned int config = read_c0_config();
 798         unsigned int prid = read_c0_prid();
 799         unsigned long config1;
 800         unsigned int lsize;
 801
 802         switch (c->cputype) {
 803         case CPU_R4600:                 /* QED style two way caches? */
 804         case CPU_R4700:
 805         case CPU_R5000:
 806         case CPU_NEVADA:
 807                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 808                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 809                 c->icache.ways = 2;
 810                 c->icache.waybit = ffs(icache_size/2) - 1;
 811
 812                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 813                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 814                 c->dcache.ways = 2;
 815                 c->dcache.waybit= ffs(dcache_size/2) - 1;
 816
 817                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 818                 break;
 819
 820         case CPU_R5432:
 821         case CPU_R5500:
 822                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 823                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 824                 c->icache.ways = 2;
 825                 c->icache.waybit= 0;
 826
 827                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 828                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 829                 c->dcache.ways = 2;
 830                 c->dcache.waybit = 0;
 831
 832                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 833                 break;
 834
 835         case CPU_TX49XX:
 836                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 837                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 838                 c->icache.ways = 4;
 839                 c->icache.waybit= 0;
 840
 841                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 842                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 843                 c->dcache.ways = 4;
 844                 c->dcache.waybit = 0;
 845
 846                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 847                 break;
 848
 849         case CPU_R4000PC:
 850         case CPU_R4000SC:
 851         case CPU_R4000MC:
 852         case CPU_R4400PC:
 853         case CPU_R4400SC:
 854         case CPU_R4400MC:
 855         case CPU_R4300:
 856                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 857                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 858                 c->icache.ways = 1;
 859                 c->icache.waybit = 0;   /* doesn't matter */
 860
 861                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 862                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 863                 c->dcache.ways = 1;
 864                 c->dcache.waybit = 0;   /* does not matter */
 865
 866                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 867                 break;
 868
 869         case CPU_R10000:
 870         case CPU_R12000:
 871                 icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29));
 872                 c->icache.linesz = 64;
 873                 c->icache.ways = 2;
 874                 c->icache.waybit = 0;
 875
 876                 dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26));
 877                 c->dcache.linesz = 32;
 878                 c->dcache.ways = 2;
 879                 c->dcache.waybit = 0;
 880
 881                 c->options |= MIPS_CPU_PREFETCH;
 882                 break;
 883
 884         case CPU_VR4133:
 885                 write_c0_config(config & ~CONF_EB);
 886         case CPU_VR4131:
 887                 /* Workaround for cache instruction bug of VR4131 */
 888                 if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U ||
 889                     c->processor_id == 0x0c82U) {
 890                         config &= ~0x00000030U;
 891                         config |= 0x00410000U;
 892                         write_c0_config(config);
 893                 }
 894                 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
 895                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 896                 c->icache.ways = 2;
 897                 c->icache.waybit = ffs(icache_size/2) - 1;
 898
 899                 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
 900                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 901                 c->dcache.ways = 2;
 902                 c->dcache.waybit = ffs(dcache_size/2) - 1;
 903
 904                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 905                 break;
 906
 907         case CPU_VR41XX:
 908         case CPU_VR4111:
 909         case CPU_VR4121:
 910         case CPU_VR4122:
 911         case CPU_VR4181:
 912         case CPU_VR4181A:
 913                 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
 914                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 915                 c->icache.ways = 1;
 916                 c->icache.waybit = 0;   /* doesn't matter */
 917
 918                 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
 919                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 920                 c->dcache.ways = 1;
 921                 c->dcache.waybit = 0;   /* does not matter */
 922
 923                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 924                 break;
 925
 926         case CPU_RM7000:
 927                 rm7k_erratum31();
 928
 929         case CPU_RM9000:
 930                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 931                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 932                 c->icache.ways = 4;
 933                 c->icache.waybit = ffs(icache_size / c->icache.ways) - 1;
 934
 935                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 936                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 937                 c->dcache.ways = 4;
 938                 c->dcache.waybit = ffs(dcache_size / c->dcache.ways) - 1;
 939
 940 #if !defined(CONFIG_SMP) || !defined(RM9000_CDEX_SMP_WAR)
 941                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 942 #endif
 943                 c->options |= MIPS_CPU_PREFETCH;
 944                 break;
 945
 946         default:
 947                 if (!(config & MIPS_CONF_M))
 948                         panic("Don't know how to probe P-caches on this cpu.");
 949
 950                 /*
 951                  * So we seem to be a MIPS32 or MIPS64 CPU
 952                  * So let's probe the I-cache ...
 953                  */
 954                 config1 = read_c0_config1();
 955
 956                 if ((lsize = ((config1 >> 19) & 7)))
 957                         c->icache.linesz = 2 << lsize;
 958                 else
 959                         c->icache.linesz = lsize;
 960                 c->icache.sets = 64 << ((config1 >> 22) & 7);
 961                 c->icache.ways = 1 + ((config1 >> 16) & 7);
 962
 963                 icache_size = c->icache.sets *
 964                               c->icache.ways *
 965                               c->icache.linesz;
 966                 c->icache.waybit = ffs(icache_size/c->icache.ways) - 1;
 967
 968                 if (config & 0x8)               /* VI bit */
 969                         c->icache.flags |= MIPS_CACHE_VTAG;
 970
 971                 /*
 972                  * Now probe the MIPS32 / MIPS64 data cache.
 973                  */
 974                 c->dcache.flags = 0;
 975
 976                 if ((lsize = ((config1 >> 10) & 7)))
 977                         c->dcache.linesz = 2 << lsize;
 978                 else
 979                         c->dcache.linesz= lsize;
 980                 c->dcache.sets = 64 << ((config1 >> 13) & 7);
 981                 c->dcache.ways = 1 + ((config1 >> 7) & 7);
 982
 983                 dcache_size = c->dcache.sets *
 984                               c->dcache.ways *
 985                               c->dcache.linesz;
 986                 c->dcache.waybit = ffs(dcache_size/c->dcache.ways) - 1;
 987
 988                 c->options |= MIPS_CPU_PREFETCH;
 989                 break;
 990         }
 991
 992         /*
 993          * Processor configuration sanity check for the R4000SC erratum
 994          * #5.  With page sizes larger than 32kB there is no possibility
 995          * to get a VCE exception anymore so we don't care about this
 996          * misconfiguration.  The case is rather theoretical anyway;
 997          * presumably no vendor is shipping his hardware in the "bad"
 998          * configuration.
 999          */
1000         if ((prid & 0xff00) == PRID_IMP_R4000 && (prid & 0xff) < 0x40 &&
1001             !(config & CONF_SC) && c->icache.linesz != 16 &&
1002             PAGE_SIZE <= 0x8000)
1003                 panic("Improper R4000SC processor configuration detected");
1004
1005         /* compute a couple of other cache variables */
1006         c->icache.waysize = icache_size / c->icache.ways;
1007         c->dcache.waysize = dcache_size / c->dcache.ways;
1008
1009         c->icache.sets = icache_size / (c->icache.linesz * c->icache.ways);
1010         c->dcache.sets = dcache_size / (c->dcache.linesz * c->dcache.ways);
1011
1012         /*
1013          * R10000 and R12000 P-caches are odd in a positive way.  They're 32kB
1014          * 2-way virtually indexed so normally would suffer from aliases.  So
1015          * normally they'd suffer from aliases but magic in the hardware deals
1016          * with that for us so we don't need to take care ourselves.
1017          */
1018         switch (c->cputype) {
1019         case CPU_20KC:
1020         case CPU_25KF:
1021         case CPU_R10000:
1022         case CPU_R12000:
1023         case CPU_SB1:
1024                 break;
1025         case CPU_24K:
1026                 if (!(read_c0_config7() & (1 << 16)))
1027         default:
1028                         if (c->dcache.waysize > PAGE_SIZE)
1029                                 c->dcache.flags |= MIPS_CACHE_ALIASES;
1030         }
1031
1032         switch (c->cputype) {
1033         case CPU_20KC:
1034                 /*
1035                  * Some older 20Kc chips doesn't have the 'VI' bit in
1036                  * the config register.
1037                  */
1038                 c->icache.flags |= MIPS_CACHE_VTAG;
1039                 break;
1040
1041         case CPU_AU1000:
1042         case CPU_AU1500:
1043         case CPU_AU1100:
1044         case CPU_AU1550:
1045         case CPU_AU1200:
1046                 c->icache.flags |= MIPS_CACHE_IC_F_DC;
1047                 break;
1048         }
1049
1050         printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
1051                icache_size >> 10,
1052                cpu_has_vtag_icache ? "virtually tagged" : "physically tagged",
1053                way_string[c->icache.ways], c->icache.linesz);
1054
1055         printk("Primary data cache %ldkB, %s, linesize %d bytes.\n",
1056                dcache_size >> 10, way_string[c->dcache.ways], c->dcache.linesz);
1057 }
1058
1059 /*
1060  * If you even _breathe_ on this function, look at the gcc output and make sure
1061  * it does not pop things on and off the stack for the cache sizing loop that
1062  * executes in KSEG1 space or else you will crash and burn badly.  You have
1063  * been warned.
1064  */
1065 static int __init probe_scache(void)
1066 {
1067         extern unsigned long stext;
1068         unsigned long flags, addr, begin, end, pow2;
1069         unsigned int config = read_c0_config();
1070         struct cpuinfo_mips *c = &current_cpu_data;
1071         int tmp;
1072
1073         if (config & CONF_SC)
1074                 return 0;
1075
1076         begin = (unsigned long) &stext;
1077         begin &= ~((4 * 1024 * 1024) - 1);
1078         end = begin + (4 * 1024 * 1024);
1079
1080         /*
1081          * This is such a bitch, you'd think they would make it easy to do
1082          * this.  Away you daemons of stupidity!
1083          */
1084         local_irq_save(flags);
1085
1086         /* Fill each size-multiple cache line with a valid tag. */
1087         pow2 = (64 * 1024);
1088         for (addr = begin; addr < end; addr = (begin + pow2)) {
1089                 unsigned long *p = (unsigned long *) addr;
1090                 __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */
1091                 pow2 <<= 1;
1092         }
1093
1094         /* Load first line with zero (therefore invalid) tag. */
1095         write_c0_taglo(0);
1096         write_c0_taghi(0);
1097         __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */
1098         cache_op(Index_Store_Tag_I, begin);
1099         cache_op(Index_Store_Tag_D, begin);
1100         cache_op(Index_Store_Tag_SD, begin);
1101
1102         /* Now search for the wrap around point. */
1103         pow2 = (128 * 1024);
1104         tmp = 0;
1105         for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) {
1106                 cache_op(Index_Load_Tag_SD, addr);
1107                 __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */
1108                 if (!read_c0_taglo())
1109                         break;
1110                 pow2 <<= 1;
1111         }
1112         local_irq_restore(flags);
1113         addr -= begin;
1114
1115         scache_size = addr;
1116         c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22);
1117         c->scache.ways = 1;
1118         c->dcache.waybit = 0;           /* does not matter */
1119
1120         return 1;
1121 }
1122
1123 extern int r5k_sc_init(void);
1124 extern int rm7k_sc_init(void);
1125
1126 static void __init setup_scache(void)
1127 {
1128         struct cpuinfo_mips *c = &current_cpu_data;
1129         unsigned int config = read_c0_config();
1130         int sc_present = 0;
1131
1132         /*
1133          * Do the probing thing on R4000SC and R4400SC processors.  Other
1134          * processors don't have a S-cache that would be relevant to the
1135          * Linux memory managment.
1136          */
1137         switch (c->cputype) {
1138         case CPU_R4000SC:
1139         case CPU_R4000MC:
1140         case CPU_R4400SC:
1141         case CPU_R4400MC:
1142                 sc_present = run_uncached(probe_scache);
1143                 if (sc_present)
1144                         c->options |= MIPS_CPU_CACHE_CDEX_S;
1145                 break;
1146
1147         case CPU_R10000:
1148         case CPU_R12000:
1149                 scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16);
1150                 c->scache.linesz = 64 << ((config >> 13) & 1);
1151                 c->scache.ways = 2;
1152                 c->scache.waybit= 0;
1153                 sc_present = 1;
1154                 break;
1155
1156         case CPU_R5000:
1157         case CPU_NEVADA:
1158 #ifdef CONFIG_R5000_CPU_SCACHE
1159                 r5k_sc_init();
1160 #endif
1161                 return;
1162
1163         case CPU_RM7000:
1164         case CPU_RM9000:
1165 #ifdef CONFIG_RM7000_CPU_SCACHE
1166                 rm7k_sc_init();
1167 #endif
1168                 return;
1169
1170         default:
1171                 sc_present = 0;
1172         }
1173
1174         if (!sc_present)
1175                 return;
1176
1177         if ((c->isa_level == MIPS_CPU_ISA_M32 ||
1178              c->isa_level == MIPS_CPU_ISA_M64) &&
1179             !(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
1180                 panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
1181
1182         /* compute a couple of other cache variables */
1183         c->scache.waysize = scache_size / c->scache.ways;
1184
1185         c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1186
1187         printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1188                scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1189
1190         c->options |= MIPS_CPU_SUBSET_CACHES;
1191 }
1192
1193 static inline void coherency_setup(void)
1194 {
1195         change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
1196
1197         /*
1198          * c0_status.cu=0 specifies that updates by the sc instruction use
1199          * the coherency mode specified by the TLB; 1 means cachable
1200          * coherent update on write will be used.  Not all processors have
1201          * this bit and; some wire it to zero, others like Toshiba had the
1202          * silly idea of putting something else there ...
1203          */
1204         switch (current_cpu_data.cputype) {
1205         case CPU_R4000PC:
1206         case CPU_R4000SC:
1207         case CPU_R4000MC:
1208         case CPU_R4400PC:
1209         case CPU_R4400SC:
1210         case CPU_R4400MC:
1211                 clear_c0_config(CONF_CU);
1212                 break;
1213         }
1214 }
1215
1216 void __init ld_mmu_r4xx0(void)
1217 {
1218         extern void build_clear_page(void);
1219         extern void build_copy_page(void);
1220         extern char except_vec2_generic;
1221         struct cpuinfo_mips *c = &current_cpu_data;
1222
1223         /* Default cache error handler for R4000 and R5000 family */
1224         memcpy((void *)(CAC_BASE   + 0x100), &except_vec2_generic, 0x80);
1225         memcpy((void *)(UNCAC_BASE + 0x100), &except_vec2_generic, 0x80);
1226
1227         probe_pcache();
1228         setup_scache();
1229
1230         r4k_blast_dcache_page_setup();
1231         r4k_blast_dcache_page_indexed_setup();
1232         r4k_blast_dcache_setup();
1233         r4k_blast_icache_page_setup();
1234         r4k_blast_icache_page_indexed_setup();
1235         r4k_blast_icache_setup();
1236         r4k_blast_scache_page_setup();
1237         r4k_blast_scache_page_indexed_setup();
1238         r4k_blast_scache_setup();
1239
1240         /*
1241          * Some MIPS32 and MIPS64 processors have physically indexed caches.
1242          * This code supports virtually indexed processors and will be
1243          * unnecessarily inefficient on physically indexed processors.
1244          */
1245         shm_align_mask = max_t( unsigned long,
1246                                 c->dcache.sets * c->dcache.linesz - 1,
1247                                 PAGE_SIZE - 1);
1248
1249         flush_cache_all         = r4k_flush_cache_all;
1250         __flush_cache_all       = r4k___flush_cache_all;
1251         flush_cache_mm          = r4k_flush_cache_mm;
1252         flush_cache_page        = r4k_flush_cache_page;
1253         flush_icache_page       = r4k_flush_icache_page;
1254         flush_cache_range       = r4k_flush_cache_range;
1255
1256         flush_cache_sigtramp    = r4k_flush_cache_sigtramp;
1257         flush_icache_all        = r4k_flush_icache_all;
1258         flush_data_cache_page   = r4k_flush_data_cache_page;
1259         flush_icache_range      = r4k_flush_icache_range;
1260
1261 #ifdef CONFIG_DMA_NONCOHERENT
1262         _dma_cache_wback_inv    = r4k_dma_cache_wback_inv;
1263         _dma_cache_wback        = r4k_dma_cache_wback_inv;
1264         _dma_cache_inv          = r4k_dma_cache_inv;
1265 #endif
1266
1267         __flush_cache_all();
1268         coherency_setup();
1269
1270         build_clear_page();
1271         build_copy_page();
1272 }