SAFE public projects git trees. - safe/jmp/linux-2.6/blob - arch/mips/mips-boards/generic/time.c

   1 /*
   2  * Carsten Langgaard, carstenl@mips.com
   3  * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
   4  *
   5  *  This program is free software; you can distribute it and/or modify it
   6  *  under the terms of the GNU General Public License (Version 2) as
   7  *  published by the Free Software Foundation.
   8  *
   9  *  This program is distributed in the hope it will be useful, but WITHOUT
  10  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  *  for more details.
  13  *
  14  *  You should have received a copy of the GNU General Public License along
  15  *  with this program; if not, write to the Free Software Foundation, Inc.,
  16  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  17  *
  18  * Setting up the clock on the MIPS boards.
  19  */
  20
  21 #include <linux/types.h>
  22 #include <linux/init.h>
  23 #include <linux/kernel_stat.h>
  24 #include <linux/sched.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/time.h>
  28 #include <linux/timex.h>
  29 #include <linux/mc146818rtc.h>
  30
  31 #include <asm/mipsregs.h>
  32 #include <asm/mipsmtregs.h>
  33 #include <asm/hardirq.h>
  34 #include <asm/i8253.h>
  35 #include <asm/irq.h>
  36 #include <asm/div64.h>
  37 #include <asm/cpu.h>
  38 #include <asm/time.h>
  39 #include <asm/mc146818-time.h>
  40 #include <asm/msc01_ic.h>
  41
  42 #include <asm/mips-boards/generic.h>
  43 #include <asm/mips-boards/prom.h>
  44
  45 #ifdef CONFIG_MIPS_MALTA
  46 #include <asm/mips-boards/maltaint.h>
  47 #endif
  48
  49 unsigned long cpu_khz;
  50
  51 static int mips_cpu_timer_irq;
  52 static int mips_cpu_perf_irq;
  53 extern int cp0_perfcount_irq;
  54
  55 static void mips_timer_dispatch(void)
  56 {
  57         do_IRQ(mips_cpu_timer_irq);
  58 }
  59
  60 static void mips_perf_dispatch(void)
  61 {
  62         do_IRQ(mips_cpu_perf_irq);
  63 }
  64
  65 /*
  66  * Estimate CPU frequency.  Sets mips_hpt_frequency as a side-effect
  67  */
  68 static unsigned int __init estimate_cpu_frequency(void)
  69 {
  70         unsigned int prid = read_c0_prid() & 0xffff00;
  71         unsigned int count;
  72
  73 #ifdef CONFIG_MIPS_SIM
  74         /*
  75          * The SEAD board doesn't have a real time clock, so we can't
  76          * really calculate the timer frequency
  77          * For now we hardwire the SEAD board frequency to 12MHz.
  78          */
  79
  80         if ((prid == (PRID_COMP_MIPS | PRID_IMP_20KC)) ||
  81             (prid == (PRID_COMP_MIPS | PRID_IMP_25KF)))
  82                 count = 12000000;
  83         else
  84                 count = 6000000;
  85 #endif
  86 #ifdef CONFIG_MIPS_MALTA
  87         unsigned long flags;
  88         unsigned int start;
  89
  90         local_irq_save(flags);
  91
  92         /* Start counter exactly on falling edge of update flag */
  93         while (CMOS_READ(RTC_REG_A) & RTC_UIP);
  94         while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
  95
  96         /* Start r4k counter. */
  97         start = read_c0_count();
  98
  99         /* Read counter exactly on falling edge of update flag */
 100         while (CMOS_READ(RTC_REG_A) & RTC_UIP);
 101         while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
 102
 103         count = read_c0_count() - start;
 104
 105         /* restore interrupts */
 106         local_irq_restore(flags);
 107 #endif
 108
 109         mips_hpt_frequency = count;
 110         if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
 111             (prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
 112                 count *= 2;
 113
 114         count += 5000;    /* round */
 115         count -= count%10000;
 116
 117         return count;
 118 }
 119
 120 unsigned long read_persistent_clock(void)
 121 {
 122         return mc146818_get_cmos_time();
 123 }
 124
 125 static void __init plat_perf_setup(void)
 126 {
 127 #ifdef MSC01E_INT_BASE
 128         if (cpu_has_veic) {
 129                 set_vi_handler(MSC01E_INT_PERFCTR, mips_perf_dispatch);
 130                 mips_cpu_perf_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR;
 131         } else
 132 #endif
 133         if (cp0_perfcount_irq >= 0) {
 134                 if (cpu_has_vint)
 135                         set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch);
 136                 mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
 137 #ifdef CONFIG_SMP
 138                 set_irq_handler(mips_cpu_perf_irq, handle_percpu_irq);
 139 #endif
 140         }
 141 }
 142
 143 unsigned int __cpuinit get_c0_compare_int(void)
 144 {
 145 #ifdef MSC01E_INT_BASE
 146         if (cpu_has_veic) {
 147                 set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch);
 148                 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
 149         } else
 150 #endif
 151         {
 152                 if (cpu_has_vint)
 153                         set_vi_handler(cp0_compare_irq, mips_timer_dispatch);
 154                 mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
 155         }
 156
 157         return mips_cpu_timer_irq;
 158 }
 159
 160 void __init plat_time_init(void)
 161 {
 162         unsigned int est_freq;
 163
 164         /* Set Data mode - binary. */
 165         CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
 166
 167         est_freq = estimate_cpu_frequency();
 168
 169         printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
 170                (est_freq%1000000)*100/1000000);
 171
 172         cpu_khz = est_freq / 1000;
 173
 174         mips_scroll_message();
 175 #ifdef CONFIG_I8253             /* Only Malta has a PIT */
 176         setup_pit_timer();
 177 #endif
 178
 179         plat_perf_setup();
 180 }