3 * BRIEF MODULE DESCRIPTION
4 * Alchemy Db1x00 board setup.
6 * Copyright 2000, 2008 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc. <source@mvista.com>
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
30 #include <linux/gpio.h>
31 #include <linux/init.h>
32 #include <linux/interrupt.h>
34 #include <asm/mach-au1x00/au1000.h>
35 #include <asm/mach-db1x00/db1x00.h>
36 #include <asm/mach-db1x00/bcsr.h>
40 #ifdef CONFIG_MIPS_DB1500
41 char irq_tab_alchemy[][5] __initdata = {
42 [12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - HPT371 */
43 [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */
47 #ifdef CONFIG_MIPS_BOSPORUS
48 char irq_tab_alchemy[][5] __initdata = {
49 [11] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 11 - miniPCI */
50 [12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - SN1741 */
51 [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */
55 #ifdef CONFIG_MIPS_MIRAGE
56 char irq_tab_alchemy[][5] __initdata = {
57 [11] = { -1, AU1500_PCI_INTD, 0xff, 0xff, 0xff }, /* IDSEL 11 - SMI VGX */
58 [12] = { -1, 0xff, 0xff, AU1500_PCI_INTC, 0xff }, /* IDSEL 12 - PNX1300 */
59 [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 13 - miniPCI */
63 #ifdef CONFIG_MIPS_DB1550
64 char irq_tab_alchemy[][5] __initdata = {
65 [11] = { -1, AU1550_PCI_INTC, 0xff, 0xff, 0xff }, /* IDSEL 11 - on-board HPT371 */
66 [12] = { -1, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD, AU1550_PCI_INTA }, /* IDSEL 12 - PCI slot 2 (left) */
67 [13] = { -1, AU1550_PCI_INTA, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD }, /* IDSEL 13 - PCI slot 1 (right) */
71 const char *get_system_type(void)
73 #ifdef CONFIG_MIPS_BOSPORUS
74 return "Alchemy Bosporus Gateway Reference";
76 return "Alchemy Db1x00";
80 void board_reset(void)
82 bcsr_write(BCSR_SYSTEM, 0);
85 void __init board_setup(void)
87 unsigned long bcsr1, bcsr2;
91 bcsr1 = DB1000_BCSR_PHYS_ADDR;
92 bcsr2 = DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS;
96 #ifdef CONFIG_MIPS_DB1000
97 printk(KERN_INFO "AMD Alchemy Au1000/Db1000 Board\n");
99 #ifdef CONFIG_MIPS_DB1500
100 printk(KERN_INFO "AMD Alchemy Au1500/Db1500 Board\n");
102 #ifdef CONFIG_MIPS_DB1100
103 printk(KERN_INFO "AMD Alchemy Au1100/Db1100 Board\n");
105 #ifdef CONFIG_MIPS_BOSPORUS
106 printk(KERN_INFO "AMD Alchemy Bosporus Board\n");
108 #ifdef CONFIG_MIPS_MIRAGE
109 printk(KERN_INFO "AMD Alchemy Mirage Board\n");
111 #ifdef CONFIG_MIPS_DB1550
112 printk(KERN_INFO "AMD Alchemy Au1550/Db1550 Board\n");
114 bcsr1 = DB1550_BCSR_PHYS_ADDR;
115 bcsr2 = DB1550_BCSR_PHYS_ADDR + DB1550_BCSR_HEXLED_OFS;
118 /* initialize board register space */
119 bcsr_init(bcsr1, bcsr2);
121 argptr = prom_getcmdline();
122 #ifdef CONFIG_SERIAL_8250_CONSOLE
123 argptr = strstr(argptr, "console=");
124 if (argptr == NULL) {
125 argptr = prom_getcmdline();
126 strcat(argptr, " console=ttyS0,115200");
130 #ifdef CONFIG_FB_AU1100
131 argptr = strstr(argptr, "video=");
132 if (argptr == NULL) {
133 argptr = prom_getcmdline();
135 /*strcat(argptr, " video=au1100fb:panel:Sharp_320x240_16");*/
139 #if defined(CONFIG_SOUND_AU1X00) && !defined(CONFIG_SOC_AU1000)
140 /* au1000 does not support vra, au1500 and au1100 do */
141 strcat(argptr, " au1000_audio=vra");
142 argptr = prom_getcmdline();
145 /* Not valid for Au1550 */
146 #if defined(CONFIG_IRDA) && \
147 (defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1100))
148 /* Set IRFIRSEL instead of GPIO15 */
149 pin_func = au_readl(SYS_PINFUNC) | SYS_PF_IRF;
150 au_writel(pin_func, SYS_PINFUNC);
151 /* Power off until the driver is in use */
152 bcsr_mod(BCSR_RESETS, BCSR_RESETS_IRDA_MODE_MASK,
153 BCSR_RESETS_IRDA_MODE_OFF);
155 bcsr_write(BCSR_PCMCIA, 0); /* turn off PCMCIA power */
157 /* Enable GPIO[31:0] inputs */
158 alchemy_gpio1_input_enable();
160 #ifdef CONFIG_MIPS_MIRAGE
161 /* GPIO[20] is output */
162 alchemy_gpio_direction_output(20, 0);
164 /* Set GPIO[210:208] instead of SSI_0 */
165 pin_func = au_readl(SYS_PINFUNC) | SYS_PF_S0;
167 /* Set GPIO[215:211] for LEDs */
170 /* Set GPIO[214:213] for more LEDs */
173 /* Set GPIO[207:200] instead of PCMCIA/LCD */
174 pin_func |= SYS_PF_LCD | SYS_PF_PC;
175 au_writel(pin_func, SYS_PINFUNC);
178 * Enable speaker amplifier. This should
179 * be part of the audio driver.
181 alchemy_gpio_direction_output(209, 1);
187 static int __init db1x00_init_irq(void)
189 #if defined(CONFIG_MIPS_MIRAGE)
190 set_irq_type(AU1500_GPIO7_INT, IRQF_TRIGGER_RISING); /* TS pendown */
191 #elif defined(CONFIG_MIPS_DB1550)
192 set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
193 set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW); /* CD1# */
194 set_irq_type(AU1550_GPIO3_INT, IRQF_TRIGGER_LOW); /* CARD0# */
195 set_irq_type(AU1550_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
196 set_irq_type(AU1550_GPIO21_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
197 set_irq_type(AU1550_GPIO22_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
198 #elif defined(CONFIG_MIPS_DB1500)
199 set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
200 set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
201 set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
202 set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
203 set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
204 set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
205 #elif defined(CONFIG_MIPS_DB1100)
206 set_irq_type(AU1100_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
207 set_irq_type(AU1100_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
208 set_irq_type(AU1100_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
209 set_irq_type(AU1100_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
210 set_irq_type(AU1100_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
211 set_irq_type(AU1100_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
212 #elif defined(CONFIG_MIPS_DB1000)
213 set_irq_type(AU1000_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
214 set_irq_type(AU1000_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
215 set_irq_type(AU1000_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
216 set_irq_type(AU1000_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
217 set_irq_type(AU1000_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
218 set_irq_type(AU1000_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
222 arch_initcall(db1x00_init_irq);