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   1 /*
   2  * I/O SAPIC support.
   3  *
   4  * Copyright (C) 1999 Intel Corp.
   5  * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
   6  * Copyright (C) 2000-2002 J.I. Lee <jung-ik.lee@intel.com>
   7  * Copyright (C) 1999-2000, 2002-2003 Hewlett-Packard Co.
   8  *      David Mosberger-Tang <davidm@hpl.hp.com>
   9  * Copyright (C) 1999 VA Linux Systems
  10  * Copyright (C) 1999,2000 Walt Drummond <drummond@valinux.com>
  11  *
  12  * 00/04/19     D. Mosberger    Rewritten to mirror more closely the x86 I/O
  13  *                              APIC code.  In particular, we now have separate
  14  *                              handlers for edge and level triggered
  15  *                              interrupts.
  16  * 00/10/27     Asit Mallick, Goutham Rao <goutham.rao@intel.com> IRQ vector
  17  *                              allocation PCI to vector mapping, shared PCI
  18  *                              interrupts.
  19  * 00/10/27     D. Mosberger    Document things a bit more to make them more
  20  *                              understandable.  Clean up much of the old
  21  *                              IOSAPIC cruft.
  22  * 01/07/27     J.I. Lee        PCI irq routing, Platform/Legacy interrupts
  23  *                              and fixes for ACPI S5(SoftOff) support.
  24  * 02/01/23     J.I. Lee        iosapic pgm fixes for PCI irq routing from _PRT
  25  * 02/01/07     E. Focht        <efocht@ess.nec.de> Redirectable interrupt
  26  *                              vectors in iosapic_set_affinity(),
  27  *                              initializations for /proc/irq/#/smp_affinity
  28  * 02/04/02     P. Diefenbaugh  Cleaned up ACPI PCI IRQ routing.
  29  * 02/04/18     J.I. Lee        bug fix in iosapic_init_pci_irq
  30  * 02/04/30     J.I. Lee        bug fix in find_iosapic to fix ACPI PCI IRQ to
  31  *                              IOSAPIC mapping error
  32  * 02/07/29     T. Kochi        Allocate interrupt vectors dynamically
  33  * 02/08/04     T. Kochi        Cleaned up terminology (irq, global system
  34  *                              interrupt, vector, etc.)
  35  * 02/09/20     D. Mosberger    Simplified by taking advantage of ACPI's
  36  *                              pci_irq code.
  37  * 03/02/19     B. Helgaas      Make pcat_compat system-wide, not per-IOSAPIC.
  38  *                              Remove iosapic_address & gsi_base from
  39  *                              external interfaces.  Rationalize
  40  *                              __init/__devinit attributes.
  41  * 04/12/04 Ashok Raj   <ashok.raj@intel.com> Intel Corporation 2004
  42  *                              Updated to work with irq migration necessary
  43  *                              for CPU Hotplug
  44  */
  45 /*
  46  * Here is what the interrupt logic between a PCI device and the kernel looks
  47  * like:
  48  *
  49  * (1) A PCI device raises one of the four interrupt pins (INTA, INTB, INTC,
  50  *     INTD).  The device is uniquely identified by its bus-, and slot-number
  51  *     (the function number does not matter here because all functions share
  52  *     the same interrupt lines).
  53  *
  54  * (2) The motherboard routes the interrupt line to a pin on a IOSAPIC
  55  *     controller.  Multiple interrupt lines may have to share the same
  56  *     IOSAPIC pin (if they're level triggered and use the same polarity).
  57  *     Each interrupt line has a unique Global System Interrupt (GSI) number
  58  *     which can be calculated as the sum of the controller's base GSI number
  59  *     and the IOSAPIC pin number to which the line connects.
  60  *
  61  * (3) The IOSAPIC uses an internal routing table entries (RTEs) to map the
  62  * IOSAPIC pin into the IA-64 interrupt vector.  This interrupt vector is then
  63  * sent to the CPU.
  64  *
  65  * (4) The kernel recognizes an interrupt as an IRQ.  The IRQ interface is
  66  *     used as architecture-independent interrupt handling mechanism in Linux.
  67  *     As an IRQ is a number, we have to have
  68  *     IA-64 interrupt vector number <-> IRQ number mapping.  On smaller
  69  *     systems, we use one-to-one mapping between IA-64 vector and IRQ.  A
  70  *     platform can implement platform_irq_to_vector(irq) and
  71  *     platform_local_vector_to_irq(vector) APIs to differentiate the mapping.
  72  *     Please see also include/asm-ia64/hw_irq.h for those APIs.
  73  *
  74  * To sum up, there are three levels of mappings involved:
  75  *
  76  *      PCI pin -> global system interrupt (GSI) -> IA-64 vector <-> IRQ
  77  *
  78  * Note: The term "IRQ" is loosely used everywhere in Linux kernel to
  79  * describeinterrupts.  Now we use "IRQ" only for Linux IRQ's.  ISA IRQ
  80  * (isa_irq) is the only exception in this source code.
  81  */
  82
  83 #include <linux/acpi.h>
  84 #include <linux/init.h>
  85 #include <linux/irq.h>
  86 #include <linux/kernel.h>
  87 #include <linux/list.h>
  88 #include <linux/pci.h>
  89 #include <linux/smp.h>
  90 #include <linux/string.h>
  91 #include <linux/bootmem.h>
  92
  93 #include <asm/delay.h>
  94 #include <asm/hw_irq.h>
  95 #include <asm/io.h>
  96 #include <asm/iosapic.h>
  97 #include <asm/machvec.h>
  98 #include <asm/processor.h>
  99 #include <asm/ptrace.h>
 100 #include <asm/system.h>
 101
 102 #undef DEBUG_INTERRUPT_ROUTING
 103
 104 #ifdef DEBUG_INTERRUPT_ROUTING
 105 #define DBG(fmt...)     printk(fmt)
 106 #else
 107 #define DBG(fmt...)
 108 #endif
 109
 110 #define NR_PREALLOCATE_RTE_ENTRIES \
 111         (PAGE_SIZE / sizeof(struct iosapic_rte_info))
 112 #define RTE_PREALLOCATED        (1)
 113
 114 static DEFINE_SPINLOCK(iosapic_lock);
 115
 116 /*
 117  * These tables map IA-64 vectors to the IOSAPIC pin that generates this
 118  * vector.
 119  */
 120 static struct iosapic {
 121         char __iomem    *addr;          /* base address of IOSAPIC */
 122         unsigned int    gsi_base;       /* GSI base */
 123         unsigned short  num_rte;        /* # of RTEs on this IOSAPIC */
 124         int             rtes_inuse;     /* # of RTEs in use on this IOSAPIC */
 125 #ifdef CONFIG_NUMA
 126         unsigned short  node;           /* numa node association via pxm */
 127 #endif
 128         spinlock_t      lock;           /* lock for indirect reg access */
 129 } iosapic_lists[NR_IOSAPICS];
 130
 131 struct iosapic_rte_info {
 132         struct list_head rte_list;      /* RTEs sharing the same vector */
 133         char            rte_index;      /* IOSAPIC RTE index */
 134         int             refcnt;         /* reference counter */
 135         unsigned int    flags;          /* flags */
 136         struct iosapic  *iosapic;
 137 } ____cacheline_aligned;
 138
 139 static struct iosapic_intr_info {
 140         struct list_head rtes;          /* RTEs using this vector (empty =>
 141                                          * not an IOSAPIC interrupt) */
 142         int             count;          /* # of RTEs that shares this vector */
 143         u32             low32;          /* current value of low word of
 144                                          * Redirection table entry */
 145         unsigned int    dest;           /* destination CPU physical ID */
 146         unsigned char   dmode   : 3;    /* delivery mode (see iosapic.h) */
 147         unsigned char   polarity: 1;    /* interrupt polarity
 148                                          * (see iosapic.h) */
 149         unsigned char   trigger : 1;    /* trigger mode (see iosapic.h) */
 150 } iosapic_intr_info[NR_IRQS];
 151
 152 static unsigned char pcat_compat __devinitdata; /* 8259 compatibility flag */
 153
 154 static int iosapic_kmalloc_ok;
 155 static LIST_HEAD(free_rte_list);
 156
 157 static inline void
 158 iosapic_write(struct iosapic *iosapic, unsigned int reg, u32 val)
 159 {
 160         unsigned long flags;
 161
 162         spin_lock_irqsave(&iosapic->lock, flags);
 163         __iosapic_write(iosapic->addr, reg, val);
 164         spin_unlock_irqrestore(&iosapic->lock, flags);
 165 }
 166
 167 /*
 168  * Find an IOSAPIC associated with a GSI
 169  */
 170 static inline int
 171 find_iosapic (unsigned int gsi)
 172 {
 173         int i;
 174
 175         for (i = 0; i < NR_IOSAPICS; i++) {
 176                 if ((unsigned) (gsi - iosapic_lists[i].gsi_base) <
 177                     iosapic_lists[i].num_rte)
 178                         return i;
 179         }
 180
 181         return -1;
 182 }
 183
 184 static inline int __gsi_to_irq(unsigned int gsi)
 185 {
 186         int irq;
 187         struct iosapic_intr_info *info;
 188         struct iosapic_rte_info *rte;
 189
 190         for (irq = 0; irq < NR_IRQS; irq++) {
 191                 info = &iosapic_intr_info[irq];
 192                 list_for_each_entry(rte, &info->rtes, rte_list)
 193                         if (rte->iosapic->gsi_base + rte->rte_index == gsi)
 194                                 return irq;
 195         }
 196         return -1;
 197 }
 198
 199 /*
 200  * Translate GSI number to the corresponding IA-64 interrupt vector.  If no
 201  * entry exists, return -1.
 202  */
 203 inline int
 204 gsi_to_vector (unsigned int gsi)
 205 {
 206         int irq = __gsi_to_irq(gsi);
 207         if (irq < 0)
 208                 return -1;
 209         return irq_to_vector(irq);
 210 }
 211
 212 int
 213 gsi_to_irq (unsigned int gsi)
 214 {
 215         unsigned long flags;
 216         int irq;
 217
 218         spin_lock_irqsave(&iosapic_lock, flags);
 219         irq = __gsi_to_irq(gsi);
 220         spin_unlock_irqrestore(&iosapic_lock, flags);
 221         return irq;
 222 }
 223
 224 static struct iosapic_rte_info *find_rte(unsigned int irq, unsigned int gsi)
 225 {
 226         struct iosapic_rte_info *rte;
 227
 228         list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list)
 229                 if (rte->iosapic->gsi_base + rte->rte_index == gsi)
 230                         return rte;
 231         return NULL;
 232 }
 233
 234 static void
 235 set_rte (unsigned int gsi, unsigned int irq, unsigned int dest, int mask)
 236 {
 237         unsigned long pol, trigger, dmode;
 238         u32 low32, high32;
 239         int rte_index;
 240         char redir;
 241         struct iosapic_rte_info *rte;
 242         ia64_vector vector = irq_to_vector(irq);
 243
 244         DBG(KERN_DEBUG"IOSAPIC: routing vector %d to 0x%x\n", vector, dest);
 245
 246         rte = find_rte(irq, gsi);
 247         if (!rte)
 248                 return;         /* not an IOSAPIC interrupt */
 249
 250         rte_index = rte->rte_index;
 251         pol     = iosapic_intr_info[irq].polarity;
 252         trigger = iosapic_intr_info[irq].trigger;
 253         dmode   = iosapic_intr_info[irq].dmode;
 254
 255         redir = (dmode == IOSAPIC_LOWEST_PRIORITY) ? 1 : 0;
 256
 257 #ifdef CONFIG_SMP
 258         set_irq_affinity_info(irq, (int)(dest & 0xffff), redir);
 259 #endif
 260
 261         low32 = ((pol << IOSAPIC_POLARITY_SHIFT) |
 262                  (trigger << IOSAPIC_TRIGGER_SHIFT) |
 263                  (dmode << IOSAPIC_DELIVERY_SHIFT) |
 264                  ((mask ? 1 : 0) << IOSAPIC_MASK_SHIFT) |
 265                  vector);
 266
 267         /* dest contains both id and eid */
 268         high32 = (dest << IOSAPIC_DEST_SHIFT);
 269
 270         iosapic_write(rte->iosapic, IOSAPIC_RTE_HIGH(rte_index), high32);
 271         iosapic_write(rte->iosapic, IOSAPIC_RTE_LOW(rte_index), low32);
 272         iosapic_intr_info[irq].low32 = low32;
 273         iosapic_intr_info[irq].dest = dest;
 274 }
 275
 276 static void
 277 nop (unsigned int irq)
 278 {
 279         /* do nothing... */
 280 }
 281
 282
 283 #ifdef CONFIG_KEXEC
 284 void
 285 kexec_disable_iosapic(void)
 286 {
 287         struct iosapic_intr_info *info;
 288         struct iosapic_rte_info *rte;
 289         ia64_vector vec;
 290         int irq;
 291
 292         for (irq = 0; irq < NR_IRQS; irq++) {
 293                 info = &iosapic_intr_info[irq];
 294                 vec = irq_to_vector(irq);
 295                 list_for_each_entry(rte, &info->rtes,
 296                                 rte_list) {
 297                         iosapic_write(rte->iosapic,
 298                                         IOSAPIC_RTE_LOW(rte->rte_index),
 299                                         IOSAPIC_MASK|vec);
 300                         iosapic_eoi(rte->iosapic->addr, vec);
 301                 }
 302         }
 303 }
 304 #endif
 305
 306 static void
 307 mask_irq (unsigned int irq)
 308 {
 309         u32 low32;
 310         int rte_index;
 311         struct iosapic_rte_info *rte;
 312
 313         if (list_empty(&iosapic_intr_info[irq].rtes))
 314                 return;                 /* not an IOSAPIC interrupt! */
 315
 316         /* set only the mask bit */
 317         low32 = iosapic_intr_info[irq].low32 |= IOSAPIC_MASK;
 318         list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list) {
 319                 rte_index = rte->rte_index;
 320                 iosapic_write(rte->iosapic, IOSAPIC_RTE_LOW(rte_index), low32);
 321         }
 322 }
 323
 324 static void
 325 unmask_irq (unsigned int irq)
 326 {
 327         u32 low32;
 328         int rte_index;
 329         struct iosapic_rte_info *rte;
 330
 331         if (list_empty(&iosapic_intr_info[irq].rtes))
 332                 return;                 /* not an IOSAPIC interrupt! */
 333
 334         low32 = iosapic_intr_info[irq].low32 &= ~IOSAPIC_MASK;
 335         list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list) {
 336                 rte_index = rte->rte_index;
 337                 iosapic_write(rte->iosapic, IOSAPIC_RTE_LOW(rte_index), low32);
 338         }
 339 }
 340
 341
 342 static void
 343 iosapic_set_affinity (unsigned int irq, cpumask_t mask)
 344 {
 345 #ifdef CONFIG_SMP
 346         u32 high32, low32;
 347         int dest, rte_index;
 348         int redir = (irq & IA64_IRQ_REDIRECTED) ? 1 : 0;
 349         struct iosapic_rte_info *rte;
 350         struct iosapic *iosapic;
 351
 352         irq &= (~IA64_IRQ_REDIRECTED);
 353
 354         if (cpus_empty(mask))
 355                 return;
 356
 357         dest = cpu_physical_id(first_cpu(mask));
 358
 359         if (list_empty(&iosapic_intr_info[irq].rtes))
 360                 return;                 /* not an IOSAPIC interrupt */
 361
 362         set_irq_affinity_info(irq, dest, redir);
 363
 364         /* dest contains both id and eid */
 365         high32 = dest << IOSAPIC_DEST_SHIFT;
 366
 367         low32 = iosapic_intr_info[irq].low32 & ~(7 << IOSAPIC_DELIVERY_SHIFT);
 368         if (redir)
 369                 /* change delivery mode to lowest priority */
 370                 low32 |= (IOSAPIC_LOWEST_PRIORITY << IOSAPIC_DELIVERY_SHIFT);
 371         else
 372                 /* change delivery mode to fixed */
 373                 low32 |= (IOSAPIC_FIXED << IOSAPIC_DELIVERY_SHIFT);
 374
 375         iosapic_intr_info[irq].low32 = low32;
 376         iosapic_intr_info[irq].dest = dest;
 377         list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list) {
 378                 iosapic = rte->iosapic;
 379                 rte_index = rte->rte_index;
 380                 iosapic_write(iosapic, IOSAPIC_RTE_HIGH(rte_index), high32);
 381                 iosapic_write(iosapic, IOSAPIC_RTE_LOW(rte_index), low32);
 382         }
 383 #endif
 384 }
 385
 386 /*
 387  * Handlers for level-triggered interrupts.
 388  */
 389
 390 static unsigned int
 391 iosapic_startup_level_irq (unsigned int irq)
 392 {
 393         unmask_irq(irq);
 394         return 0;
 395 }
 396
 397 static void
 398 iosapic_end_level_irq (unsigned int irq)
 399 {
 400         ia64_vector vec = irq_to_vector(irq);
 401         struct iosapic_rte_info *rte;
 402
 403         move_native_irq(irq);
 404         list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list)
 405                 iosapic_eoi(rte->iosapic->addr, vec);
 406 }
 407
 408 #define iosapic_shutdown_level_irq      mask_irq
 409 #define iosapic_enable_level_irq        unmask_irq
 410 #define iosapic_disable_level_irq       mask_irq
 411 #define iosapic_ack_level_irq           nop
 412
 413 struct irq_chip irq_type_iosapic_level = {
 414         .name =         "IO-SAPIC-level",
 415         .startup =      iosapic_startup_level_irq,
 416         .shutdown =     iosapic_shutdown_level_irq,
 417         .enable =       iosapic_enable_level_irq,
 418         .disable =      iosapic_disable_level_irq,
 419         .ack =          iosapic_ack_level_irq,
 420         .end =          iosapic_end_level_irq,
 421         .mask =         mask_irq,
 422         .unmask =       unmask_irq,
 423         .set_affinity = iosapic_set_affinity
 424 };
 425
 426 /*
 427  * Handlers for edge-triggered interrupts.
 428  */
 429
 430 static unsigned int
 431 iosapic_startup_edge_irq (unsigned int irq)
 432 {
 433         unmask_irq(irq);
 434         /*
 435          * IOSAPIC simply drops interrupts pended while the
 436          * corresponding pin was masked, so we can't know if an
 437          * interrupt is pending already.  Let's hope not...
 438          */
 439         return 0;
 440 }
 441
 442 static void
 443 iosapic_ack_edge_irq (unsigned int irq)
 444 {
 445         irq_desc_t *idesc = irq_desc + irq;
 446
 447         move_native_irq(irq);
 448         /*
 449          * Once we have recorded IRQ_PENDING already, we can mask the
 450          * interrupt for real. This prevents IRQ storms from unhandled
 451          * devices.
 452          */
 453         if ((idesc->status & (IRQ_PENDING|IRQ_DISABLED)) ==
 454             (IRQ_PENDING|IRQ_DISABLED))
 455                 mask_irq(irq);
 456 }
 457
 458 #define iosapic_enable_edge_irq         unmask_irq
 459 #define iosapic_disable_edge_irq        nop
 460 #define iosapic_end_edge_irq            nop
 461
 462 struct irq_chip irq_type_iosapic_edge = {
 463         .name =         "IO-SAPIC-edge",
 464         .startup =      iosapic_startup_edge_irq,
 465         .shutdown =     iosapic_disable_edge_irq,
 466         .enable =       iosapic_enable_edge_irq,
 467         .disable =      iosapic_disable_edge_irq,
 468         .ack =          iosapic_ack_edge_irq,
 469         .end =          iosapic_end_edge_irq,
 470         .mask =         mask_irq,
 471         .unmask =       unmask_irq,
 472         .set_affinity = iosapic_set_affinity
 473 };
 474
 475 unsigned int
 476 iosapic_version (char __iomem *addr)
 477 {
 478         /*
 479          * IOSAPIC Version Register return 32 bit structure like:
 480          * {
 481          *      unsigned int version   : 8;
 482          *      unsigned int reserved1 : 8;
 483          *      unsigned int max_redir : 8;
 484          *      unsigned int reserved2 : 8;
 485          * }
 486          */
 487         return __iosapic_read(addr, IOSAPIC_VERSION);
 488 }
 489
 490 static int iosapic_find_sharable_irq(unsigned long trigger, unsigned long pol)
 491 {
 492         int i, irq = -ENOSPC, min_count = -1;
 493         struct iosapic_intr_info *info;
 494
 495         /*
 496          * shared vectors for edge-triggered interrupts are not
 497          * supported yet
 498          */
 499         if (trigger == IOSAPIC_EDGE)
 500                 return -EINVAL;
 501
 502         for (i = 0; i <= NR_IRQS; i++) {
 503                 info = &iosapic_intr_info[i];
 504                 if (info->trigger == trigger && info->polarity == pol &&
 505                     (info->dmode == IOSAPIC_FIXED ||
 506                      info->dmode == IOSAPIC_LOWEST_PRIORITY) &&
 507                     can_request_irq(i, IRQF_SHARED)) {
 508                         if (min_count == -1 || info->count < min_count) {
 509                                 irq = i;
 510                                 min_count = info->count;
 511                         }
 512                 }
 513         }
 514         return irq;
 515 }
 516
 517 /*
 518  * if the given vector is already owned by other,
 519  *  assign a new vector for the other and make the vector available
 520  */
 521 static void __init
 522 iosapic_reassign_vector (int irq)
 523 {
 524         int new_irq;
 525
 526         if (!list_empty(&iosapic_intr_info[irq].rtes)) {
 527                 new_irq = create_irq();
 528                 if (new_irq < 0)
 529                         panic("%s: out of interrupt vectors!\n", __FUNCTION__);
 530                 printk(KERN_INFO "Reassigning vector %d to %d\n",
 531                        irq_to_vector(irq), irq_to_vector(new_irq));
 532                 memcpy(&iosapic_intr_info[new_irq], &iosapic_intr_info[irq],
 533                        sizeof(struct iosapic_intr_info));
 534                 INIT_LIST_HEAD(&iosapic_intr_info[new_irq].rtes);
 535                 list_move(iosapic_intr_info[irq].rtes.next,
 536                           &iosapic_intr_info[new_irq].rtes);
 537                 memset(&iosapic_intr_info[irq], 0,
 538                        sizeof(struct iosapic_intr_info));
 539                 iosapic_intr_info[irq].low32 = IOSAPIC_MASK;
 540                 INIT_LIST_HEAD(&iosapic_intr_info[irq].rtes);
 541         }
 542 }
 543
 544 static struct iosapic_rte_info *iosapic_alloc_rte (void)
 545 {
 546         int i;
 547         struct iosapic_rte_info *rte;
 548         int preallocated = 0;
 549
 550         if (!iosapic_kmalloc_ok && list_empty(&free_rte_list)) {
 551                 rte = alloc_bootmem(sizeof(struct iosapic_rte_info) *
 552                                     NR_PREALLOCATE_RTE_ENTRIES);
 553                 if (!rte)
 554                         return NULL;
 555                 for (i = 0; i < NR_PREALLOCATE_RTE_ENTRIES; i++, rte++)
 556                         list_add(&rte->rte_list, &free_rte_list);
 557         }
 558
 559         if (!list_empty(&free_rte_list)) {
 560                 rte = list_entry(free_rte_list.next, struct iosapic_rte_info,
 561                                  rte_list);
 562                 list_del(&rte->rte_list);
 563                 preallocated++;
 564         } else {
 565                 rte = kmalloc(sizeof(struct iosapic_rte_info), GFP_ATOMIC);
 566                 if (!rte)
 567                         return NULL;
 568         }
 569
 570         memset(rte, 0, sizeof(struct iosapic_rte_info));
 571         if (preallocated)
 572                 rte->flags |= RTE_PREALLOCATED;
 573
 574         return rte;
 575 }
 576
 577 static void iosapic_free_rte (struct iosapic_rte_info *rte)
 578 {
 579         if (rte->flags & RTE_PREALLOCATED)
 580                 list_add_tail(&rte->rte_list, &free_rte_list);
 581         else
 582                 kfree(rte);
 583 }
 584
 585 static inline int irq_is_shared (int irq)
 586 {
 587         return (iosapic_intr_info[irq].count > 1);
 588 }
 589
 590 static int
 591 register_intr (unsigned int gsi, int irq, unsigned char delivery,
 592                unsigned long polarity, unsigned long trigger)
 593 {
 594         irq_desc_t *idesc;
 595         struct hw_interrupt_type *irq_type;
 596         int index;
 597         struct iosapic_rte_info *rte;
 598
 599         index = find_iosapic(gsi);
 600         if (index < 0) {
 601                 printk(KERN_WARNING "%s: No IOSAPIC for GSI %u\n",
 602                        __FUNCTION__, gsi);
 603                 return -ENODEV;
 604         }
 605
 606         rte = find_rte(irq, gsi);
 607         if (!rte) {
 608                 rte = iosapic_alloc_rte();
 609                 if (!rte) {
 610                         printk(KERN_WARNING "%s: cannot allocate memory\n",
 611                                __FUNCTION__);
 612                         return -ENOMEM;
 613                 }
 614
 615                 rte->iosapic    = &iosapic_lists[index];
 616                 rte->rte_index  = gsi - rte->iosapic->gsi_base;
 617                 rte->refcnt++;
 618                 list_add_tail(&rte->rte_list, &iosapic_intr_info[irq].rtes);
 619                 iosapic_intr_info[irq].count++;
 620                 iosapic_lists[index].rtes_inuse++;
 621         }
 622         else if (irq_is_shared(irq)) {
 623                 struct iosapic_intr_info *info = &iosapic_intr_info[irq];
 624                 if (info->trigger != trigger || info->polarity != polarity) {
 625                         printk (KERN_WARNING
 626                                 "%s: cannot override the interrupt\n",
 627                                 __FUNCTION__);
 628                         return -EINVAL;
 629                 }
 630         }
 631
 632         iosapic_intr_info[irq].polarity = polarity;
 633         iosapic_intr_info[irq].dmode    = delivery;
 634         iosapic_intr_info[irq].trigger  = trigger;
 635
 636         if (trigger == IOSAPIC_EDGE)
 637                 irq_type = &irq_type_iosapic_edge;
 638         else
 639                 irq_type = &irq_type_iosapic_level;
 640
 641         idesc = irq_desc + irq;
 642         if (idesc->chip != irq_type) {
 643                 if (idesc->chip != &no_irq_type)
 644                         printk(KERN_WARNING
 645                                "%s: changing vector %d from %s to %s\n",
 646                                __FUNCTION__, irq_to_vector(irq),
 647                                idesc->chip->name, irq_type->name);
 648                 idesc->chip = irq_type;
 649         }
 650         return 0;
 651 }
 652
 653 static unsigned int
 654 get_target_cpu (unsigned int gsi, int irq)
 655 {
 656 #ifdef CONFIG_SMP
 657         static int cpu = -1;
 658         extern int cpe_vector;
 659
 660         /*
 661          * In case of vector shared by multiple RTEs, all RTEs that
 662          * share the vector need to use the same destination CPU.
 663          */
 664         if (!list_empty(&iosapic_intr_info[irq].rtes))
 665                 return iosapic_intr_info[irq].dest;
 666
 667         /*
 668          * If the platform supports redirection via XTP, let it
 669          * distribute interrupts.
 670          */
 671         if (smp_int_redirect & SMP_IRQ_REDIRECTION)
 672                 return cpu_physical_id(smp_processor_id());
 673
 674         /*
 675          * Some interrupts (ACPI SCI, for instance) are registered
 676          * before the BSP is marked as online.
 677          */
 678         if (!cpu_online(smp_processor_id()))
 679                 return cpu_physical_id(smp_processor_id());
 680
 681 #ifdef CONFIG_ACPI
 682         if (cpe_vector > 0 && irq_to_vector(irq) == IA64_CPEP_VECTOR)
 683                 return get_cpei_target_cpu();
 684 #endif
 685
 686 #ifdef CONFIG_NUMA
 687         {
 688                 int num_cpus, cpu_index, iosapic_index, numa_cpu, i = 0;
 689                 cpumask_t cpu_mask;
 690
 691                 iosapic_index = find_iosapic(gsi);
 692                 if (iosapic_index < 0 ||
 693                     iosapic_lists[iosapic_index].node == MAX_NUMNODES)
 694                         goto skip_numa_setup;
 695
 696                 cpu_mask = node_to_cpumask(iosapic_lists[iosapic_index].node);
 697
 698                 for_each_cpu_mask(numa_cpu, cpu_mask) {
 699                         if (!cpu_online(numa_cpu))
 700                                 cpu_clear(numa_cpu, cpu_mask);
 701                 }
 702
 703                 num_cpus = cpus_weight(cpu_mask);
 704
 705                 if (!num_cpus)
 706                         goto skip_numa_setup;
 707
 708                 /* Use irq assignment to distribute across cpus in node */
 709                 cpu_index = irq % num_cpus;
 710
 711                 for (numa_cpu = first_cpu(cpu_mask) ; i < cpu_index ; i++)
 712                         numa_cpu = next_cpu(numa_cpu, cpu_mask);
 713
 714                 if (numa_cpu != NR_CPUS)
 715                         return cpu_physical_id(numa_cpu);
 716         }
 717 skip_numa_setup:
 718 #endif
 719         /*
 720          * Otherwise, round-robin interrupt vectors across all the
 721          * processors.  (It'd be nice if we could be smarter in the
 722          * case of NUMA.)
 723          */
 724         do {
 725                 if (++cpu >= NR_CPUS)
 726                         cpu = 0;
 727         } while (!cpu_online(cpu));
 728
 729         return cpu_physical_id(cpu);
 730 #else  /* CONFIG_SMP */
 731         return cpu_physical_id(smp_processor_id());
 732 #endif
 733 }
 734
 735 /*
 736  * ACPI can describe IOSAPIC interrupts via static tables and namespace
 737  * methods.  This provides an interface to register those interrupts and
 738  * program the IOSAPIC RTE.
 739  */
 740 int
 741 iosapic_register_intr (unsigned int gsi,
 742                        unsigned long polarity, unsigned long trigger)
 743 {
 744         int irq, mask = 1, err;
 745         unsigned int dest;
 746         unsigned long flags;
 747         struct iosapic_rte_info *rte;
 748         u32 low32;
 749
 750         /*
 751          * If this GSI has already been registered (i.e., it's a
 752          * shared interrupt, or we lost a race to register it),
 753          * don't touch the RTE.
 754          */
 755         spin_lock_irqsave(&iosapic_lock, flags);
 756         irq = __gsi_to_irq(gsi);
 757         if (irq > 0) {
 758                 rte = find_rte(irq, gsi);
 759                 rte->refcnt++;
 760                 goto unlock_iosapic_lock;
 761         }
 762
 763         /* If vector is running out, we try to find a sharable vector */
 764         irq = create_irq();
 765         if (irq < 0) {
 766                 irq = iosapic_find_sharable_irq(trigger, polarity);
 767                 if (irq < 0)
 768                         goto unlock_iosapic_lock;
 769         }
 770
 771         spin_lock(&irq_desc[irq].lock);
 772         dest = get_target_cpu(gsi, irq);
 773         err = register_intr(gsi, irq, IOSAPIC_LOWEST_PRIORITY,
 774                             polarity, trigger);
 775         if (err < 0) {
 776                 irq = err;
 777                 goto unlock_all;
 778         }
 779
 780         /*
 781          * If the vector is shared and already unmasked for other
 782          * interrupt sources, don't mask it.
 783          */
 784         low32 = iosapic_intr_info[irq].low32;
 785         if (irq_is_shared(irq) && !(low32 & IOSAPIC_MASK))
 786                 mask = 0;
 787         set_rte(gsi, irq, dest, mask);
 788
 789         printk(KERN_INFO "GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d\n",
 790                gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"),
 791                (polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
 792                cpu_logical_id(dest), dest, irq_to_vector(irq));
 793  unlock_all:
 794         spin_unlock(&irq_desc[irq].lock);
 795  unlock_iosapic_lock:
 796         spin_unlock_irqrestore(&iosapic_lock, flags);
 797         return irq;
 798 }
 799
 800 void
 801 iosapic_unregister_intr (unsigned int gsi)
 802 {
 803         unsigned long flags;
 804         int irq, index;
 805         irq_desc_t *idesc;
 806         u32 low32;
 807         unsigned long trigger, polarity;
 808         unsigned int dest;
 809         struct iosapic_rte_info *rte;
 810
 811         /*
 812          * If the irq associated with the gsi is not found,
 813          * iosapic_unregister_intr() is unbalanced. We need to check
 814          * this again after getting locks.
 815          */
 816         irq = gsi_to_irq(gsi);
 817         if (irq < 0) {
 818                 printk(KERN_ERR "iosapic_unregister_intr(%u) unbalanced\n",
 819                        gsi);
 820                 WARN_ON(1);
 821                 return;
 822         }
 823
 824         spin_lock_irqsave(&iosapic_lock, flags);
 825         if ((rte = find_rte(irq, gsi)) == NULL) {
 826                 printk(KERN_ERR "iosapic_unregister_intr(%u) unbalanced\n",
 827                        gsi);
 828                 WARN_ON(1);
 829                 goto out;
 830         }
 831
 832         if (--rte->refcnt > 0)
 833                 goto out;
 834
 835         /* Remove the rte entry from the list */
 836         idesc = irq_desc + irq;
 837         spin_lock(&idesc->lock);
 838         list_del(&rte->rte_list);
 839         spin_unlock(&idesc->lock);
 840
 841         /* Mask the interrupt */
 842         low32 = iosapic_intr_info[irq].low32 | IOSAPIC_MASK;
 843         iosapic_write(rte->iosapic, IOSAPIC_RTE_LOW(rte->rte_index), low32);
 844
 845         iosapic_intr_info[irq].count--;
 846         iosapic_free_rte(rte);
 847         index = find_iosapic(gsi);
 848         iosapic_lists[index].rtes_inuse--;
 849         WARN_ON(iosapic_lists[index].rtes_inuse < 0);
 850
 851         trigger  = iosapic_intr_info[irq].trigger;
 852         polarity = iosapic_intr_info[irq].polarity;
 853         dest     = iosapic_intr_info[irq].dest;
 854         printk(KERN_INFO
 855                "GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d unregistered\n",
 856                gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"),
 857                (polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
 858                cpu_logical_id(dest), dest, irq_to_vector(irq));
 859
 860         if (list_empty(&iosapic_intr_info[irq].rtes)) {
 861                 /* Sanity check */
 862                 BUG_ON(iosapic_intr_info[irq].count);
 863 #ifdef CONFIG_SMP
 864                 /* Clear affinity */
 865                 cpus_setall(idesc->affinity);
 866 #endif
 867                 /* Clear the interrupt information */
 868                 memset(&iosapic_intr_info[irq], 0,
 869                        sizeof(struct iosapic_intr_info));
 870                 iosapic_intr_info[irq].low32 |= IOSAPIC_MASK;
 871                 INIT_LIST_HEAD(&iosapic_intr_info[irq].rtes);
 872
 873                 /* Destroy IRQ */
 874                 destroy_irq(irq);
 875         }
 876  out:
 877         spin_unlock_irqrestore(&iosapic_lock, flags);
 878 }
 879
 880 /*
 881  * ACPI calls this when it finds an entry for a platform interrupt.
 882  */
 883 int __init
 884 iosapic_register_platform_intr (u32 int_type, unsigned int gsi,
 885                                 int iosapic_vector, u16 eid, u16 id,
 886                                 unsigned long polarity, unsigned long trigger)
 887 {
 888         static const char * const name[] = {"unknown", "PMI", "INIT", "CPEI"};
 889         unsigned char delivery;
 890         int irq, vector, mask = 0;
 891         unsigned int dest = ((id << 8) | eid) & 0xffff;
 892
 893         switch (int_type) {
 894               case ACPI_INTERRUPT_PMI:
 895                 vector = iosapic_vector;
 896                 irq = vector;           /* FIXME */
 897                 /*
 898                  * since PMI vector is alloc'd by FW(ACPI) not by kernel,
 899                  * we need to make sure the vector is available
 900                  */
 901                 iosapic_reassign_vector(irq);
 902                 delivery = IOSAPIC_PMI;
 903                 break;
 904               case ACPI_INTERRUPT_INIT:
 905                 irq = create_irq();
 906                 if (irq < 0)
 907                         panic("%s: out of interrupt vectors!\n", __FUNCTION__);
 908                 vector = irq_to_vector(irq);
 909                 delivery = IOSAPIC_INIT;
 910                 break;
 911               case ACPI_INTERRUPT_CPEI:
 912                 vector = IA64_CPE_VECTOR;
 913                 irq = vector;           /* FIXME */
 914                 delivery = IOSAPIC_LOWEST_PRIORITY;
 915                 mask = 1;
 916                 break;
 917               default:
 918                 printk(KERN_ERR "%s: invalid int type 0x%x\n", __FUNCTION__,
 919                        int_type);
 920                 return -1;
 921         }
 922
 923         register_intr(gsi, irq, delivery, polarity, trigger);
 924
 925         printk(KERN_INFO
 926                "PLATFORM int %s (0x%x): GSI %u (%s, %s) -> CPU %d (0x%04x)"
 927                " vector %d\n",
 928                int_type < ARRAY_SIZE(name) ? name[int_type] : "unknown",
 929                int_type, gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"),
 930                (polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
 931                cpu_logical_id(dest), dest, vector);
 932
 933         set_rte(gsi, irq, dest, mask);
 934         return vector;
 935 }
 936
 937 /*
 938  * ACPI calls this when it finds an entry for a legacy ISA IRQ override.
 939  */
 940 void __devinit
 941 iosapic_override_isa_irq (unsigned int isa_irq, unsigned int gsi,
 942                           unsigned long polarity,
 943                           unsigned long trigger)
 944 {
 945         int vector, irq;
 946         unsigned int dest = cpu_physical_id(smp_processor_id());
 947
 948         vector = isa_irq_to_vector(isa_irq);
 949         irq = vector;   /* FIXME */
 950         register_intr(gsi, irq, IOSAPIC_LOWEST_PRIORITY, polarity, trigger);
 951
 952         DBG("ISA: IRQ %u -> GSI %u (%s,%s) -> CPU %d (0x%04x) vector %d\n",
 953             isa_irq, gsi, trigger == IOSAPIC_EDGE ? "edge" : "level",
 954             polarity == IOSAPIC_POL_HIGH ? "high" : "low",
 955             cpu_logical_id(dest), dest, vector);
 956
 957         set_rte(gsi, irq, dest, 1);
 958 }
 959
 960 void __init
 961 iosapic_system_init (int system_pcat_compat)
 962 {
 963         int irq;
 964
 965         for (irq = 0; irq < NR_IRQS; ++irq) {
 966                 iosapic_intr_info[irq].low32 = IOSAPIC_MASK;
 967                 /* mark as unused */
 968                 INIT_LIST_HEAD(&iosapic_intr_info[irq].rtes);
 969         }
 970
 971         pcat_compat = system_pcat_compat;
 972         if (pcat_compat) {
 973                 /*
 974                  * Disable the compatibility mode interrupts (8259 style),
 975                  * needs IN/OUT support enabled.
 976                  */
 977                 printk(KERN_INFO
 978                        "%s: Disabling PC-AT compatible 8259 interrupts\n",
 979                        __FUNCTION__);
 980                 outb(0xff, 0xA1);
 981                 outb(0xff, 0x21);
 982         }
 983 }
 984
 985 static inline int
 986 iosapic_alloc (void)
 987 {
 988         int index;
 989
 990         for (index = 0; index < NR_IOSAPICS; index++)
 991                 if (!iosapic_lists[index].addr)
 992                         return index;
 993
 994         printk(KERN_WARNING "%s: failed to allocate iosapic\n", __FUNCTION__);
 995         return -1;
 996 }
 997
 998 static inline void
 999 iosapic_free (int index)
1000 {
1001         memset(&iosapic_lists[index], 0, sizeof(iosapic_lists[0]));
1002 }
1003
1004 static inline int
1005 iosapic_check_gsi_range (unsigned int gsi_base, unsigned int ver)
1006 {
1007         int index;
1008         unsigned int gsi_end, base, end;
1009
1010         /* check gsi range */
1011         gsi_end = gsi_base + ((ver >> 16) & 0xff);
1012         for (index = 0; index < NR_IOSAPICS; index++) {
1013                 if (!iosapic_lists[index].addr)
1014                         continue;
1015
1016                 base = iosapic_lists[index].gsi_base;
1017                 end  = base + iosapic_lists[index].num_rte - 1;
1018
1019                 if (gsi_end < base || end < gsi_base)
1020                         continue; /* OK */
1021
1022                 return -EBUSY;
1023         }
1024         return 0;
1025 }
1026
1027 int __devinit
1028 iosapic_init (unsigned long phys_addr, unsigned int gsi_base)
1029 {
1030         int num_rte, err, index;
1031         unsigned int isa_irq, ver;
1032         char __iomem *addr;
1033         unsigned long flags;
1034
1035         spin_lock_irqsave(&iosapic_lock, flags);
1036         index = find_iosapic(gsi_base);
1037         if (index >= 0) {
1038                 spin_unlock_irqrestore(&iosapic_lock, flags);
1039                 return -EBUSY;
1040         }
1041
1042         addr = ioremap(phys_addr, 0);
1043         ver = iosapic_version(addr);
1044         if ((err = iosapic_check_gsi_range(gsi_base, ver))) {
1045                 iounmap(addr);
1046                 spin_unlock_irqrestore(&iosapic_lock, flags);
1047                 return err;
1048         }
1049
1050         /*
1051          * The MAX_REDIR register holds the highest input pin number
1052          * (starting from 0).  We add 1 so that we can use it for
1053          * number of pins (= RTEs)
1054          */
1055         num_rte = ((ver >> 16) & 0xff) + 1;
1056
1057         index = iosapic_alloc();
1058         iosapic_lists[index].addr = addr;
1059         iosapic_lists[index].gsi_base = gsi_base;
1060         iosapic_lists[index].num_rte = num_rte;
1061 #ifdef CONFIG_NUMA
1062         iosapic_lists[index].node = MAX_NUMNODES;
1063 #endif
1064         spin_lock_init(&iosapic_lists[index].lock);
1065         spin_unlock_irqrestore(&iosapic_lock, flags);
1066
1067         if ((gsi_base == 0) && pcat_compat) {
1068                 /*
1069                  * Map the legacy ISA devices into the IOSAPIC data.  Some of
1070                  * these may get reprogrammed later on with data from the ACPI
1071                  * Interrupt Source Override table.
1072                  */
1073                 for (isa_irq = 0; isa_irq < 16; ++isa_irq)
1074                         iosapic_override_isa_irq(isa_irq, isa_irq,
1075                                                  IOSAPIC_POL_HIGH,
1076                                                  IOSAPIC_EDGE);
1077         }
1078         return 0;
1079 }
1080
1081 #ifdef CONFIG_HOTPLUG
1082 int
1083 iosapic_remove (unsigned int gsi_base)
1084 {
1085         int index, err = 0;
1086         unsigned long flags;
1087
1088         spin_lock_irqsave(&iosapic_lock, flags);
1089         index = find_iosapic(gsi_base);
1090         if (index < 0) {
1091                 printk(KERN_WARNING "%s: No IOSAPIC for GSI base %u\n",
1092                        __FUNCTION__, gsi_base);
1093                 goto out;
1094         }
1095
1096         if (iosapic_lists[index].rtes_inuse) {
1097                 err = -EBUSY;
1098                 printk(KERN_WARNING "%s: IOSAPIC for GSI base %u is busy\n",
1099                        __FUNCTION__, gsi_base);
1100                 goto out;
1101         }
1102
1103         iounmap(iosapic_lists[index].addr);
1104         iosapic_free(index);
1105  out:
1106         spin_unlock_irqrestore(&iosapic_lock, flags);
1107         return err;
1108 }
1109 #endif /* CONFIG_HOTPLUG */
1110
1111 #ifdef CONFIG_NUMA
1112 void __devinit
1113 map_iosapic_to_node(unsigned int gsi_base, int node)
1114 {
1115         int index;
1116
1117         index = find_iosapic(gsi_base);
1118         if (index < 0) {
1119                 printk(KERN_WARNING "%s: No IOSAPIC for GSI %u\n",
1120                        __FUNCTION__, gsi_base);
1121                 return;
1122         }
1123         iosapic_lists[index].node = node;
1124         return;
1125 }
1126 #endif
1127
1128 static int __init iosapic_enable_kmalloc (void)
1129 {
1130         iosapic_kmalloc_ok = 1;
1131         return 0;
1132 }
1133 core_initcall (iosapic_enable_kmalloc);