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   1 /*
   2  *  linux/arch/i386/nmi.c
   3  *
   4  *  NMI watchdog support on APIC systems
   5  *
   6  *  Started by Ingo Molnar <mingo@redhat.com>
   7  *
   8  *  Fixes:
   9  *  Mikael Pettersson   : AMD K7 support for local APIC NMI watchdog.
  10  *  Mikael Pettersson   : Power Management for local APIC NMI watchdog.
  11  *  Mikael Pettersson   : Pentium 4 support for local APIC NMI watchdog.
  12  *  Pavel Machek and
  13  *  Mikael Pettersson   : PM converted to driver model. Disable/enable API.
  14  */
  15
  16 #include <linux/config.h>
  17 #include <linux/delay.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/module.h>
  20 #include <linux/nmi.h>
  21 #include <linux/sysdev.h>
  22 #include <linux/sysctl.h>
  23 #include <linux/percpu.h>
  24
  25 #include <asm/smp.h>
  26 #include <asm/nmi.h>
  27 #include <asm/kdebug.h>
  28
  29 #include "mach_traps.h"
  30
  31 /* perfctr_nmi_owner tracks the ownership of the perfctr registers:
  32  * evtsel_nmi_owner tracks the ownership of the event selection
  33  * - different performance counters/ event selection may be reserved for
  34  *   different subsystems this reservation system just tries to coordinate
  35  *   things a little
  36  */
  37 static DEFINE_PER_CPU(unsigned long, perfctr_nmi_owner);
  38 static DEFINE_PER_CPU(unsigned long, evntsel_nmi_owner[3]);
  39
  40 /* this number is calculated from Intel's MSR_P4_CRU_ESCR5 register and it's
  41  * offset from MSR_P4_BSU_ESCR0.  It will be the max for all platforms (for now)
  42  */
  43 #define NMI_MAX_COUNTER_BITS 66
  44
  45 /* nmi_active:
  46  * >0: the lapic NMI watchdog is active, but can be disabled
  47  * <0: the lapic NMI watchdog has not been set up, and cannot
  48  *     be enabled
  49  *  0: the lapic NMI watchdog is disabled, but can be enabled
  50  */
  51 atomic_t nmi_active = ATOMIC_INIT(0);           /* oprofile uses this */
  52
  53 unsigned int nmi_watchdog = NMI_DEFAULT;
  54 static unsigned int nmi_hz = HZ;
  55
  56 struct nmi_watchdog_ctlblk {
  57         int enabled;
  58         u64 check_bit;
  59         unsigned int cccr_msr;
  60         unsigned int perfctr_msr;  /* the MSR to reset in NMI handler */
  61         unsigned int evntsel_msr;  /* the MSR to select the events to handle */
  62 };
  63 static DEFINE_PER_CPU(struct nmi_watchdog_ctlblk, nmi_watchdog_ctlblk);
  64
  65 /* local prototypes */
  66 static void stop_apic_nmi_watchdog(void *unused);
  67 static int unknown_nmi_panic_callback(struct pt_regs *regs, int cpu);
  68
  69 extern void show_registers(struct pt_regs *regs);
  70 extern int unknown_nmi_panic;
  71
  72 /* converts an msr to an appropriate reservation bit */
  73 static inline unsigned int nmi_perfctr_msr_to_bit(unsigned int msr)
  74 {
  75         /* returns the bit offset of the performance counter register */
  76         switch (boot_cpu_data.x86_vendor) {
  77         case X86_VENDOR_AMD:
  78                 return (msr - MSR_K7_PERFCTR0);
  79         case X86_VENDOR_INTEL:
  80                 switch (boot_cpu_data.x86) {
  81                 case 6:
  82                         return (msr - MSR_P6_PERFCTR0);
  83                 case 15:
  84                         return (msr - MSR_P4_BPU_PERFCTR0);
  85                 }
  86         }
  87         return 0;
  88 }
  89
  90 /* converts an msr to an appropriate reservation bit */
  91 static inline unsigned int nmi_evntsel_msr_to_bit(unsigned int msr)
  92 {
  93         /* returns the bit offset of the event selection register */
  94         switch (boot_cpu_data.x86_vendor) {
  95         case X86_VENDOR_AMD:
  96                 return (msr - MSR_K7_EVNTSEL0);
  97         case X86_VENDOR_INTEL:
  98                 switch (boot_cpu_data.x86) {
  99                 case 6:
 100                         return (msr - MSR_P6_EVNTSEL0);
 101                 case 15:
 102                         return (msr - MSR_P4_BSU_ESCR0);
 103                 }
 104         }
 105         return 0;
 106 }
 107
 108 /* checks for a bit availability (hack for oprofile) */
 109 int avail_to_resrv_perfctr_nmi_bit(unsigned int counter)
 110 {
 111         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 112
 113         return (!test_bit(counter, &__get_cpu_var(perfctr_nmi_owner)));
 114 }
 115
 116 /* checks the an msr for availability */
 117 int avail_to_resrv_perfctr_nmi(unsigned int msr)
 118 {
 119         unsigned int counter;
 120
 121         counter = nmi_perfctr_msr_to_bit(msr);
 122         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 123
 124         return (!test_bit(counter, &__get_cpu_var(perfctr_nmi_owner)));
 125 }
 126
 127 int reserve_perfctr_nmi(unsigned int msr)
 128 {
 129         unsigned int counter;
 130
 131         counter = nmi_perfctr_msr_to_bit(msr);
 132         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 133
 134         if (!test_and_set_bit(counter, &__get_cpu_var(perfctr_nmi_owner)))
 135                 return 1;
 136         return 0;
 137 }
 138
 139 void release_perfctr_nmi(unsigned int msr)
 140 {
 141         unsigned int counter;
 142
 143         counter = nmi_perfctr_msr_to_bit(msr);
 144         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 145
 146         clear_bit(counter, &__get_cpu_var(perfctr_nmi_owner));
 147 }
 148
 149 int reserve_evntsel_nmi(unsigned int msr)
 150 {
 151         unsigned int counter;
 152
 153         counter = nmi_evntsel_msr_to_bit(msr);
 154         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 155
 156         if (!test_and_set_bit(counter, &__get_cpu_var(evntsel_nmi_owner)[0]))
 157                 return 1;
 158         return 0;
 159 }
 160
 161 void release_evntsel_nmi(unsigned int msr)
 162 {
 163         unsigned int counter;
 164
 165         counter = nmi_evntsel_msr_to_bit(msr);
 166         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 167
 168         clear_bit(counter, &__get_cpu_var(evntsel_nmi_owner)[0]);
 169 }
 170
 171 static __cpuinit inline int nmi_known_cpu(void)
 172 {
 173         switch (boot_cpu_data.x86_vendor) {
 174         case X86_VENDOR_AMD:
 175                 return ((boot_cpu_data.x86 == 15) || (boot_cpu_data.x86 == 6));
 176         case X86_VENDOR_INTEL:
 177                 return ((boot_cpu_data.x86 == 15) || (boot_cpu_data.x86 == 6));
 178         }
 179         return 0;
 180 }
 181
 182 #ifdef CONFIG_SMP
 183 /* The performance counters used by NMI_LOCAL_APIC don't trigger when
 184  * the CPU is idle. To make sure the NMI watchdog really ticks on all
 185  * CPUs during the test make them busy.
 186  */
 187 static __init void nmi_cpu_busy(void *data)
 188 {
 189         volatile int *endflag = data;
 190         local_irq_enable_in_hardirq();
 191         /* Intentionally don't use cpu_relax here. This is
 192            to make sure that the performance counter really ticks,
 193            even if there is a simulator or similar that catches the
 194            pause instruction. On a real HT machine this is fine because
 195            all other CPUs are busy with "useless" delay loops and don't
 196            care if they get somewhat less cycles. */
 197         while (*endflag == 0)
 198                 barrier();
 199 }
 200 #endif
 201
 202 static int __init check_nmi_watchdog(void)
 203 {
 204         volatile int endflag = 0;
 205         unsigned int *prev_nmi_count;
 206         int cpu;
 207
 208         if ((nmi_watchdog == NMI_NONE) || (nmi_watchdog == NMI_DEFAULT))
 209                 return 0;
 210
 211         if (!atomic_read(&nmi_active))
 212                 return 0;
 213
 214         prev_nmi_count = kmalloc(NR_CPUS * sizeof(int), GFP_KERNEL);
 215         if (!prev_nmi_count)
 216                 return -1;
 217
 218         printk(KERN_INFO "Testing NMI watchdog ... ");
 219
 220         if (nmi_watchdog == NMI_LOCAL_APIC)
 221                 smp_call_function(nmi_cpu_busy, (void *)&endflag, 0, 0);
 222
 223         for_each_possible_cpu(cpu)
 224                 prev_nmi_count[cpu] = per_cpu(irq_stat, cpu).__nmi_count;
 225         local_irq_enable();
 226         mdelay((10*1000)/nmi_hz); // wait 10 ticks
 227
 228         for_each_possible_cpu(cpu) {
 229 #ifdef CONFIG_SMP
 230                 /* Check cpu_callin_map here because that is set
 231                    after the timer is started. */
 232                 if (!cpu_isset(cpu, cpu_callin_map))
 233                         continue;
 234 #endif
 235                 if (!per_cpu(nmi_watchdog_ctlblk, cpu).enabled)
 236                         continue;
 237                 if (nmi_count(cpu) - prev_nmi_count[cpu] <= 5) {
 238                         printk("CPU#%d: NMI appears to be stuck (%d->%d)!\n",
 239                                 cpu,
 240                                 prev_nmi_count[cpu],
 241                                 nmi_count(cpu));
 242                         per_cpu(nmi_watchdog_ctlblk, cpu).enabled = 0;
 243                         atomic_dec(&nmi_active);
 244                 }
 245         }
 246         if (!atomic_read(&nmi_active)) {
 247                 kfree(prev_nmi_count);
 248                 atomic_set(&nmi_active, -1);
 249                 return -1;
 250         }
 251         endflag = 1;
 252         printk("OK.\n");
 253
 254         /* now that we know it works we can reduce NMI frequency to
 255            something more reasonable; makes a difference in some configs */
 256         if (nmi_watchdog == NMI_LOCAL_APIC)
 257                 nmi_hz = 1;
 258
 259         kfree(prev_nmi_count);
 260         return 0;
 261 }
 262 /* This needs to happen later in boot so counters are working */
 263 late_initcall(check_nmi_watchdog);
 264
 265 static int __init setup_nmi_watchdog(char *str)
 266 {
 267         int nmi;
 268
 269         get_option(&str, &nmi);
 270
 271         if ((nmi >= NMI_INVALID) || (nmi < NMI_NONE))
 272                 return 0;
 273         /*
 274          * If any other x86 CPU has a local APIC, then
 275          * please test the NMI stuff there and send me the
 276          * missing bits. Right now Intel P6/P4 and AMD K7 only.
 277          */
 278         if ((nmi == NMI_LOCAL_APIC) && (nmi_known_cpu() == 0))
 279                 return 0;  /* no lapic support */
 280         nmi_watchdog = nmi;
 281         return 1;
 282 }
 283
 284 __setup("nmi_watchdog=", setup_nmi_watchdog);
 285
 286 static void disable_lapic_nmi_watchdog(void)
 287 {
 288         BUG_ON(nmi_watchdog != NMI_LOCAL_APIC);
 289
 290         if (atomic_read(&nmi_active) <= 0)
 291                 return;
 292
 293         on_each_cpu(stop_apic_nmi_watchdog, NULL, 0, 1);
 294
 295         BUG_ON(atomic_read(&nmi_active) != 0);
 296 }
 297
 298 static void enable_lapic_nmi_watchdog(void)
 299 {
 300         BUG_ON(nmi_watchdog != NMI_LOCAL_APIC);
 301
 302         /* are we already enabled */
 303         if (atomic_read(&nmi_active) != 0)
 304                 return;
 305
 306         /* are we lapic aware */
 307         if (nmi_known_cpu() <= 0)
 308                 return;
 309
 310         on_each_cpu(setup_apic_nmi_watchdog, NULL, 0, 1);
 311         touch_nmi_watchdog();
 312 }
 313
 314 void disable_timer_nmi_watchdog(void)
 315 {
 316         BUG_ON(nmi_watchdog != NMI_IO_APIC);
 317
 318         if (atomic_read(&nmi_active) <= 0)
 319                 return;
 320
 321         disable_irq(0);
 322         on_each_cpu(stop_apic_nmi_watchdog, NULL, 0, 1);
 323
 324         BUG_ON(atomic_read(&nmi_active) != 0);
 325 }
 326
 327 void enable_timer_nmi_watchdog(void)
 328 {
 329         BUG_ON(nmi_watchdog != NMI_IO_APIC);
 330
 331         if (atomic_read(&nmi_active) == 0) {
 332                 touch_nmi_watchdog();
 333                 on_each_cpu(setup_apic_nmi_watchdog, NULL, 0, 1);
 334                 enable_irq(0);
 335         }
 336 }
 337
 338 #ifdef CONFIG_PM
 339
 340 static int nmi_pm_active; /* nmi_active before suspend */
 341
 342 static int lapic_nmi_suspend(struct sys_device *dev, pm_message_t state)
 343 {
 344         nmi_pm_active = atomic_read(&nmi_active);
 345         disable_lapic_nmi_watchdog();
 346         return 0;
 347 }
 348
 349 static int lapic_nmi_resume(struct sys_device *dev)
 350 {
 351         if (nmi_pm_active > 0)
 352                 enable_lapic_nmi_watchdog();
 353         return 0;
 354 }
 355
 356
 357 static struct sysdev_class nmi_sysclass = {
 358         set_kset_name("lapic_nmi"),
 359         .resume         = lapic_nmi_resume,
 360         .suspend        = lapic_nmi_suspend,
 361 };
 362
 363 static struct sys_device device_lapic_nmi = {
 364         .id     = 0,
 365         .cls    = &nmi_sysclass,
 366 };
 367
 368 static int __init init_lapic_nmi_sysfs(void)
 369 {
 370         int error;
 371
 372         /* should really be a BUG_ON but b/c this is an
 373          * init call, it just doesn't work.  -dcz
 374          */
 375         if (nmi_watchdog != NMI_LOCAL_APIC)
 376                 return 0;
 377
 378         if ( atomic_read(&nmi_active) < 0 )
 379                 return 0;
 380
 381         error = sysdev_class_register(&nmi_sysclass);
 382         if (!error)
 383                 error = sysdev_register(&device_lapic_nmi);
 384         return error;
 385 }
 386 /* must come after the local APIC's device_initcall() */
 387 late_initcall(init_lapic_nmi_sysfs);
 388
 389 #endif  /* CONFIG_PM */
 390
 391 /*
 392  * Activate the NMI watchdog via the local APIC.
 393  * Original code written by Keith Owens.
 394  */
 395
 396 static void write_watchdog_counter(unsigned int perfctr_msr, const char *descr)
 397 {
 398         u64 count = (u64)cpu_khz * 1000;
 399
 400         do_div(count, nmi_hz);
 401         if(descr)
 402                 Dprintk("setting %s to -0x%08Lx\n", descr, count);
 403         wrmsrl(perfctr_msr, 0 - count);
 404 }
 405
 406 /* Note that these events don't tick when the CPU idles. This means
 407    the frequency varies with CPU load. */
 408
 409 #define K7_EVNTSEL_ENABLE       (1 << 22)
 410 #define K7_EVNTSEL_INT          (1 << 20)
 411 #define K7_EVNTSEL_OS           (1 << 17)
 412 #define K7_EVNTSEL_USR          (1 << 16)
 413 #define K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING    0x76
 414 #define K7_NMI_EVENT            K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING
 415
 416 static int setup_k7_watchdog(void)
 417 {
 418         unsigned int perfctr_msr, evntsel_msr;
 419         unsigned int evntsel;
 420         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 421
 422         perfctr_msr = MSR_K7_PERFCTR0;
 423         evntsel_msr = MSR_K7_EVNTSEL0;
 424         if (!reserve_perfctr_nmi(perfctr_msr))
 425                 goto fail;
 426
 427         if (!reserve_evntsel_nmi(evntsel_msr))
 428                 goto fail1;
 429
 430         wrmsrl(perfctr_msr, 0UL);
 431
 432         evntsel = K7_EVNTSEL_INT
 433                 | K7_EVNTSEL_OS
 434                 | K7_EVNTSEL_USR
 435                 | K7_NMI_EVENT;
 436
 437         /* setup the timer */
 438         wrmsr(evntsel_msr, evntsel, 0);
 439         write_watchdog_counter(perfctr_msr, "K7_PERFCTR0");
 440         apic_write(APIC_LVTPC, APIC_DM_NMI);
 441         evntsel |= K7_EVNTSEL_ENABLE;
 442         wrmsr(evntsel_msr, evntsel, 0);
 443
 444         wd->perfctr_msr = perfctr_msr;
 445         wd->evntsel_msr = evntsel_msr;
 446         wd->cccr_msr = 0;  //unused
 447         wd->check_bit = 1ULL<<63;
 448         return 1;
 449 fail1:
 450         release_perfctr_nmi(perfctr_msr);
 451 fail:
 452         return 0;
 453 }
 454
 455 static void stop_k7_watchdog(void)
 456 {
 457         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 458
 459         wrmsr(wd->evntsel_msr, 0, 0);
 460
 461         release_evntsel_nmi(wd->evntsel_msr);
 462         release_perfctr_nmi(wd->perfctr_msr);
 463 }
 464
 465 #define P6_EVNTSEL0_ENABLE      (1 << 22)
 466 #define P6_EVNTSEL_INT          (1 << 20)
 467 #define P6_EVNTSEL_OS           (1 << 17)
 468 #define P6_EVNTSEL_USR          (1 << 16)
 469 #define P6_EVENT_CPU_CLOCKS_NOT_HALTED  0x79
 470 #define P6_NMI_EVENT            P6_EVENT_CPU_CLOCKS_NOT_HALTED
 471
 472 static int setup_p6_watchdog(void)
 473 {
 474         unsigned int perfctr_msr, evntsel_msr;
 475         unsigned int evntsel;
 476         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 477
 478         perfctr_msr = MSR_P6_PERFCTR0;
 479         evntsel_msr = MSR_P6_EVNTSEL0;
 480         if (!reserve_perfctr_nmi(perfctr_msr))
 481                 goto fail;
 482
 483         if (!reserve_evntsel_nmi(evntsel_msr))
 484                 goto fail1;
 485
 486         wrmsrl(perfctr_msr, 0UL);
 487
 488         evntsel = P6_EVNTSEL_INT
 489                 | P6_EVNTSEL_OS
 490                 | P6_EVNTSEL_USR
 491                 | P6_NMI_EVENT;
 492
 493         /* setup the timer */
 494         wrmsr(evntsel_msr, evntsel, 0);
 495         write_watchdog_counter(perfctr_msr, "P6_PERFCTR0");
 496         apic_write(APIC_LVTPC, APIC_DM_NMI);
 497         evntsel |= P6_EVNTSEL0_ENABLE;
 498         wrmsr(evntsel_msr, evntsel, 0);
 499
 500         wd->perfctr_msr = perfctr_msr;
 501         wd->evntsel_msr = evntsel_msr;
 502         wd->cccr_msr = 0;  //unused
 503         wd->check_bit = 1ULL<<39;
 504         return 1;
 505 fail1:
 506         release_perfctr_nmi(perfctr_msr);
 507 fail:
 508         return 0;
 509 }
 510
 511 static void stop_p6_watchdog(void)
 512 {
 513         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 514
 515         wrmsr(wd->evntsel_msr, 0, 0);
 516
 517         release_evntsel_nmi(wd->evntsel_msr);
 518         release_perfctr_nmi(wd->perfctr_msr);
 519 }
 520
 521 /* Note that these events don't tick when the CPU idles. This means
 522    the frequency varies with CPU load. */
 523
 524 #define MSR_P4_MISC_ENABLE_PERF_AVAIL   (1<<7)
 525 #define P4_ESCR_EVENT_SELECT(N) ((N)<<25)
 526 #define P4_ESCR_OS              (1<<3)
 527 #define P4_ESCR_USR             (1<<2)
 528 #define P4_CCCR_OVF_PMI0        (1<<26)
 529 #define P4_CCCR_OVF_PMI1        (1<<27)
 530 #define P4_CCCR_THRESHOLD(N)    ((N)<<20)
 531 #define P4_CCCR_COMPLEMENT      (1<<19)
 532 #define P4_CCCR_COMPARE         (1<<18)
 533 #define P4_CCCR_REQUIRED        (3<<16)
 534 #define P4_CCCR_ESCR_SELECT(N)  ((N)<<13)
 535 #define P4_CCCR_ENABLE          (1<<12)
 536 #define P4_CCCR_OVF             (1<<31)
 537 /* Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter
 538    CRU_ESCR0 (with any non-null event selector) through a complemented
 539    max threshold. [IA32-Vol3, Section 14.9.9] */
 540
 541 static int setup_p4_watchdog(void)
 542 {
 543         unsigned int perfctr_msr, evntsel_msr, cccr_msr;
 544         unsigned int evntsel, cccr_val;
 545         unsigned int misc_enable, dummy;
 546         unsigned int ht_num;
 547         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 548
 549         rdmsr(MSR_IA32_MISC_ENABLE, misc_enable, dummy);
 550         if (!(misc_enable & MSR_P4_MISC_ENABLE_PERF_AVAIL))
 551                 return 0;
 552
 553 #ifdef CONFIG_SMP
 554         /* detect which hyperthread we are on */
 555         if (smp_num_siblings == 2) {
 556                 unsigned int ebx, apicid;
 557
 558                 ebx = cpuid_ebx(1);
 559                 apicid = (ebx >> 24) & 0xff;
 560                 ht_num = apicid & 1;
 561         } else
 562 #endif
 563                 ht_num = 0;
 564
 565         /* performance counters are shared resources
 566          * assign each hyperthread its own set
 567          * (re-use the ESCR0 register, seems safe
 568          * and keeps the cccr_val the same)
 569          */
 570         if (!ht_num) {
 571                 /* logical cpu 0 */
 572                 perfctr_msr = MSR_P4_IQ_PERFCTR0;
 573                 evntsel_msr = MSR_P4_CRU_ESCR0;
 574                 cccr_msr = MSR_P4_IQ_CCCR0;
 575                 cccr_val = P4_CCCR_OVF_PMI0 | P4_CCCR_ESCR_SELECT(4);
 576         } else {
 577                 /* logical cpu 1 */
 578                 perfctr_msr = MSR_P4_IQ_PERFCTR1;
 579                 evntsel_msr = MSR_P4_CRU_ESCR0;
 580                 cccr_msr = MSR_P4_IQ_CCCR1;
 581                 cccr_val = P4_CCCR_OVF_PMI1 | P4_CCCR_ESCR_SELECT(4);
 582         }
 583
 584         if (!reserve_perfctr_nmi(perfctr_msr))
 585                 goto fail;
 586
 587         if (!reserve_evntsel_nmi(evntsel_msr))
 588                 goto fail1;
 589
 590         evntsel = P4_ESCR_EVENT_SELECT(0x3F)
 591                 | P4_ESCR_OS
 592                 | P4_ESCR_USR;
 593
 594         cccr_val |= P4_CCCR_THRESHOLD(15)
 595                  | P4_CCCR_COMPLEMENT
 596                  | P4_CCCR_COMPARE
 597                  | P4_CCCR_REQUIRED;
 598
 599         wrmsr(evntsel_msr, evntsel, 0);
 600         wrmsr(cccr_msr, cccr_val, 0);
 601         write_watchdog_counter(perfctr_msr, "P4_IQ_COUNTER0");
 602         apic_write(APIC_LVTPC, APIC_DM_NMI);
 603         cccr_val |= P4_CCCR_ENABLE;
 604         wrmsr(cccr_msr, cccr_val, 0);
 605         wd->perfctr_msr = perfctr_msr;
 606         wd->evntsel_msr = evntsel_msr;
 607         wd->cccr_msr = cccr_msr;
 608         wd->check_bit = 1ULL<<39;
 609         return 1;
 610 fail1:
 611         release_perfctr_nmi(perfctr_msr);
 612 fail:
 613         return 0;
 614 }
 615
 616 static void stop_p4_watchdog(void)
 617 {
 618         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 619
 620         wrmsr(wd->cccr_msr, 0, 0);
 621         wrmsr(wd->evntsel_msr, 0, 0);
 622
 623         release_evntsel_nmi(wd->evntsel_msr);
 624         release_perfctr_nmi(wd->perfctr_msr);
 625 }
 626
 627 void setup_apic_nmi_watchdog (void *unused)
 628 {
 629         /* only support LOCAL and IO APICs for now */
 630         if ((nmi_watchdog != NMI_LOCAL_APIC) &&
 631             (nmi_watchdog != NMI_IO_APIC))
 632                 return;
 633
 634         if (nmi_watchdog == NMI_LOCAL_APIC) {
 635                 switch (boot_cpu_data.x86_vendor) {
 636                 case X86_VENDOR_AMD:
 637                         if (boot_cpu_data.x86 != 6 && boot_cpu_data.x86 != 15)
 638                                 return;
 639                         if (!setup_k7_watchdog())
 640                                 return;
 641                         break;
 642                 case X86_VENDOR_INTEL:
 643                         switch (boot_cpu_data.x86) {
 644                         case 6:
 645                                 if (boot_cpu_data.x86_model > 0xd)
 646                                         return;
 647
 648                                 if (!setup_p6_watchdog())
 649                                         return;
 650                                 break;
 651                         case 15:
 652                                 if (boot_cpu_data.x86_model > 0x4)
 653                                         return;
 654
 655                                 if (!setup_p4_watchdog())
 656                                         return;
 657                                 break;
 658                         default:
 659                                 return;
 660                         }
 661                         break;
 662                 default:
 663                         return;
 664                 }
 665         }
 666         __get_cpu_var(nmi_watchdog_ctlblk.enabled) = 1;
 667         atomic_inc(&nmi_active);
 668 }
 669
 670 static void stop_apic_nmi_watchdog(void *unused)
 671 {
 672         /* only support LOCAL and IO APICs for now */
 673         if ((nmi_watchdog != NMI_LOCAL_APIC) &&
 674             (nmi_watchdog != NMI_IO_APIC))
 675                 return;
 676
 677         if (nmi_watchdog == NMI_LOCAL_APIC) {
 678                 switch (boot_cpu_data.x86_vendor) {
 679                 case X86_VENDOR_AMD:
 680                         stop_k7_watchdog();
 681                         break;
 682                 case X86_VENDOR_INTEL:
 683                         switch (boot_cpu_data.x86) {
 684                         case 6:
 685                                 if (boot_cpu_data.x86_model > 0xd)
 686                                         break;
 687                                 stop_p6_watchdog();
 688                                 break;
 689                         case 15:
 690                                 if (boot_cpu_data.x86_model > 0x4)
 691                                         break;
 692                                 stop_p4_watchdog();
 693                                 break;
 694                         }
 695                         break;
 696                 default:
 697                         return;
 698                 }
 699         }
 700         __get_cpu_var(nmi_watchdog_ctlblk.enabled) = 0;
 701         atomic_dec(&nmi_active);
 702 }
 703
 704 /*
 705  * the best way to detect whether a CPU has a 'hard lockup' problem
 706  * is to check it's local APIC timer IRQ counts. If they are not
 707  * changing then that CPU has some problem.
 708  *
 709  * as these watchdog NMI IRQs are generated on every CPU, we only
 710  * have to check the current processor.
 711  *
 712  * since NMIs don't listen to _any_ locks, we have to be extremely
 713  * careful not to rely on unsafe variables. The printk might lock
 714  * up though, so we have to break up any console locks first ...
 715  * [when there will be more tty-related locks, break them up
 716  *  here too!]
 717  */
 718
 719 static unsigned int
 720         last_irq_sums [NR_CPUS],
 721         alert_counter [NR_CPUS];
 722
 723 void touch_nmi_watchdog (void)
 724 {
 725         int i;
 726
 727         /*
 728          * Just reset the alert counters, (other CPUs might be
 729          * spinning on locks we hold):
 730          */
 731         for_each_possible_cpu(i)
 732                 alert_counter[i] = 0;
 733
 734         /*
 735          * Tickle the softlockup detector too:
 736          */
 737         touch_softlockup_watchdog();
 738 }
 739 EXPORT_SYMBOL(touch_nmi_watchdog);
 740
 741 extern void die_nmi(struct pt_regs *, const char *msg);
 742
 743 int nmi_watchdog_tick (struct pt_regs * regs, unsigned reason)
 744 {
 745
 746         /*
 747          * Since current_thread_info()-> is always on the stack, and we
 748          * always switch the stack NMI-atomically, it's safe to use
 749          * smp_processor_id().
 750          */
 751         unsigned int sum;
 752         int touched = 0;
 753         int cpu = smp_processor_id();
 754         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 755         u64 dummy;
 756         int rc=0;
 757
 758         /* check for other users first */
 759         if (notify_die(DIE_NMI, "nmi", regs, reason, 2, SIGINT)
 760                         == NOTIFY_STOP) {
 761                 rc = 1;
 762                 touched = 1;
 763         }
 764
 765         sum = per_cpu(irq_stat, cpu).apic_timer_irqs;
 766
 767         /* if the apic timer isn't firing, this cpu isn't doing much */
 768         if (!touched && last_irq_sums[cpu] == sum) {
 769                 /*
 770                  * Ayiee, looks like this CPU is stuck ...
 771                  * wait a few IRQs (5 seconds) before doing the oops ...
 772                  */
 773                 alert_counter[cpu]++;
 774                 if (alert_counter[cpu] == 5*nmi_hz)
 775                         /*
 776                          * die_nmi will return ONLY if NOTIFY_STOP happens..
 777                          */
 778                         die_nmi(regs, "BUG: NMI Watchdog detected LOCKUP");
 779         } else {
 780                 last_irq_sums[cpu] = sum;
 781                 alert_counter[cpu] = 0;
 782         }
 783         /* see if the nmi watchdog went off */
 784         if (wd->enabled) {
 785                 if (nmi_watchdog == NMI_LOCAL_APIC) {
 786                         rdmsrl(wd->perfctr_msr, dummy);
 787                         if (dummy & wd->check_bit){
 788                                 /* this wasn't a watchdog timer interrupt */
 789                                 goto done;
 790                         }
 791
 792                         /* only Intel P4 uses the cccr msr */
 793                         if (wd->cccr_msr != 0) {
 794                                 /*
 795                                  * P4 quirks:
 796                                  * - An overflown perfctr will assert its interrupt
 797                                  *   until the OVF flag in its CCCR is cleared.
 798                                  * - LVTPC is masked on interrupt and must be
 799                                  *   unmasked by the LVTPC handler.
 800                                  */
 801                                 rdmsrl(wd->cccr_msr, dummy);
 802                                 dummy &= ~P4_CCCR_OVF;
 803                                 wrmsrl(wd->cccr_msr, dummy);
 804                                 apic_write(APIC_LVTPC, APIC_DM_NMI);
 805                         }
 806                         else if (wd->perfctr_msr == MSR_P6_PERFCTR0) {
 807                                 /* Only P6 based Pentium M need to re-unmask
 808                                  * the apic vector but it doesn't hurt
 809                                  * other P6 variant */
 810                                 apic_write(APIC_LVTPC, APIC_DM_NMI);
 811                         }
 812                         /* start the cycle over again */
 813                         write_watchdog_counter(wd->perfctr_msr, NULL);
 814                         rc = 1;
 815                 } else if (nmi_watchdog == NMI_IO_APIC) {
 816                         /* don't know how to accurately check for this.
 817                          * just assume it was a watchdog timer interrupt
 818                          * This matches the old behaviour.
 819                          */
 820                         rc = 1;
 821                 } else
 822                         printk(KERN_WARNING "Unknown enabled NMI hardware?!\n");
 823         }
 824 done:
 825         return rc;
 826 }
 827
 828 int do_nmi_callback(struct pt_regs * regs, int cpu)
 829 {
 830 #ifdef CONFIG_SYSCTL
 831         if (unknown_nmi_panic)
 832                 return unknown_nmi_panic_callback(regs, cpu);
 833 #endif
 834         return 0;
 835 }
 836
 837 #ifdef CONFIG_SYSCTL
 838
 839 static int unknown_nmi_panic_callback(struct pt_regs *regs, int cpu)
 840 {
 841         unsigned char reason = get_nmi_reason();
 842         char buf[64];
 843
 844         sprintf(buf, "NMI received for unknown reason %02x\n", reason);
 845         die_nmi(regs, buf);
 846         return 0;
 847 }
 848
 849 /*
 850  * proc handler for /proc/sys/kernel/nmi
 851  */
 852 int proc_nmi_enabled(struct ctl_table *table, int write, struct file *file,
 853                         void __user *buffer, size_t *length, loff_t *ppos)
 854 {
 855         int old_state;
 856
 857         nmi_watchdog_enabled = (atomic_read(&nmi_active) > 0) ? 1 : 0;
 858         old_state = nmi_watchdog_enabled;
 859         proc_dointvec(table, write, file, buffer, length, ppos);
 860         if (!!old_state == !!nmi_watchdog_enabled)
 861                 return 0;
 862
 863         if (atomic_read(&nmi_active) < 0) {
 864                 printk( KERN_WARNING "NMI watchdog is permanently disabled\n");
 865                 return -EIO;
 866         }
 867
 868         if (nmi_watchdog == NMI_DEFAULT) {
 869                 if (nmi_known_cpu() > 0)
 870                         nmi_watchdog = NMI_LOCAL_APIC;
 871                 else
 872                         nmi_watchdog = NMI_IO_APIC;
 873         }
 874
 875         if (nmi_watchdog == NMI_LOCAL_APIC) {
 876                 if (nmi_watchdog_enabled)
 877                         enable_lapic_nmi_watchdog();
 878                 else
 879                         disable_lapic_nmi_watchdog();
 880         } else {
 881                 printk( KERN_WARNING
 882                         "NMI watchdog doesn't know what hardware to touch\n");
 883                 return -EIO;
 884         }
 885         return 0;
 886 }
 887
 888 #endif
 889
 890 EXPORT_SYMBOL(nmi_active);
 891 EXPORT_SYMBOL(nmi_watchdog);
 892 EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi);
 893 EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi_bit);
 894 EXPORT_SYMBOL(reserve_perfctr_nmi);
 895 EXPORT_SYMBOL(release_perfctr_nmi);
 896 EXPORT_SYMBOL(reserve_evntsel_nmi);
 897 EXPORT_SYMBOL(release_evntsel_nmi);
 898 EXPORT_SYMBOL(disable_timer_nmi_watchdog);
 899 EXPORT_SYMBOL(enable_timer_nmi_watchdog);