SAFE public projects git trees. - safe/jmp/linux-2.6/blob - arch/blackfin/mach-common/ints-priority.c

   1 /*
   2  * Set up the interrupt priorities
   3  *
   4  * Copyright  2004-2009 Analog Devices Inc.
   5  *                 2003 Bas Vermeulen <bas@buyways.nl>
   6  *                 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
   7  *            2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
   8  *                 1999 D. Jeff Dionne <jeff@uclinux.org>
   9  *                 1996 Roman Zippel
  10  *
  11  * Licensed under the GPL-2
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/kernel_stat.h>
  16 #include <linux/seq_file.h>
  17 #include <linux/irq.h>
  18 #ifdef CONFIG_IPIPE
  19 #include <linux/ipipe.h>
  20 #endif
  21 #ifdef CONFIG_KGDB
  22 #include <linux/kgdb.h>
  23 #endif
  24 #include <asm/traps.h>
  25 #include <asm/blackfin.h>
  26 #include <asm/gpio.h>
  27 #include <asm/irq_handler.h>
  28 #include <asm/dpmc.h>
  29 #include <asm/bfin5xx_spi.h>
  30 #include <asm/bfin_sport.h>
  31 #include <asm/bfin_can.h>
  32
  33 #define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
  34
  35 #ifdef BF537_FAMILY
  36 # define BF537_GENERIC_ERROR_INT_DEMUX
  37 # define SPI_ERR_MASK   (BIT_STAT_TXCOL | BIT_STAT_RBSY | BIT_STAT_MODF | BIT_STAT_TXE) /* SPI_STAT */
  38 # define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF)     /* SPORT_STAT */
  39 # define PPI_ERR_MASK   (0xFFFF & ~FLD) /* PPI_STATUS */
  40 # define EMAC_ERR_MASK  (PHYINT | MMCINT | RXFSINT | TXFSINT | WAKEDET | RXDMAERR | TXDMAERR | STMDONE) /* EMAC_SYSTAT */
  41 # define UART_ERR_MASK  (0x6)   /* UART_IIR */
  42 # define CAN_ERR_MASK   (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | RMLIF | UCEIF | EXTIF | ADIF)      /* CAN_GIF */
  43 #else
  44 # undef BF537_GENERIC_ERROR_INT_DEMUX
  45 #endif
  46
  47 /*
  48  * NOTES:
  49  * - we have separated the physical Hardware interrupt from the
  50  * levels that the LINUX kernel sees (see the description in irq.h)
  51  * -
  52  */
  53
  54 #ifndef CONFIG_SMP
  55 /* Initialize this to an actual value to force it into the .data
  56  * section so that we know it is properly initialized at entry into
  57  * the kernel but before bss is initialized to zero (which is where
  58  * it would live otherwise).  The 0x1f magic represents the IRQs we
  59  * cannot actually mask out in hardware.
  60  */
  61 unsigned long bfin_irq_flags = 0x1f;
  62 EXPORT_SYMBOL(bfin_irq_flags);
  63 #endif
  64
  65 /* The number of spurious interrupts */
  66 atomic_t num_spurious;
  67
  68 #ifdef CONFIG_PM
  69 unsigned long bfin_sic_iwr[3];  /* Up to 3 SIC_IWRx registers */
  70 unsigned vr_wakeup;
  71 #endif
  72
  73 struct ivgx {
  74         /* irq number for request_irq, available in mach-bf5xx/irq.h */
  75         unsigned int irqno;
  76         /* corresponding bit in the SIC_ISR register */
  77         unsigned int isrflag;
  78 } ivg_table[NR_PERI_INTS];
  79
  80 struct ivg_slice {
  81         /* position of first irq in ivg_table for given ivg */
  82         struct ivgx *ifirst;
  83         struct ivgx *istop;
  84 } ivg7_13[IVG13 - IVG7 + 1];
  85
  86
  87 /*
  88  * Search SIC_IAR and fill tables with the irqvalues
  89  * and their positions in the SIC_ISR register.
  90  */
  91 static void __init search_IAR(void)
  92 {
  93         unsigned ivg, irq_pos = 0;
  94         for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
  95                 int irqn;
  96
  97                 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
  98
  99                 for (irqn = 0; irqn < NR_PERI_INTS; irqn++) {
 100                         int iar_shift = (irqn & 7) * 4;
 101                                 if (ivg == (0xf &
 102 #if defined(CONFIG_BF52x) || defined(CONFIG_BF538) \
 103         || defined(CONFIG_BF539) || defined(CONFIG_BF51x)
 104                              bfin_read32((unsigned long *)SIC_IAR0 +
 105                                          ((irqn % 32) >> 3) + ((irqn / 32) *
 106                                          ((SIC_IAR4 - SIC_IAR0) / 4))) >> iar_shift)) {
 107 #else
 108                              bfin_read32((unsigned long *)SIC_IAR0 +
 109                                          (irqn >> 3)) >> iar_shift)) {
 110 #endif
 111                                 ivg_table[irq_pos].irqno = IVG7 + irqn;
 112                                 ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
 113                                 ivg7_13[ivg].istop++;
 114                                 irq_pos++;
 115                         }
 116                 }
 117         }
 118 }
 119
 120 /*
 121  * This is for core internal IRQs
 122  */
 123
 124 static void bfin_ack_noop(unsigned int irq)
 125 {
 126         /* Dummy function.  */
 127 }
 128
 129 static void bfin_core_mask_irq(unsigned int irq)
 130 {
 131         bfin_irq_flags &= ~(1 << irq);
 132         if (!irqs_disabled_hw())
 133                 local_irq_enable_hw();
 134 }
 135
 136 static void bfin_core_unmask_irq(unsigned int irq)
 137 {
 138         bfin_irq_flags |= 1 << irq;
 139         /*
 140          * If interrupts are enabled, IMASK must contain the same value
 141          * as bfin_irq_flags.  Make sure that invariant holds.  If interrupts
 142          * are currently disabled we need not do anything; one of the
 143          * callers will take care of setting IMASK to the proper value
 144          * when reenabling interrupts.
 145          * local_irq_enable just does "STI bfin_irq_flags", so it's exactly
 146          * what we need.
 147          */
 148         if (!irqs_disabled_hw())
 149                 local_irq_enable_hw();
 150         return;
 151 }
 152
 153 static void bfin_internal_mask_irq(unsigned int irq)
 154 {
 155         unsigned long flags;
 156
 157 #ifdef CONFIG_BF53x
 158         local_irq_save_hw(flags);
 159         bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
 160                              ~(1 << SIC_SYSIRQ(irq)));
 161 #else
 162         unsigned mask_bank, mask_bit;
 163         local_irq_save_hw(flags);
 164         mask_bank = SIC_SYSIRQ(irq) / 32;
 165         mask_bit = SIC_SYSIRQ(irq) % 32;
 166         bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
 167                              ~(1 << mask_bit));
 168 #ifdef CONFIG_SMP
 169         bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) &
 170                              ~(1 << mask_bit));
 171 #endif
 172 #endif
 173         local_irq_restore_hw(flags);
 174 }
 175
 176 #ifdef CONFIG_SMP
 177 static void bfin_internal_unmask_irq_affinity(unsigned int irq,
 178                 const struct cpumask *affinity)
 179 #else
 180 static void bfin_internal_unmask_irq(unsigned int irq)
 181 #endif
 182 {
 183         unsigned long flags;
 184
 185 #ifdef CONFIG_BF53x
 186         local_irq_save_hw(flags);
 187         bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
 188                              (1 << SIC_SYSIRQ(irq)));
 189 #else
 190         unsigned mask_bank, mask_bit;
 191         local_irq_save_hw(flags);
 192         mask_bank = SIC_SYSIRQ(irq) / 32;
 193         mask_bit = SIC_SYSIRQ(irq) % 32;
 194 #ifdef CONFIG_SMP
 195         if (cpumask_test_cpu(0, affinity))
 196 #endif
 197                 bfin_write_SIC_IMASK(mask_bank,
 198                         bfin_read_SIC_IMASK(mask_bank) |
 199                         (1 << mask_bit));
 200 #ifdef CONFIG_SMP
 201         if (cpumask_test_cpu(1, affinity))
 202                 bfin_write_SICB_IMASK(mask_bank,
 203                         bfin_read_SICB_IMASK(mask_bank) |
 204                         (1 << mask_bit));
 205 #endif
 206 #endif
 207         local_irq_restore_hw(flags);
 208 }
 209
 210 #ifdef CONFIG_SMP
 211 static void bfin_internal_unmask_irq(unsigned int irq)
 212 {
 213         struct irq_desc *desc = irq_to_desc(irq);
 214         bfin_internal_unmask_irq_affinity(irq, desc->affinity);
 215 }
 216
 217 static int bfin_internal_set_affinity(unsigned int irq, const struct cpumask *mask)
 218 {
 219         bfin_internal_mask_irq(irq);
 220         bfin_internal_unmask_irq_affinity(irq, mask);
 221
 222         return 0;
 223 }
 224 #endif
 225
 226 #ifdef CONFIG_PM
 227 int bfin_internal_set_wake(unsigned int irq, unsigned int state)
 228 {
 229         u32 bank, bit, wakeup = 0;
 230         unsigned long flags;
 231         bank = SIC_SYSIRQ(irq) / 32;
 232         bit = SIC_SYSIRQ(irq) % 32;
 233
 234         switch (irq) {
 235 #ifdef IRQ_RTC
 236         case IRQ_RTC:
 237         wakeup |= WAKE;
 238         break;
 239 #endif
 240 #ifdef IRQ_CAN0_RX
 241         case IRQ_CAN0_RX:
 242         wakeup |= CANWE;
 243         break;
 244 #endif
 245 #ifdef IRQ_CAN1_RX
 246         case IRQ_CAN1_RX:
 247         wakeup |= CANWE;
 248         break;
 249 #endif
 250 #ifdef IRQ_USB_INT0
 251         case IRQ_USB_INT0:
 252         wakeup |= USBWE;
 253         break;
 254 #endif
 255 #ifdef CONFIG_BF54x
 256         case IRQ_CNT:
 257         wakeup |= ROTWE;
 258         break;
 259 #endif
 260         default:
 261         break;
 262         }
 263
 264         local_irq_save_hw(flags);
 265
 266         if (state) {
 267                 bfin_sic_iwr[bank] |= (1 << bit);
 268                 vr_wakeup  |= wakeup;
 269
 270         } else {
 271                 bfin_sic_iwr[bank] &= ~(1 << bit);
 272                 vr_wakeup  &= ~wakeup;
 273         }
 274
 275         local_irq_restore_hw(flags);
 276
 277         return 0;
 278 }
 279 #endif
 280
 281 static struct irq_chip bfin_core_irqchip = {
 282         .name = "CORE",
 283         .ack = bfin_ack_noop,
 284         .mask = bfin_core_mask_irq,
 285         .unmask = bfin_core_unmask_irq,
 286 };
 287
 288 static struct irq_chip bfin_internal_irqchip = {
 289         .name = "INTN",
 290         .ack = bfin_ack_noop,
 291         .mask = bfin_internal_mask_irq,
 292         .unmask = bfin_internal_unmask_irq,
 293         .mask_ack = bfin_internal_mask_irq,
 294         .disable = bfin_internal_mask_irq,
 295         .enable = bfin_internal_unmask_irq,
 296 #ifdef CONFIG_SMP
 297         .set_affinity = bfin_internal_set_affinity,
 298 #endif
 299 #ifdef CONFIG_PM
 300         .set_wake = bfin_internal_set_wake,
 301 #endif
 302 };
 303
 304 static void bfin_handle_irq(unsigned irq)
 305 {
 306 #ifdef CONFIG_IPIPE
 307         struct pt_regs regs;    /* Contents not used. */
 308         ipipe_trace_irq_entry(irq);
 309         __ipipe_handle_irq(irq, &regs);
 310         ipipe_trace_irq_exit(irq);
 311 #else /* !CONFIG_IPIPE */
 312         struct irq_desc *desc = irq_desc + irq;
 313         desc->handle_irq(irq, desc);
 314 #endif  /* !CONFIG_IPIPE */
 315 }
 316
 317 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
 318 static int error_int_mask;
 319
 320 static void bfin_generic_error_mask_irq(unsigned int irq)
 321 {
 322         error_int_mask &= ~(1L << (irq - IRQ_PPI_ERROR));
 323         if (!error_int_mask)
 324                 bfin_internal_mask_irq(IRQ_GENERIC_ERROR);
 325 }
 326
 327 static void bfin_generic_error_unmask_irq(unsigned int irq)
 328 {
 329         bfin_internal_unmask_irq(IRQ_GENERIC_ERROR);
 330         error_int_mask |= 1L << (irq - IRQ_PPI_ERROR);
 331 }
 332
 333 static struct irq_chip bfin_generic_error_irqchip = {
 334         .name = "ERROR",
 335         .ack = bfin_ack_noop,
 336         .mask_ack = bfin_generic_error_mask_irq,
 337         .mask = bfin_generic_error_mask_irq,
 338         .unmask = bfin_generic_error_unmask_irq,
 339 };
 340
 341 static void bfin_demux_error_irq(unsigned int int_err_irq,
 342                                  struct irq_desc *inta_desc)
 343 {
 344         int irq = 0;
 345
 346 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
 347         if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
 348                 irq = IRQ_MAC_ERROR;
 349         else
 350 #endif
 351         if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
 352                 irq = IRQ_SPORT0_ERROR;
 353         else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
 354                 irq = IRQ_SPORT1_ERROR;
 355         else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
 356                 irq = IRQ_PPI_ERROR;
 357         else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
 358                 irq = IRQ_CAN_ERROR;
 359         else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
 360                 irq = IRQ_SPI_ERROR;
 361         else if ((bfin_read_UART0_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
 362                 irq = IRQ_UART0_ERROR;
 363         else if ((bfin_read_UART1_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
 364                 irq = IRQ_UART1_ERROR;
 365
 366         if (irq) {
 367                 if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR)))
 368                         bfin_handle_irq(irq);
 369                 else {
 370
 371                         switch (irq) {
 372                         case IRQ_PPI_ERROR:
 373                                 bfin_write_PPI_STATUS(PPI_ERR_MASK);
 374                                 break;
 375 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
 376                         case IRQ_MAC_ERROR:
 377                                 bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
 378                                 break;
 379 #endif
 380                         case IRQ_SPORT0_ERROR:
 381                                 bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
 382                                 break;
 383
 384                         case IRQ_SPORT1_ERROR:
 385                                 bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
 386                                 break;
 387
 388                         case IRQ_CAN_ERROR:
 389                                 bfin_write_CAN_GIS(CAN_ERR_MASK);
 390                                 break;
 391
 392                         case IRQ_SPI_ERROR:
 393                                 bfin_write_SPI_STAT(SPI_ERR_MASK);
 394                                 break;
 395
 396                         default:
 397                                 break;
 398                         }
 399
 400                         pr_debug("IRQ %d:"
 401                                  " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
 402                                  irq);
 403                 }
 404         } else
 405                 printk(KERN_ERR
 406                        "%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR"
 407                        " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
 408                        __func__, __FILE__, __LINE__);
 409
 410 }
 411 #endif                          /* BF537_GENERIC_ERROR_INT_DEMUX */
 412
 413 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
 414 static int mac_stat_int_mask;
 415
 416 static void bfin_mac_status_ack_irq(unsigned int irq)
 417 {
 418         switch (irq) {
 419         case IRQ_MAC_MMCINT:
 420                 bfin_write_EMAC_MMC_TIRQS(
 421                         bfin_read_EMAC_MMC_TIRQE() &
 422                         bfin_read_EMAC_MMC_TIRQS());
 423                 bfin_write_EMAC_MMC_RIRQS(
 424                         bfin_read_EMAC_MMC_RIRQE() &
 425                         bfin_read_EMAC_MMC_RIRQS());
 426                 break;
 427         case IRQ_MAC_RXFSINT:
 428                 bfin_write_EMAC_RX_STKY(
 429                         bfin_read_EMAC_RX_IRQE() &
 430                         bfin_read_EMAC_RX_STKY());
 431                 break;
 432         case IRQ_MAC_TXFSINT:
 433                 bfin_write_EMAC_TX_STKY(
 434                         bfin_read_EMAC_TX_IRQE() &
 435                         bfin_read_EMAC_TX_STKY());
 436                 break;
 437         case IRQ_MAC_WAKEDET:
 438                  bfin_write_EMAC_WKUP_CTL(
 439                         bfin_read_EMAC_WKUP_CTL() | MPKS | RWKS);
 440                 break;
 441         default:
 442                 /* These bits are W1C */
 443                 bfin_write_EMAC_SYSTAT(1L << (irq - IRQ_MAC_PHYINT));
 444                 break;
 445         }
 446 }
 447
 448 static void bfin_mac_status_mask_irq(unsigned int irq)
 449 {
 450         mac_stat_int_mask &= ~(1L << (irq - IRQ_MAC_PHYINT));
 451 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
 452         switch (irq) {
 453         case IRQ_MAC_PHYINT:
 454                 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() & ~PHYIE);
 455                 break;
 456         default:
 457                 break;
 458         }
 459 #else
 460         if (!mac_stat_int_mask)
 461                 bfin_internal_mask_irq(IRQ_MAC_ERROR);
 462 #endif
 463         bfin_mac_status_ack_irq(irq);
 464 }
 465
 466 static void bfin_mac_status_unmask_irq(unsigned int irq)
 467 {
 468 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
 469         switch (irq) {
 470         case IRQ_MAC_PHYINT:
 471                 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() | PHYIE);
 472                 break;
 473         default:
 474                 break;
 475         }
 476 #else
 477         if (!mac_stat_int_mask)
 478                 bfin_internal_unmask_irq(IRQ_MAC_ERROR);
 479 #endif
 480         mac_stat_int_mask |= 1L << (irq - IRQ_MAC_PHYINT);
 481 }
 482
 483 #ifdef CONFIG_PM
 484 int bfin_mac_status_set_wake(unsigned int irq, unsigned int state)
 485 {
 486 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
 487         return bfin_internal_set_wake(IRQ_GENERIC_ERROR, state);
 488 #else
 489         return bfin_internal_set_wake(IRQ_MAC_ERROR, state);
 490 #endif
 491 }
 492 #endif
 493
 494 static struct irq_chip bfin_mac_status_irqchip = {
 495         .name = "MACST",
 496         .ack = bfin_ack_noop,
 497         .mask_ack = bfin_mac_status_mask_irq,
 498         .mask = bfin_mac_status_mask_irq,
 499         .unmask = bfin_mac_status_unmask_irq,
 500 #ifdef CONFIG_PM
 501         .set_wake = bfin_mac_status_set_wake,
 502 #endif
 503 };
 504
 505 static void bfin_demux_mac_status_irq(unsigned int int_err_irq,
 506                                  struct irq_desc *inta_desc)
 507 {
 508         int i, irq = 0;
 509         u32 status = bfin_read_EMAC_SYSTAT();
 510
 511         for (i = 0; i < (IRQ_MAC_STMDONE - IRQ_MAC_PHYINT); i++)
 512                 if (status & (1L << i)) {
 513                         irq = IRQ_MAC_PHYINT + i;
 514                         break;
 515                 }
 516
 517         if (irq) {
 518                 if (mac_stat_int_mask & (1L << (irq - IRQ_MAC_PHYINT))) {
 519                         bfin_handle_irq(irq);
 520                 } else {
 521                         bfin_mac_status_ack_irq(irq);
 522                         pr_debug("IRQ %d:"
 523                                  " MASKED MAC ERROR INTERRUPT ASSERTED\n",
 524                                  irq);
 525                 }
 526         } else
 527                 printk(KERN_ERR
 528                        "%s : %s : LINE %d :\nIRQ ?: MAC ERROR"
 529                        " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
 530                        __func__, __FILE__, __LINE__);
 531 }
 532 #endif
 533
 534 static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
 535 {
 536 #ifdef CONFIG_IPIPE
 537         _set_irq_handler(irq, handle_level_irq);
 538 #else
 539         struct irq_desc *desc = irq_desc + irq;
 540         /* May not call generic set_irq_handler() due to spinlock
 541            recursion. */
 542         desc->handle_irq = handle;
 543 #endif
 544 }
 545
 546 static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS);
 547 extern void bfin_gpio_irq_prepare(unsigned gpio);
 548
 549 #if !defined(CONFIG_BF54x)
 550
 551 static void bfin_gpio_ack_irq(unsigned int irq)
 552 {
 553         /* AFAIK ack_irq in case mask_ack is provided
 554          * get's only called for edge sense irqs
 555          */
 556         set_gpio_data(irq_to_gpio(irq), 0);
 557 }
 558
 559 static void bfin_gpio_mask_ack_irq(unsigned int irq)
 560 {
 561         struct irq_desc *desc = irq_desc + irq;
 562         u32 gpionr = irq_to_gpio(irq);
 563
 564         if (desc->handle_irq == handle_edge_irq)
 565                 set_gpio_data(gpionr, 0);
 566
 567         set_gpio_maska(gpionr, 0);
 568 }
 569
 570 static void bfin_gpio_mask_irq(unsigned int irq)
 571 {
 572         set_gpio_maska(irq_to_gpio(irq), 0);
 573 }
 574
 575 static void bfin_gpio_unmask_irq(unsigned int irq)
 576 {
 577         set_gpio_maska(irq_to_gpio(irq), 1);
 578 }
 579
 580 static unsigned int bfin_gpio_irq_startup(unsigned int irq)
 581 {
 582         u32 gpionr = irq_to_gpio(irq);
 583
 584         if (__test_and_set_bit(gpionr, gpio_enabled))
 585                 bfin_gpio_irq_prepare(gpionr);
 586
 587         bfin_gpio_unmask_irq(irq);
 588
 589         return 0;
 590 }
 591
 592 static void bfin_gpio_irq_shutdown(unsigned int irq)
 593 {
 594         u32 gpionr = irq_to_gpio(irq);
 595
 596         bfin_gpio_mask_irq(irq);
 597         __clear_bit(gpionr, gpio_enabled);
 598         bfin_gpio_irq_free(gpionr);
 599 }
 600
 601 static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
 602 {
 603         int ret;
 604         char buf[16];
 605         u32 gpionr = irq_to_gpio(irq);
 606
 607         if (type == IRQ_TYPE_PROBE) {
 608                 /* only probe unenabled GPIO interrupt lines */
 609                 if (test_bit(gpionr, gpio_enabled))
 610                         return 0;
 611                 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
 612         }
 613
 614         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
 615                     IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
 616
 617                 snprintf(buf, 16, "gpio-irq%d", irq);
 618                 ret = bfin_gpio_irq_request(gpionr, buf);
 619                 if (ret)
 620                         return ret;
 621
 622                 if (__test_and_set_bit(gpionr, gpio_enabled))
 623                         bfin_gpio_irq_prepare(gpionr);
 624
 625         } else {
 626                 __clear_bit(gpionr, gpio_enabled);
 627                 return 0;
 628         }
 629
 630         set_gpio_inen(gpionr, 0);
 631         set_gpio_dir(gpionr, 0);
 632
 633         if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 634             == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 635                 set_gpio_both(gpionr, 1);
 636         else
 637                 set_gpio_both(gpionr, 0);
 638
 639         if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
 640                 set_gpio_polar(gpionr, 1);      /* low or falling edge denoted by one */
 641         else
 642                 set_gpio_polar(gpionr, 0);      /* high or rising edge denoted by zero */
 643
 644         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
 645                 set_gpio_edge(gpionr, 1);
 646                 set_gpio_inen(gpionr, 1);
 647                 set_gpio_data(gpionr, 0);
 648
 649         } else {
 650                 set_gpio_edge(gpionr, 0);
 651                 set_gpio_inen(gpionr, 1);
 652         }
 653
 654         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 655                 bfin_set_irq_handler(irq, handle_edge_irq);
 656         else
 657                 bfin_set_irq_handler(irq, handle_level_irq);
 658
 659         return 0;
 660 }
 661
 662 #ifdef CONFIG_PM
 663 int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
 664 {
 665         return gpio_pm_wakeup_ctrl(irq_to_gpio(irq), state);
 666 }
 667 #endif
 668
 669 static void bfin_demux_gpio_irq(unsigned int inta_irq,
 670                                 struct irq_desc *desc)
 671 {
 672         unsigned int i, gpio, mask, irq, search = 0;
 673
 674         switch (inta_irq) {
 675 #if defined(CONFIG_BF53x)
 676         case IRQ_PROG_INTA:
 677                 irq = IRQ_PF0;
 678                 search = 1;
 679                 break;
 680 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
 681         case IRQ_MAC_RX:
 682                 irq = IRQ_PH0;
 683                 break;
 684 # endif
 685 #elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
 686         case IRQ_PORTF_INTA:
 687                 irq = IRQ_PF0;
 688                 break;
 689 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
 690         case IRQ_PORTF_INTA:
 691                 irq = IRQ_PF0;
 692                 break;
 693         case IRQ_PORTG_INTA:
 694                 irq = IRQ_PG0;
 695                 break;
 696         case IRQ_PORTH_INTA:
 697                 irq = IRQ_PH0;
 698                 break;
 699 #elif defined(CONFIG_BF561)
 700         case IRQ_PROG0_INTA:
 701                 irq = IRQ_PF0;
 702                 break;
 703         case IRQ_PROG1_INTA:
 704                 irq = IRQ_PF16;
 705                 break;
 706         case IRQ_PROG2_INTA:
 707                 irq = IRQ_PF32;
 708                 break;
 709 #endif
 710         default:
 711                 BUG();
 712                 return;
 713         }
 714
 715         if (search) {
 716                 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
 717                         irq += i;
 718
 719                         mask = get_gpiop_data(i) & get_gpiop_maska(i);
 720
 721                         while (mask) {
 722                                 if (mask & 1)
 723                                         bfin_handle_irq(irq);
 724                                 irq++;
 725                                 mask >>= 1;
 726                         }
 727                 }
 728         } else {
 729                         gpio = irq_to_gpio(irq);
 730                         mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio);
 731
 732                         do {
 733                                 if (mask & 1)
 734                                         bfin_handle_irq(irq);
 735                                 irq++;
 736                                 mask >>= 1;
 737                         } while (mask);
 738         }
 739
 740 }
 741
 742 #else                           /* CONFIG_BF54x */
 743
 744 #define NR_PINT_SYS_IRQS        4
 745 #define NR_PINT_BITS            32
 746 #define NR_PINTS                160
 747 #define IRQ_NOT_AVAIL           0xFF
 748
 749 #define PINT_2_BANK(x)          ((x) >> 5)
 750 #define PINT_2_BIT(x)           ((x) & 0x1F)
 751 #define PINT_BIT(x)             (1 << (PINT_2_BIT(x)))
 752
 753 static unsigned char irq2pint_lut[NR_PINTS];
 754 static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
 755
 756 struct pin_int_t {
 757         unsigned int mask_set;
 758         unsigned int mask_clear;
 759         unsigned int request;
 760         unsigned int assign;
 761         unsigned int edge_set;
 762         unsigned int edge_clear;
 763         unsigned int invert_set;
 764         unsigned int invert_clear;
 765         unsigned int pinstate;
 766         unsigned int latch;
 767 };
 768
 769 static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = {
 770         (struct pin_int_t *)PINT0_MASK_SET,
 771         (struct pin_int_t *)PINT1_MASK_SET,
 772         (struct pin_int_t *)PINT2_MASK_SET,
 773         (struct pin_int_t *)PINT3_MASK_SET,
 774 };
 775
 776 inline unsigned int get_irq_base(u32 bank, u8 bmap)
 777 {
 778         unsigned int irq_base;
 779
 780         if (bank < 2) {         /*PA-PB */
 781                 irq_base = IRQ_PA0 + bmap * 16;
 782         } else {                /*PC-PJ */
 783                 irq_base = IRQ_PC0 + bmap * 16;
 784         }
 785
 786         return irq_base;
 787 }
 788
 789         /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
 790 void init_pint_lut(void)
 791 {
 792         u16 bank, bit, irq_base, bit_pos;
 793         u32 pint_assign;
 794         u8 bmap;
 795
 796         memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
 797
 798         for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
 799
 800                 pint_assign = pint[bank]->assign;
 801
 802                 for (bit = 0; bit < NR_PINT_BITS; bit++) {
 803
 804                         bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
 805
 806                         irq_base = get_irq_base(bank, bmap);
 807
 808                         irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
 809                         bit_pos = bit + bank * NR_PINT_BITS;
 810
 811                         pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
 812                         irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
 813                 }
 814         }
 815 }
 816
 817 static void bfin_gpio_ack_irq(unsigned int irq)
 818 {
 819         struct irq_desc *desc = irq_desc + irq;
 820         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 821         u32 pintbit = PINT_BIT(pint_val);
 822         u32 bank = PINT_2_BANK(pint_val);
 823
 824         if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
 825                 if (pint[bank]->invert_set & pintbit)
 826                         pint[bank]->invert_clear = pintbit;
 827                 else
 828                         pint[bank]->invert_set = pintbit;
 829         }
 830         pint[bank]->request = pintbit;
 831
 832 }
 833
 834 static void bfin_gpio_mask_ack_irq(unsigned int irq)
 835 {
 836         struct irq_desc *desc = irq_desc + irq;
 837         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 838         u32 pintbit = PINT_BIT(pint_val);
 839         u32 bank = PINT_2_BANK(pint_val);
 840
 841         if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
 842                 if (pint[bank]->invert_set & pintbit)
 843                         pint[bank]->invert_clear = pintbit;
 844                 else
 845                         pint[bank]->invert_set = pintbit;
 846         }
 847
 848         pint[bank]->request = pintbit;
 849         pint[bank]->mask_clear = pintbit;
 850 }
 851
 852 static void bfin_gpio_mask_irq(unsigned int irq)
 853 {
 854         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 855
 856         pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
 857 }
 858
 859 static void bfin_gpio_unmask_irq(unsigned int irq)
 860 {
 861         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 862         u32 pintbit = PINT_BIT(pint_val);
 863         u32 bank = PINT_2_BANK(pint_val);
 864
 865         pint[bank]->request = pintbit;
 866         pint[bank]->mask_set = pintbit;
 867 }
 868
 869 static unsigned int bfin_gpio_irq_startup(unsigned int irq)
 870 {
 871         u32 gpionr = irq_to_gpio(irq);
 872         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 873
 874         if (pint_val == IRQ_NOT_AVAIL) {
 875                 printk(KERN_ERR
 876                 "GPIO IRQ %d :Not in PINT Assign table "
 877                 "Reconfigure Interrupt to Port Assignemt\n", irq);
 878                 return -ENODEV;
 879         }
 880
 881         if (__test_and_set_bit(gpionr, gpio_enabled))
 882                 bfin_gpio_irq_prepare(gpionr);
 883
 884         bfin_gpio_unmask_irq(irq);
 885
 886         return 0;
 887 }
 888
 889 static void bfin_gpio_irq_shutdown(unsigned int irq)
 890 {
 891         u32 gpionr = irq_to_gpio(irq);
 892
 893         bfin_gpio_mask_irq(irq);
 894         __clear_bit(gpionr, gpio_enabled);
 895         bfin_gpio_irq_free(gpionr);
 896 }
 897
 898 static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
 899 {
 900         int ret;
 901         char buf[16];
 902         u32 gpionr = irq_to_gpio(irq);
 903         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 904         u32 pintbit = PINT_BIT(pint_val);
 905         u32 bank = PINT_2_BANK(pint_val);
 906
 907         if (pint_val == IRQ_NOT_AVAIL)
 908                 return -ENODEV;
 909
 910         if (type == IRQ_TYPE_PROBE) {
 911                 /* only probe unenabled GPIO interrupt lines */
 912                 if (test_bit(gpionr, gpio_enabled))
 913                         return 0;
 914                 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
 915         }
 916
 917         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
 918                     IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
 919
 920                 snprintf(buf, 16, "gpio-irq%d", irq);
 921                 ret = bfin_gpio_irq_request(gpionr, buf);
 922                 if (ret)
 923                         return ret;
 924
 925                 if (__test_and_set_bit(gpionr, gpio_enabled))
 926                         bfin_gpio_irq_prepare(gpionr);
 927
 928         } else {
 929                 __clear_bit(gpionr, gpio_enabled);
 930                 return 0;
 931         }
 932
 933         if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
 934                 pint[bank]->invert_set = pintbit;       /* low or falling edge denoted by one */
 935         else
 936                 pint[bank]->invert_clear = pintbit;     /* high or rising edge denoted by zero */
 937
 938         if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 939             == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
 940                 if (gpio_get_value(gpionr))
 941                         pint[bank]->invert_set = pintbit;
 942                 else
 943                         pint[bank]->invert_clear = pintbit;
 944         }
 945
 946         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
 947                 pint[bank]->edge_set = pintbit;
 948                 bfin_set_irq_handler(irq, handle_edge_irq);
 949         } else {
 950                 pint[bank]->edge_clear = pintbit;
 951                 bfin_set_irq_handler(irq, handle_level_irq);
 952         }
 953
 954         return 0;
 955 }
 956
 957 #ifdef CONFIG_PM
 958 u32 pint_saved_masks[NR_PINT_SYS_IRQS];
 959 u32 pint_wakeup_masks[NR_PINT_SYS_IRQS];
 960
 961 int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
 962 {
 963         u32 pint_irq;
 964         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 965         u32 bank = PINT_2_BANK(pint_val);
 966         u32 pintbit = PINT_BIT(pint_val);
 967
 968         switch (bank) {
 969         case 0:
 970                 pint_irq = IRQ_PINT0;
 971                 break;
 972         case 2:
 973                 pint_irq = IRQ_PINT2;
 974                 break;
 975         case 3:
 976                 pint_irq = IRQ_PINT3;
 977                 break;
 978         case 1:
 979                 pint_irq = IRQ_PINT1;
 980                 break;
 981         default:
 982                 return -EINVAL;
 983         }
 984
 985         bfin_internal_set_wake(pint_irq, state);
 986
 987         if (state)
 988                 pint_wakeup_masks[bank] |= pintbit;
 989         else
 990                 pint_wakeup_masks[bank] &= ~pintbit;
 991
 992         return 0;
 993 }
 994
 995 u32 bfin_pm_setup(void)
 996 {
 997         u32 val, i;
 998
 999         for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
1000                 val = pint[i]->mask_clear;
1001                 pint_saved_masks[i] = val;
1002                 if (val ^ pint_wakeup_masks[i]) {
1003                         pint[i]->mask_clear = val;
1004                         pint[i]->mask_set = pint_wakeup_masks[i];
1005                 }
1006         }
1007
1008         return 0;
1009 }
1010
1011 void bfin_pm_restore(void)
1012 {
1013         u32 i, val;
1014
1015         for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
1016                 val = pint_saved_masks[i];
1017                 if (val ^ pint_wakeup_masks[i]) {
1018                         pint[i]->mask_clear = pint[i]->mask_clear;
1019                         pint[i]->mask_set = val;
1020                 }
1021         }
1022 }
1023 #endif
1024
1025 static void bfin_demux_gpio_irq(unsigned int inta_irq,
1026                                 struct irq_desc *desc)
1027 {
1028         u32 bank, pint_val;
1029         u32 request, irq;
1030
1031         switch (inta_irq) {
1032         case IRQ_PINT0:
1033                 bank = 0;
1034                 break;
1035         case IRQ_PINT2:
1036                 bank = 2;
1037                 break;
1038         case IRQ_PINT3:
1039                 bank = 3;
1040                 break;
1041         case IRQ_PINT1:
1042                 bank = 1;
1043                 break;
1044         default:
1045                 return;
1046         }
1047
1048         pint_val = bank * NR_PINT_BITS;
1049
1050         request = pint[bank]->request;
1051
1052         while (request) {
1053                 if (request & 1) {
1054                         irq = pint2irq_lut[pint_val] + SYS_IRQS;
1055                         bfin_handle_irq(irq);
1056                 }
1057                 pint_val++;
1058                 request >>= 1;
1059         }
1060
1061 }
1062 #endif
1063
1064 static struct irq_chip bfin_gpio_irqchip = {
1065         .name = "GPIO",
1066         .ack = bfin_gpio_ack_irq,
1067         .mask = bfin_gpio_mask_irq,
1068         .mask_ack = bfin_gpio_mask_ack_irq,
1069         .unmask = bfin_gpio_unmask_irq,
1070         .disable = bfin_gpio_mask_irq,
1071         .enable = bfin_gpio_unmask_irq,
1072         .set_type = bfin_gpio_irq_type,
1073         .startup = bfin_gpio_irq_startup,
1074         .shutdown = bfin_gpio_irq_shutdown,
1075 #ifdef CONFIG_PM
1076         .set_wake = bfin_gpio_set_wake,
1077 #endif
1078 };
1079
1080 void __cpuinit init_exception_vectors(void)
1081 {
1082         /* cannot program in software:
1083          * evt0 - emulation (jtag)
1084          * evt1 - reset
1085          */
1086         bfin_write_EVT2(evt_nmi);
1087         bfin_write_EVT3(trap);
1088         bfin_write_EVT5(evt_ivhw);
1089         bfin_write_EVT6(evt_timer);
1090         bfin_write_EVT7(evt_evt7);
1091         bfin_write_EVT8(evt_evt8);
1092         bfin_write_EVT9(evt_evt9);
1093         bfin_write_EVT10(evt_evt10);
1094         bfin_write_EVT11(evt_evt11);
1095         bfin_write_EVT12(evt_evt12);
1096         bfin_write_EVT13(evt_evt13);
1097         bfin_write_EVT14(evt_evt14);
1098         bfin_write_EVT15(evt_system_call);
1099         CSYNC();
1100 }
1101
1102 /*
1103  * This function should be called during kernel startup to initialize
1104  * the BFin IRQ handling routines.
1105  */
1106
1107 int __init init_arch_irq(void)
1108 {
1109         int irq;
1110         unsigned long ilat = 0;
1111         /*  Disable all the peripheral intrs  - page 4-29 HW Ref manual */
1112 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \
1113         || defined(BF538_FAMILY) || defined(CONFIG_BF51x)
1114         bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
1115         bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
1116 # ifdef CONFIG_BF54x
1117         bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
1118 # endif
1119 # ifdef CONFIG_SMP
1120         bfin_write_SICB_IMASK0(SIC_UNMASK_ALL);
1121         bfin_write_SICB_IMASK1(SIC_UNMASK_ALL);
1122 # endif
1123 #else
1124         bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
1125 #endif
1126
1127         local_irq_disable();
1128
1129 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
1130         /* Clear EMAC Interrupt Status bits so we can demux it later */
1131         bfin_write_EMAC_SYSTAT(-1);
1132 #endif
1133
1134 #ifdef CONFIG_BF54x
1135 # ifdef CONFIG_PINTx_REASSIGN
1136         pint[0]->assign = CONFIG_PINT0_ASSIGN;
1137         pint[1]->assign = CONFIG_PINT1_ASSIGN;
1138         pint[2]->assign = CONFIG_PINT2_ASSIGN;
1139         pint[3]->assign = CONFIG_PINT3_ASSIGN;
1140 # endif
1141         /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
1142         init_pint_lut();
1143 #endif
1144
1145         for (irq = 0; irq <= SYS_IRQS; irq++) {
1146                 if (irq <= IRQ_CORETMR)
1147                         set_irq_chip(irq, &bfin_core_irqchip);
1148                 else
1149                         set_irq_chip(irq, &bfin_internal_irqchip);
1150
1151                 switch (irq) {
1152 #if defined(CONFIG_BF53x)
1153                 case IRQ_PROG_INTA:
1154 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
1155                 case IRQ_MAC_RX:
1156 # endif
1157 #elif defined(CONFIG_BF54x)
1158                 case IRQ_PINT0:
1159                 case IRQ_PINT1:
1160                 case IRQ_PINT2:
1161                 case IRQ_PINT3:
1162 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
1163                 case IRQ_PORTF_INTA:
1164                 case IRQ_PORTG_INTA:
1165                 case IRQ_PORTH_INTA:
1166 #elif defined(CONFIG_BF561)
1167                 case IRQ_PROG0_INTA:
1168                 case IRQ_PROG1_INTA:
1169                 case IRQ_PROG2_INTA:
1170 #elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
1171                 case IRQ_PORTF_INTA:
1172 #endif
1173                         set_irq_chained_handler(irq,
1174                                                 bfin_demux_gpio_irq);
1175                         break;
1176 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
1177                 case IRQ_GENERIC_ERROR:
1178                         set_irq_chained_handler(irq, bfin_demux_error_irq);
1179                         break;
1180 #endif
1181 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1182                 case IRQ_MAC_ERROR:
1183                         set_irq_chained_handler(irq, bfin_demux_mac_status_irq);
1184                         break;
1185 #endif
1186 #ifdef CONFIG_SMP
1187                 case IRQ_SUPPLE_0:
1188                 case IRQ_SUPPLE_1:
1189                         set_irq_handler(irq, handle_percpu_irq);
1190                         break;
1191 #endif
1192
1193 #ifdef CONFIG_TICKSOURCE_CORETMR
1194                 case IRQ_CORETMR:
1195 # ifdef CONFIG_SMP
1196                         set_irq_handler(irq, handle_percpu_irq);
1197                         break;
1198 # else
1199                         set_irq_handler(irq, handle_simple_irq);
1200                         break;
1201 # endif
1202 #endif
1203
1204 #ifdef CONFIG_TICKSOURCE_GPTMR0
1205                 case IRQ_TIMER0:
1206                         set_irq_handler(irq, handle_simple_irq);
1207                         break;
1208 #endif
1209
1210 #ifdef CONFIG_IPIPE
1211                 default:
1212                         set_irq_handler(irq, handle_level_irq);
1213                         break;
1214 #else /* !CONFIG_IPIPE */
1215                 default:
1216                         set_irq_handler(irq, handle_simple_irq);
1217                         break;
1218 #endif /* !CONFIG_IPIPE */
1219                 }
1220         }
1221
1222 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
1223         for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++)
1224                 set_irq_chip_and_handler(irq, &bfin_generic_error_irqchip,
1225                                          handle_level_irq);
1226 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1227         set_irq_chained_handler(IRQ_MAC_ERROR, bfin_demux_mac_status_irq);
1228 #endif
1229 #endif
1230
1231 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1232         for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++)
1233                 set_irq_chip_and_handler(irq, &bfin_mac_status_irqchip,
1234                                          handle_level_irq);
1235 #endif
1236         /* if configured as edge, then will be changed to do_edge_IRQ */
1237         for (irq = GPIO_IRQ_BASE;
1238                 irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
1239                 set_irq_chip_and_handler(irq, &bfin_gpio_irqchip,
1240                                          handle_level_irq);
1241
1242         bfin_write_IMASK(0);
1243         CSYNC();
1244         ilat = bfin_read_ILAT();
1245         CSYNC();
1246         bfin_write_ILAT(ilat);
1247         CSYNC();
1248
1249         printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
1250         /* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx,
1251          * local_irq_enable()
1252          */
1253         program_IAR();
1254         /* Therefore it's better to setup IARs before interrupts enabled */
1255         search_IAR();
1256
1257         /* Enable interrupts IVG7-15 */
1258         bfin_irq_flags |= IMASK_IVG15 |
1259             IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
1260             IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1261
1262         /* This implicitly covers ANOMALY_05000171
1263          * Boot-ROM code modifies SICA_IWRx wakeup registers
1264          */
1265 #ifdef SIC_IWR0
1266         bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
1267 # ifdef SIC_IWR1
1268         /* BF52x/BF51x system reset does not properly reset SIC_IWR1 which
1269          * will screw up the bootrom as it relies on MDMA0/1 waking it
1270          * up from IDLE instructions.  See this report for more info:
1271          * http://blackfin.uclinux.org/gf/tracker/4323
1272          */
1273         if (ANOMALY_05000435)
1274                 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
1275         else
1276                 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
1277 # endif
1278 # ifdef SIC_IWR2
1279         bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
1280 # endif
1281 #else
1282         bfin_write_SIC_IWR(IWR_DISABLE_ALL);
1283 #endif
1284
1285         return 0;
1286 }
1287
1288 #ifdef CONFIG_DO_IRQ_L1
1289 __attribute__((l1_text))
1290 #endif
1291 void do_irq(int vec, struct pt_regs *fp)
1292 {
1293         if (vec == EVT_IVTMR_P) {
1294                 vec = IRQ_CORETMR;
1295         } else {
1296                 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
1297                 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
1298 #if defined(SIC_ISR0) || defined(SICA_ISR0)
1299                 unsigned long sic_status[3];
1300
1301                 if (smp_processor_id()) {
1302 # ifdef SICB_ISR0
1303                         /* This will be optimized out in UP mode. */
1304                         sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0();
1305                         sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1();
1306 # endif
1307                 } else {
1308                         sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1309                         sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1310                 }
1311 # ifdef SIC_ISR2
1312                 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1313 # endif
1314                 for (;; ivg++) {
1315                         if (ivg >= ivg_stop) {
1316                                 atomic_inc(&num_spurious);
1317                                 return;
1318                         }
1319                         if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1320                                 break;
1321                 }
1322 #else
1323                 unsigned long sic_status;
1324
1325                 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1326
1327                 for (;; ivg++) {
1328                         if (ivg >= ivg_stop) {
1329                                 atomic_inc(&num_spurious);
1330                                 return;
1331                         } else if (sic_status & ivg->isrflag)
1332                                 break;
1333                 }
1334 #endif
1335                 vec = ivg->irqno;
1336         }
1337         asm_do_IRQ(vec, fp);
1338 }
1339
1340 #ifdef CONFIG_IPIPE
1341
1342 int __ipipe_get_irq_priority(unsigned irq)
1343 {
1344         int ient, prio;
1345
1346         if (irq <= IRQ_CORETMR)
1347                 return irq;
1348
1349         for (ient = 0; ient < NR_PERI_INTS; ient++) {
1350                 struct ivgx *ivg = ivg_table + ient;
1351                 if (ivg->irqno == irq) {
1352                         for (prio = 0; prio <= IVG13-IVG7; prio++) {
1353                                 if (ivg7_13[prio].ifirst <= ivg &&
1354                                     ivg7_13[prio].istop > ivg)
1355                                         return IVG7 + prio;
1356                         }
1357                 }
1358         }
1359
1360         return IVG15;
1361 }
1362
1363 /* Hw interrupts are disabled on entry (check SAVE_CONTEXT). */
1364 #ifdef CONFIG_DO_IRQ_L1
1365 __attribute__((l1_text))
1366 #endif
1367 asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
1368 {
1369         struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr();
1370         struct ipipe_domain *this_domain = __ipipe_current_domain;
1371         struct ivgx *ivg_stop = ivg7_13[vec-IVG7].istop;
1372         struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst;
1373         int irq, s;
1374
1375         if (likely(vec == EVT_IVTMR_P))
1376                 irq = IRQ_CORETMR;
1377         else {
1378 #if defined(SIC_ISR0) || defined(SICA_ISR0)
1379                 unsigned long sic_status[3];
1380
1381                 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1382                 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1383 # ifdef SIC_ISR2
1384                 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1385 # endif
1386                 for (;; ivg++) {
1387                         if (ivg >= ivg_stop) {
1388                                 atomic_inc(&num_spurious);
1389                                 return 0;
1390                         }
1391                         if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1392                                 break;
1393                 }
1394 #else
1395                 unsigned long sic_status;
1396
1397                 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1398
1399                 for (;; ivg++) {
1400                         if (ivg >= ivg_stop) {
1401                                 atomic_inc(&num_spurious);
1402                                 return 0;
1403                         } else if (sic_status & ivg->isrflag)
1404                                 break;
1405                 }
1406 #endif
1407                 irq = ivg->irqno;
1408         }
1409
1410         if (irq == IRQ_SYSTMR) {
1411 #if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_TICKSOURCE_GPTMR0)
1412                 bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */
1413 #endif
1414                 /* This is basically what we need from the register frame. */
1415                 __raw_get_cpu_var(__ipipe_tick_regs).ipend = regs->ipend;
1416                 __raw_get_cpu_var(__ipipe_tick_regs).pc = regs->pc;
1417                 if (this_domain != ipipe_root_domain)
1418                         __raw_get_cpu_var(__ipipe_tick_regs).ipend &= ~0x10;
1419                 else
1420                         __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10;
1421         }
1422
1423         if (this_domain == ipipe_root_domain) {
1424                 s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1425                 barrier();
1426         }
1427
1428         ipipe_trace_irq_entry(irq);
1429         __ipipe_handle_irq(irq, regs);
1430         ipipe_trace_irq_exit(irq);
1431
1432         if (this_domain == ipipe_root_domain) {
1433                 set_thread_flag(TIF_IRQ_SYNC);
1434                 if (!s) {
1435                         __clear_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1436                         return !test_bit(IPIPE_STALL_FLAG, &p->status);
1437                 }
1438         }
1439
1440         return 0;
1441 }
1442
1443 #endif /* CONFIG_IPIPE */