2 * Blackfin cache control code
4 * Copyright 2004-2008 Analog Devices Inc.
6 * Enter bugs at http://blackfin.uclinux.org/
8 * Licensed under the GPL-2 or later.
11 #include <linux/linkage.h>
12 #include <asm/blackfin.h>
13 #include <asm/cache.h>
18 /* Since all L1 caches work the same way, we use the same method for flushing
19 * them. Only the actual flush instruction differs. We write this in asm as
20 * GCC can be hard to coax into writing nice hardware loops.
22 * Also, we assume the following register setup:
26 .macro do_flush flushins:req optflushins optnopins label
30 /* start = (start & -L1_CACHE_BYTES) */
33 /* end = ((end - 1) & -L1_CACHE_BYTES) + L1_CACHE_BYTES; */
38 /* count = (end - start) >> L1_CACHE_SHIFT */
40 R2 >>= L1_CACHE_SHIFT;
47 LSETUP (1f, 2f) LC1 = P1;
67 /* Invalidate all instruction cache lines assocoiated with this memory area */
68 ENTRY(_blackfin_icache_flush_range)
70 * Walkaround to avoid loading wrong instruction after invalidating icache
71 * and following sequence is met.
73 * 1) One instruction address is cached in the instruction cache.
74 * 2) This instruction in SDRAM is changed.
75 * 3) IFLASH[P0] is executed only once in blackfin_icache_flush_range().
76 * 4) This instruction is executed again, but the old one is loaded.
80 do_flush IFLUSH, , nop
81 ENDPROC(_blackfin_icache_flush_range)
83 /* Throw away all D-cached data in specified region without any obligation to
84 * write them back. Since the Blackfin ISA does not have an "invalidate"
85 * instruction, we use flush/invalidate. Perhaps as a speed optimization we
86 * could bang on the DTEST MMRs ...
88 ENTRY(_blackfin_dcache_invalidate_range)
90 ENDPROC(_blackfin_dcache_invalidate_range)
92 /* Flush all data cache lines assocoiated with this memory area */
93 ENTRY(_blackfin_dcache_flush_range)
94 do_flush FLUSH, , , .Ldfr
95 ENDPROC(_blackfin_dcache_flush_range)
97 /* Our headers convert the page structure to an address, so just need to flush
98 * its contents like normal. We know the start address is page aligned (which
99 * greater than our cache alignment), as is the end address. So just jump into
100 * the middle of the dcache flush function.
102 ENTRY(_blackfin_dflush_page)
103 P1 = 1 << (PAGE_SHIFT - L1_CACHE_SHIFT);
105 ENDPROC(_blackfin_dflush_page)