2 * Copyright 2008-2009 Analog Devices Inc.
4 * Licensed under the ADI BSD license or the GPL-2 (or later)
10 /* Include all Core registers and bit definitions */
11 #include <asm/def_LPBlackfin.h>
13 /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF516 */
15 /* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
16 #include "defBF51x_base.h"
18 /* The following are the #defines needed by ADSP-BF516 that are not in the common header */
19 /* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
21 #define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
22 #define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
23 #define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
24 #define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
25 #define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
26 #define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */
27 #define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */
28 #define EMAC_FLC 0xFFC0301C /* Flow Control Register */
29 #define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */
30 #define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */
31 #define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */
32 #define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
33 #define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
34 #define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
35 #define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
36 #define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */
37 #define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
38 #define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
39 #define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
41 #define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */
42 #define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */
43 #define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */
44 #define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */
45 #define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */
46 #define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */
47 #define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */
48 #define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */
50 #define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */
51 #define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */
52 #define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */
53 #define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */
54 #define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */
56 #define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */
57 #define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */
58 #define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */
59 #define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */
60 #define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
61 #define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */
62 #define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */
63 #define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */
64 #define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */
65 #define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */
66 #define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */
67 #define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */
68 #define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */
69 #define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */
70 #define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */
71 #define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */
72 #define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */
73 #define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
74 #define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
75 #define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 < x < 128 */
76 #define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
77 #define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
78 #define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
79 #define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
81 #define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */
82 #define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */
83 #define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
84 #define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */
85 #define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
86 #define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */
87 #define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
88 #define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
89 #define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
90 #define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */
91 #define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */
92 #define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */
93 #define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */
94 #define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */
95 #define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */
96 #define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */
97 #define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
98 #define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 < x < 128 */
99 #define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
100 #define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
101 #define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
102 #define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
103 #define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */
105 /* Listing for IEEE-Supported Count Registers */
107 #define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */
108 #define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */
109 #define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */
110 #define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */
111 #define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */
112 #define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */
113 #define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */
114 #define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */
115 #define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */
116 #define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */
117 #define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */
118 #define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */
119 #define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */
120 #define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */
121 #define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */
122 #define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */
123 #define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */
124 #define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */
125 #define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */
126 #define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 < x < 128 */
127 #define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
128 #define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
129 #define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
130 #define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */
132 #define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */
133 #define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */
134 #define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */
135 #define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */
136 #define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */
137 #define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */
138 #define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */
139 #define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */
140 #define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */
141 #define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */
142 #define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */
143 #define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */
144 #define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */
145 #define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */
146 #define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */
147 #define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */
148 #define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */
149 #define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 < x < 128 */
150 #define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
151 #define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */
152 #define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
153 #define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */
154 #define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */
156 /***********************************************************************************
157 ** System MMR Register Bits And Macros
159 ** Disclaimer: All macros are intended to make C and Assembly code more readable.
160 ** Use these macros carefully, as any that do left shifts for field
161 ** depositing will result in the lower order bits being destroyed. Any
162 ** macro that shifts left to properly position the bit-field should be
163 ** used as part of an OR to initialize a register and NOT as a dynamic
164 ** modifier UNLESS the lower order bits are saved and ORed back in when
165 ** the macro is used.
166 *************************************************************************************/
168 /************************ ETHERNET 10/100 CONTROLLER MASKS ************************/
170 /* EMAC_OPMODE Masks */
172 #define RE 0x00000001 /* Receiver Enable */
173 #define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */
174 #define HU 0x00000010 /* Hash Filter Unicast Address */
175 #define HM 0x00000020 /* Hash Filter Multicast Address */
176 #define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */
177 #define PR 0x00000080 /* Promiscuous Mode Enable */
178 #define IFE 0x00000100 /* Inverse Filtering Enable */
179 #define DBF 0x00000200 /* Disable Broadcast Frame Reception */
180 #define PBF 0x00000400 /* Pass Bad Frames Enable */
181 #define PSF 0x00000800 /* Pass Short Frames Enable */
182 #define RAF 0x00001000 /* Receive-All Mode */
183 #define TE 0x00010000 /* Transmitter Enable */
184 #define DTXPAD 0x00020000 /* Disable Automatic TX Padding */
185 #define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */
186 #define DC 0x00080000 /* Deferral Check */
187 #define BOLMT 0x00300000 /* Back-Off Limit */
188 #define BOLMT_10 0x00000000 /* 10-bit range */
189 #define BOLMT_8 0x00100000 /* 8-bit range */
190 #define BOLMT_4 0x00200000 /* 4-bit range */
191 #define BOLMT_1 0x00300000 /* 1-bit range */
192 #define DRTY 0x00400000 /* Disable TX Retry On Collision */
193 #define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */
194 #define RMII 0x01000000 /* RMII/MII* Mode */
195 #define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */
196 #define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */
197 #define LB 0x08000000 /* Internal Loopback Enable */
198 #define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */
200 /* EMAC_STAADD Masks */
202 #define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */
203 #define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */
204 #define STADISPRE 0x00000004 /* Disable Preamble Generation */
205 #define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */
206 #define REGAD 0x000007C0 /* STA Register Address */
207 #define PHYAD 0x0000F800 /* PHY Device Address */
209 #define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */
210 #define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */
212 /* EMAC_STADAT Mask */
214 #define STADATA 0x0000FFFF /* Station Management Data */
218 #define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */
219 #define FLCE 0x00000002 /* Flow Control Enable */
220 #define PCF 0x00000004 /* Pass Control Frames */
221 #define BKPRSEN 0x00000008 /* Enable Backpressure */
222 #define FLCPAUSE 0xFFFF0000 /* Pause Time */
224 #define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */
226 /* EMAC_WKUP_CTL Masks */
228 #define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */
229 #define MPKE 0x00000002 /* Magic Packet Enable */
230 #define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */
231 #define GUWKE 0x00000008 /* Global Unicast Wake Enable */
232 #define MPKS 0x00000020 /* Magic Packet Received Status */
233 #define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */
235 /* EMAC_WKUP_FFCMD Masks */
237 #define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */
238 #define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */
239 #define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */
240 #define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */
241 #define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */
242 #define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */
243 #define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */
244 #define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */
246 /* EMAC_WKUP_FFOFF Masks */
248 #define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */
249 #define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */
250 #define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */
251 #define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */
253 #define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */
254 #define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */
255 #define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */
256 #define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */
257 /* Set ALL Offsets */
258 #define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
260 /* EMAC_WKUP_FFCRC0 Masks */
262 #define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */
263 #define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */
265 #define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */
266 #define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */
268 /* EMAC_WKUP_FFCRC1 Masks */
270 #define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */
271 #define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */
273 #define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */
274 #define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */
276 /* EMAC_SYSCTL Masks */
278 #define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */
279 #define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */
280 #define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */
281 #define TXDWA 0x00000010 /* Transmit Frame DMA Word Alignment (Odd/Even*) */
282 #define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
284 #define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */
286 /* EMAC_SYSTAT Masks */
288 #define PHYINT 0x00000001 /* PHY_INT Interrupt Status */
289 #define MMCINT 0x00000002 /* MMC Counter Interrupt Status */
290 #define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */
291 #define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */
292 #define WAKEDET 0x00000010 /* Wake-Up Detected Status */
293 #define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */
294 #define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */
295 #define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */
297 /* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
299 #define RX_FRLEN 0x000007FF /* Frame Length In Bytes */
300 #define RX_COMP 0x00001000 /* RX Frame Complete */
301 #define RX_OK 0x00002000 /* RX Frame Received With No Errors */
302 #define RX_LONG 0x00004000 /* RX Frame Too Long Error */
303 #define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */
304 #define RX_CRC 0x00010000 /* RX Frame CRC Error */
305 #define RX_LEN 0x00020000 /* RX Frame Length Error */
306 #define RX_FRAG 0x00040000 /* RX Frame Fragment Error */
307 #define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */
308 #define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */
309 #define RX_PHY 0x00200000 /* RX Frame PHY Error */
310 #define RX_LATE 0x00400000 /* RX Frame Late Collision Error */
311 #define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */
312 #define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */
313 #define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */
314 #define RX_CTL 0x04000000 /* RX Control Frame Indicator */
315 #define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */
316 #define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */
317 #define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */
318 #define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */
319 #define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */
321 /* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */
323 #define TX_COMP 0x00000001 /* TX Frame Complete */
324 #define TX_OK 0x00000002 /* TX Frame Sent With No Errors */
325 #define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */
326 #define TX_LATE 0x00000008 /* TX Frame Late Collision Error */
327 #define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */
328 #define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */
329 #define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */
330 #define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */
331 #define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */
332 #define TX_CCNT 0x00000F00 /* TX Frame Collision Count */
333 #define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */
334 #define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */
335 #define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */
336 #define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */
337 #define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */
339 /* EMAC_MMC_CTL Masks */
340 #define RSTC 0x00000001 /* Reset All Counters */
341 #define CROLL 0x00000002 /* Counter Roll-Over Enable */
342 #define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */
343 #define MMCE 0x00000008 /* Enable MMC Counter Operation */
345 /* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
346 #define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */
347 #define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */
348 #define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */
349 #define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */
350 #define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */
351 #define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */
352 #define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */
353 #define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */
354 #define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */
355 #define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */
356 #define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */
357 #define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */
358 #define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */
359 #define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */
360 #define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */
361 #define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */
362 #define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */
363 #define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */
364 #define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */
365 #define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */
366 #define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */
367 #define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */
368 #define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */
369 #define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */
371 /* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */
373 #define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */
374 #define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */
375 #define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */
376 #define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */
377 #define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */
378 #define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */
379 #define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */
380 #define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */
381 #define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */
382 #define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */
383 #define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */
384 #define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */
385 #define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */
386 #define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */
387 #define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */
388 #define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */
389 #define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */
390 #define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */
391 #define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */
392 #define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */
393 #define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */
394 #define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */
395 #define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */
399 #define SDH_PWR_CTL 0xFFC03900 /* SDH Power Control */
400 #define SDH_CLK_CTL 0xFFC03904 /* SDH Clock Control */
401 #define SDH_ARGUMENT 0xFFC03908 /* SDH Argument */
402 #define SDH_COMMAND 0xFFC0390C /* SDH Command */
403 #define SDH_RESP_CMD 0xFFC03910 /* SDH Response Command */
404 #define SDH_RESPONSE0 0xFFC03914 /* SDH Response0 */
405 #define SDH_RESPONSE1 0xFFC03918 /* SDH Response1 */
406 #define SDH_RESPONSE2 0xFFC0391C /* SDH Response2 */
407 #define SDH_RESPONSE3 0xFFC03920 /* SDH Response3 */
408 #define SDH_DATA_TIMER 0xFFC03924 /* SDH Data Timer */
409 #define SDH_DATA_LGTH 0xFFC03928 /* SDH Data Length */
410 #define SDH_DATA_CTL 0xFFC0392C /* SDH Data Control */
411 #define SDH_DATA_CNT 0xFFC03930 /* SDH Data Counter */
412 #define SDH_STATUS 0xFFC03934 /* SDH Status */
413 #define SDH_STATUS_CLR 0xFFC03938 /* SDH Status Clear */
414 #define SDH_MASK0 0xFFC0393C /* SDH Interrupt0 Mask */
415 #define SDH_MASK1 0xFFC03940 /* SDH Interrupt1 Mask */
416 #define SDH_FIFO_CNT 0xFFC03948 /* SDH FIFO Counter */
417 #define SDH_FIFO 0xFFC03980 /* SDH Data FIFO */
418 #define SDH_E_STATUS 0xFFC039C0 /* SDH Exception Status */
419 #define SDH_E_MASK 0xFFC039C4 /* SDH Exception Mask */
420 #define SDH_CFG 0xFFC039C8 /* SDH Configuration */
421 #define SDH_RD_WAIT_EN 0xFFC039CC /* SDH Read Wait Enable */
422 #define SDH_PID0 0xFFC039D0 /* SDH Peripheral Identification0 */
423 #define SDH_PID1 0xFFC039D4 /* SDH Peripheral Identification1 */
424 #define SDH_PID2 0xFFC039D8 /* SDH Peripheral Identification2 */
425 #define SDH_PID3 0xFFC039DC /* SDH Peripheral Identification3 */
426 #define SDH_PID4 0xFFC039E0 /* SDH Peripheral Identification4 */
427 #define SDH_PID5 0xFFC039E4 /* SDH Peripheral Identification5 */
428 #define SDH_PID6 0xFFC039E8 /* SDH Peripheral Identification6 */
429 #define SDH_PID7 0xFFC039EC /* SDH Peripheral Identification7 */
431 /* Removable Storage Interface Registers */
433 #define RSI_PWR_CONTROL 0xFFC03800 /* RSI Power Control Register */
434 #define RSI_CLK_CONTROL 0xFFC03804 /* RSI Clock Control Register */
435 #define RSI_ARGUMENT 0xFFC03808 /* RSI Argument Register */
436 #define RSI_COMMAND 0xFFC0380C /* RSI Command Register */
437 #define RSI_RESP_CMD 0xFFC03810 /* RSI Response Command Register */
438 #define RSI_RESPONSE0 0xFFC03814 /* RSI Response Register */
439 #define RSI_RESPONSE1 0xFFC03818 /* RSI Response Register */
440 #define RSI_RESPONSE2 0xFFC0381C /* RSI Response Register */
441 #define RSI_RESPONSE3 0xFFC03820 /* RSI Response Register */
442 #define RSI_DATA_TIMER 0xFFC03824 /* RSI Data Timer Register */
443 #define RSI_DATA_LGTH 0xFFC03828 /* RSI Data Length Register */
444 #define RSI_DATA_CONTROL 0xFFC0382C /* RSI Data Control Register */
445 #define RSI_DATA_CNT 0xFFC03830 /* RSI Data Counter Register */
446 #define RSI_STATUS 0xFFC03834 /* RSI Status Register */
447 #define RSI_STATUSCL 0xFFC03838 /* RSI Status Clear Register */
448 #define RSI_MASK0 0xFFC0383C /* RSI Interrupt 0 Mask Register */
449 #define RSI_MASK1 0xFFC03840 /* RSI Interrupt 1 Mask Register */
450 #define RSI_FIFO_CNT 0xFFC03848 /* RSI FIFO Counter Register */
451 #define RSI_CEATA_CONTROL 0xFFC0384C /* RSI CEATA Register */
452 #define RSI_FIFO 0xFFC03880 /* RSI Data FIFO Register */
453 #define RSI_ESTAT 0xFFC038C0 /* RSI Exception Status Register */
454 #define RSI_EMASK 0xFFC038C4 /* RSI Exception Mask Register */
455 #define RSI_CONFIG 0xFFC038C8 /* RSI Configuration Register */
456 #define RSI_RD_WAIT_EN 0xFFC038CC /* RSI Read Wait Enable Register */
457 #define RSI_PID0 0xFFC03FE0 /* RSI Peripheral ID Register 0 */
458 #define RSI_PID1 0xFFC03FE4 /* RSI Peripheral ID Register 1 */
459 #define RSI_PID2 0xFFC03FE8 /* RSI Peripheral ID Register 2 */
460 #define RSI_PID3 0xFFC03FEC /* RSI Peripheral ID Register 3 */
461 #define RSI_PID4 0xFFC03FF0 /* RSI Peripheral ID Register 4 */
462 #define RSI_PID5 0xFFC03FF4 /* RSI Peripheral ID Register 5 */
463 #define RSI_PID6 0xFFC03FF8 /* RSI Peripheral ID Register 6 */
464 #define RSI_PID7 0xFFC03FFC /* RSI Peripheral ID Register 7 */
466 /* ********************************************************** */
467 /* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
468 /* and MULTI BIT READ MACROS */
469 /* ********************************************************** */
471 /* Bit masks for SDH_COMMAND */
473 #define CMD_IDX 0x3f /* Command Index */
474 #define CMD_RSP 0x40 /* Response */
475 #define CMD_L_RSP 0x80 /* Long Response */
476 #define CMD_INT_E 0x100 /* Command Interrupt */
477 #define CMD_PEND_E 0x200 /* Command Pending */
478 #define CMD_E 0x400 /* Command Enable */
480 /* Bit masks for SDH_PWR_CTL */
482 #define PWR_ON 0x3 /* Power On */
484 #define TBD 0x3c /* TBD */
486 #define SD_CMD_OD 0x40 /* Open Drain Output */
487 #define ROD_CTL 0x80 /* Rod Control */
489 /* Bit masks for SDH_CLK_CTL */
491 #define CLKDIV 0xff /* MC_CLK Divisor */
492 #define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
493 #define PWR_SV_E 0x200 /* Power Save Enable */
494 #define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
495 #define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
497 /* Bit masks for SDH_RESP_CMD */
499 #define RESP_CMD 0x3f /* Response Command */
501 /* Bit masks for SDH_DATA_CTL */
503 #define DTX_E 0x1 /* Data Transfer Enable */
504 #define DTX_DIR 0x2 /* Data Transfer Direction */
505 #define DTX_MODE 0x4 /* Data Transfer Mode */
506 #define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
507 #define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
509 /* Bit masks for SDH_STATUS */
511 #define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
512 #define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
513 #define CMD_TIME_OUT 0x4 /* CMD Time Out */
514 #define DAT_TIME_OUT 0x8 /* Data Time Out */
515 #define TX_UNDERRUN 0x10 /* Transmit Underrun */
516 #define RX_OVERRUN 0x20 /* Receive Overrun */
517 #define CMD_RESP_END 0x40 /* CMD Response End */
518 #define CMD_SENT 0x80 /* CMD Sent */
519 #define DAT_END 0x100 /* Data End */
520 #define START_BIT_ERR 0x200 /* Start Bit Error */
521 #define DAT_BLK_END 0x400 /* Data Block End */
522 #define CMD_ACT 0x800 /* CMD Active */
523 #define TX_ACT 0x1000 /* Transmit Active */
524 #define RX_ACT 0x2000 /* Receive Active */
525 #define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
526 #define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
527 #define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
528 #define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
529 #define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
530 #define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
531 #define TX_DAT_RDY 0x100000 /* Transmit Data Available */
532 #define RX_FIFO_RDY 0x200000 /* Receive Data Available */
534 /* Bit masks for SDH_STATUS_CLR */
536 #define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
537 #define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
538 #define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
539 #define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
540 #define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
541 #define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
542 #define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
543 #define CMD_SENT_STAT 0x80 /* CMD Sent Status */
544 #define DAT_END_STAT 0x100 /* Data End Status */
545 #define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
546 #define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
548 /* Bit masks for SDH_MASK0 */
550 #define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
551 #define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
552 #define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
553 #define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
554 #define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
555 #define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
556 #define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
557 #define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
558 #define DAT_END_MASK 0x100 /* Data End Mask */
559 #define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
560 #define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
561 #define CMD_ACT_MASK 0x800 /* CMD Active Mask */
562 #define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
563 #define RX_ACT_MASK 0x2000 /* Receive Active Mask */
564 #define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
565 #define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
566 #define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
567 #define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
568 #define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
569 #define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
570 #define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
571 #define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
573 /* Bit masks for SDH_FIFO_CNT */
575 #define FIFO_COUNT 0x7fff /* FIFO Count */
577 /* Bit masks for SDH_E_STATUS */
579 #define SDIO_INT_DET 0x2 /* SDIO Int Detected */
580 #define SD_CARD_DET 0x10 /* SD Card Detect */
582 /* Bit masks for SDH_E_MASK */
584 #define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
585 #define SCD_MSK 0x40 /* Mask Card Detect */
587 /* Bit masks for SDH_CFG */
589 #define CLKS_EN 0x1 /* Clocks Enable */
590 #define SD4E 0x4 /* SDIO 4-Bit Enable */
591 #define MWE 0x8 /* Moving Window Enable */
592 #define SD_RST 0x10 /* SDMMC Reset */
593 #define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
594 #define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
595 #define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
597 /* Bit masks for SDH_RD_WAIT_EN */
599 #define RWR 0x1 /* Read Wait Request */
601 #endif /* _DEF_BF516_H */
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