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   1 /*
   2  * File:         arch/blackfin/kernel/setup.c
   3  * Based on:
   4  * Author:
   5  *
   6  * Created:
   7  * Description:
   8  *
   9  * Modified:
  10  *               Copyright 2004-2006 Analog Devices Inc.
  11  *
  12  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License as published by
  16  * the Free Software Foundation; either version 2 of the License, or
  17  * (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, see the file COPYING, or write
  26  * to the Free Software Foundation, Inc.,
  27  * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  28  */
  29
  30 #include <linux/delay.h>
  31 #include <linux/console.h>
  32 #include <linux/bootmem.h>
  33 #include <linux/seq_file.h>
  34 #include <linux/cpu.h>
  35 #include <linux/module.h>
  36 #include <linux/tty.h>
  37
  38 #include <linux/ext2_fs.h>
  39 #include <linux/cramfs_fs.h>
  40 #include <linux/romfs_fs.h>
  41
  42 #include <asm/cacheflush.h>
  43 #include <asm/blackfin.h>
  44 #include <asm/cplbinit.h>
  45 #include <asm/fixed_code.h>
  46
  47 u16 _bfin_swrst;
  48
  49 unsigned long memory_start, memory_end, physical_mem_end;
  50 unsigned long reserved_mem_dcache_on;
  51 unsigned long reserved_mem_icache_on;
  52 EXPORT_SYMBOL(memory_start);
  53 EXPORT_SYMBOL(memory_end);
  54 EXPORT_SYMBOL(physical_mem_end);
  55 EXPORT_SYMBOL(_ramend);
  56
  57 #ifdef CONFIG_MTD_UCLINUX
  58 unsigned long memory_mtd_end, memory_mtd_start, mtd_size;
  59 unsigned long _ebss;
  60 EXPORT_SYMBOL(memory_mtd_end);
  61 EXPORT_SYMBOL(memory_mtd_start);
  62 EXPORT_SYMBOL(mtd_size);
  63 #endif
  64
  65 char __initdata command_line[COMMAND_LINE_SIZE];
  66
  67 #if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE)
  68 static void generate_cpl_tables(void);
  69 #endif
  70
  71 void __init bf53x_cache_init(void)
  72 {
  73 #if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE)
  74         generate_cpl_tables();
  75 #endif
  76
  77 #ifdef CONFIG_BLKFIN_CACHE
  78         bfin_icache_init();
  79         printk(KERN_INFO "Instruction Cache Enabled\n");
  80 #endif
  81
  82 #ifdef CONFIG_BLKFIN_DCACHE
  83         bfin_dcache_init();
  84         printk(KERN_INFO "Data Cache Enabled"
  85 # if defined CONFIG_BLKFIN_WB
  86                 " (write-back)"
  87 # elif defined CONFIG_BLKFIN_WT
  88                 " (write-through)"
  89 # endif
  90                 "\n");
  91 #endif
  92 }
  93
  94 void __init bf53x_relocate_l1_mem(void)
  95 {
  96         unsigned long l1_code_length;
  97         unsigned long l1_data_a_length;
  98         unsigned long l1_data_b_length;
  99
 100         l1_code_length = _etext_l1 - _stext_l1;
 101         if (l1_code_length > L1_CODE_LENGTH)
 102                 l1_code_length = L1_CODE_LENGTH;
 103         /* cannot complain as printk is not available as yet.
 104          * But we can continue booting and complain later!
 105          */
 106
 107         /* Copy _stext_l1 to _etext_l1 to L1 instruction SRAM */
 108         dma_memcpy(_stext_l1, _l1_lma_start, l1_code_length);
 109
 110         l1_data_a_length = _ebss_l1 - _sdata_l1;
 111         if (l1_data_a_length > L1_DATA_A_LENGTH)
 112                 l1_data_a_length = L1_DATA_A_LENGTH;
 113
 114         /* Copy _sdata_l1 to _ebss_l1 to L1 data bank A SRAM */
 115         dma_memcpy(_sdata_l1, _l1_lma_start + l1_code_length, l1_data_a_length);
 116
 117         l1_data_b_length = _ebss_b_l1 - _sdata_b_l1;
 118         if (l1_data_b_length > L1_DATA_B_LENGTH)
 119                 l1_data_b_length = L1_DATA_B_LENGTH;
 120
 121         /* Copy _sdata_b_l1 to _ebss_b_l1 to L1 data bank B SRAM */
 122         dma_memcpy(_sdata_b_l1, _l1_lma_start + l1_code_length +
 123                         l1_data_a_length, l1_data_b_length);
 124
 125 }
 126
 127 /*
 128  * Initial parsing of the command line.  Currently, we support:
 129  *  - Controlling the linux memory size: mem=xxx[KMG]
 130  *  - Controlling the physical memory size: max_mem=xxx[KMG][$][#]
 131  *       $ -> reserved memory is dcacheable
 132  *       # -> reserved memory is icacheable
 133  */
 134 static __init void parse_cmdline_early(char *cmdline_p)
 135 {
 136         char c = ' ', *to = cmdline_p;
 137         unsigned int memsize;
 138         for (;;) {
 139                 if (c == ' ') {
 140
 141                         if (!memcmp(to, "mem=", 4)) {
 142                                 to += 4;
 143                                 memsize = memparse(to, &to);
 144                                 if (memsize)
 145                                         _ramend = memsize;
 146
 147                         } else if (!memcmp(to, "max_mem=", 8)) {
 148                                 to += 8;
 149                                 memsize = memparse(to, &to);
 150                                 if (memsize) {
 151                                         physical_mem_end = memsize;
 152                                         if (*to != ' ') {
 153                                                 if (*to == '$'
 154                                                     || *(to + 1) == '$')
 155                                                         reserved_mem_dcache_on =
 156                                                             1;
 157                                                 if (*to == '#'
 158                                                     || *(to + 1) == '#')
 159                                                         reserved_mem_icache_on =
 160                                                             1;
 161                                         }
 162                                 }
 163                         }
 164
 165                 }
 166                 c = *(to++);
 167                 if (!c)
 168                         break;
 169         }
 170 }
 171
 172 void __init setup_arch(char **cmdline_p)
 173 {
 174         int bootmap_size;
 175         unsigned long l1_length, sclk, cclk;
 176 #ifdef CONFIG_MTD_UCLINUX
 177         unsigned long mtd_phys = 0;
 178 #endif
 179
 180 #ifdef CONFIG_DUMMY_CONSOLE
 181         conswitchp = &dummy_con;
 182 #endif
 183         cclk = get_cclk();
 184         sclk = get_sclk();
 185
 186 #if !defined(CONFIG_BFIN_KERNEL_CLOCK) && defined(ANOMALY_05000273)
 187         if (cclk == sclk)
 188                 panic("ANOMALY 05000273, SCLK can not be same as CCLK");
 189 #endif
 190
 191 #if defined(ANOMALY_05000266)
 192         bfin_read_IMDMA_D0_IRQ_STATUS();
 193         bfin_read_IMDMA_D1_IRQ_STATUS();
 194 #endif
 195
 196 #ifdef DEBUG_SERIAL_EARLY_INIT
 197         bfin_console_init();    /* early console registration */
 198         /* this give a chance to get printk() working before crash. */
 199 #endif
 200
 201 #if defined(CONFIG_CHR_DEV_FLASH) || defined(CONFIG_BLK_DEV_FLASH)
 202         /* we need to initialize the Flashrom device here since we might
 203          * do things with flash early on in the boot
 204          */
 205         flash_probe();
 206 #endif
 207
 208 #if defined(CONFIG_CMDLINE_BOOL)
 209         strncpy(&command_line[0], CONFIG_CMDLINE, sizeof(command_line));
 210         command_line[sizeof(command_line) - 1] = 0;
 211 #endif
 212
 213         /* Keep a copy of command line */
 214         *cmdline_p = &command_line[0];
 215         memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
 216         boot_command_line[COMMAND_LINE_SIZE - 1] = '\0';
 217
 218         /* setup memory defaults from the user config */
 219         physical_mem_end = 0;
 220         _ramend = CONFIG_MEM_SIZE * 1024 * 1024;
 221
 222         parse_cmdline_early(&command_line[0]);
 223
 224         if (physical_mem_end == 0)
 225                 physical_mem_end = _ramend;
 226
 227         /* by now the stack is part of the init task */
 228         memory_end = _ramend - DMA_UNCACHED_REGION;
 229
 230         _ramstart = (unsigned long)__bss_stop;
 231         memory_start = PAGE_ALIGN(_ramstart);
 232
 233 #if defined(CONFIG_MTD_UCLINUX)
 234         /* generic memory mapped MTD driver */
 235         memory_mtd_end = memory_end;
 236
 237         mtd_phys = _ramstart;
 238         mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 8)));
 239
 240 # if defined(CONFIG_EXT2_FS) || defined(CONFIG_EXT3_FS)
 241         if (*((unsigned short *)(mtd_phys + 0x438)) == EXT2_SUPER_MAGIC)
 242                 mtd_size =
 243                     PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x404)) << 10);
 244 # endif
 245
 246 # if defined(CONFIG_CRAMFS)
 247         if (*((unsigned long *)(mtd_phys)) == CRAMFS_MAGIC)
 248                 mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x4)));
 249 # endif
 250
 251 # if defined(CONFIG_ROMFS_FS)
 252         if (((unsigned long *)mtd_phys)[0] == ROMSB_WORD0
 253             && ((unsigned long *)mtd_phys)[1] == ROMSB_WORD1)
 254                 mtd_size =
 255                     PAGE_ALIGN(be32_to_cpu(((unsigned long *)mtd_phys)[2]));
 256 #  if (defined(CONFIG_BLKFIN_CACHE) && defined(ANOMALY_05000263))
 257         /* Due to a Hardware Anomaly we need to limit the size of usable
 258          * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on
 259          * 05000263 - Hardware loop corrupted when taking an ICPLB exception
 260          */
 261 #   if (defined(CONFIG_DEBUG_HUNT_FOR_ZERO))
 262         if (memory_end >= 56 * 1024 * 1024)
 263                 memory_end = 56 * 1024 * 1024;
 264 #   else
 265         if (memory_end >= 60 * 1024 * 1024)
 266                 memory_end = 60 * 1024 * 1024;
 267 #   endif                               /* CONFIG_DEBUG_HUNT_FOR_ZERO */
 268 #  endif                                /* ANOMALY_05000263 */
 269 # endif                         /* CONFIG_ROMFS_FS */
 270
 271         memory_end -= mtd_size;
 272
 273         if (mtd_size == 0) {
 274                 console_init();
 275                 panic("Don't boot kernel without rootfs attached.\n");
 276         }
 277
 278         /* Relocate MTD image to the top of memory after the uncached memory area */
 279         dma_memcpy((char *)memory_end, __bss_stop, mtd_size);
 280
 281         memory_mtd_start = memory_end;
 282         _ebss = memory_mtd_start;       /* define _ebss for compatible */
 283 #endif                          /* CONFIG_MTD_UCLINUX */
 284
 285 #if (defined(CONFIG_BLKFIN_CACHE) && defined(ANOMALY_05000263))
 286         /* Due to a Hardware Anomaly we need to limit the size of usable
 287          * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on
 288          * 05000263 - Hardware loop corrupted when taking an ICPLB exception
 289          */
 290 #if (defined(CONFIG_DEBUG_HUNT_FOR_ZERO))
 291         if (memory_end >= 56 * 1024 * 1024)
 292                 memory_end = 56 * 1024 * 1024;
 293 #else
 294         if (memory_end >= 60 * 1024 * 1024)
 295                 memory_end = 60 * 1024 * 1024;
 296 #endif                          /* CONFIG_DEBUG_HUNT_FOR_ZERO */
 297         printk(KERN_NOTICE "Warning: limiting memory to %liMB due to hardware anomaly 05000263\n", memory_end >> 20);
 298 #endif                          /* ANOMALY_05000263 */
 299
 300 #if !defined(CONFIG_MTD_UCLINUX)
 301         memory_end -= SIZE_4K; /*In case there is no valid CPLB behind memory_end make sure we don't get to close*/
 302 #endif
 303         init_mm.start_code = (unsigned long)_stext;
 304         init_mm.end_code = (unsigned long)_etext;
 305         init_mm.end_data = (unsigned long)_edata;
 306         init_mm.brk = (unsigned long)0;
 307
 308         init_leds();
 309
 310         printk(KERN_INFO "Blackfin support (C) 2004-2007 Analog Devices, Inc.\n");
 311         if (bfin_compiled_revid() == 0xffff)
 312                 printk(KERN_INFO "Compiled for ADSP-%s Rev any\n", CPU);
 313         else if (bfin_compiled_revid() == -1)
 314                 printk(KERN_INFO "Compiled for ADSP-%s Rev none\n", CPU);
 315         else
 316                 printk(KERN_INFO "Compiled for ADSP-%s Rev 0.%d\n", CPU, bfin_compiled_revid());
 317         if (bfin_revid() != bfin_compiled_revid()) {
 318                 if (bfin_compiled_revid() == -1)
 319                         printk(KERN_ERR "Warning: Compiled for Rev none, but running on Rev %d\n",
 320                                bfin_revid());
 321                 else if (bfin_compiled_revid() != 0xffff)
 322                         printk(KERN_ERR "Warning: Compiled for Rev %d, but running on Rev %d\n",
 323                                bfin_compiled_revid(), bfin_revid());
 324         }
 325         if (bfin_revid() < SUPPORTED_REVID)
 326                 printk(KERN_ERR "Warning: Unsupported Chip Revision ADSP-%s Rev 0.%d detected\n",
 327                        CPU, bfin_revid());
 328         printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n");
 329
 330         printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu Mhz System Clock\n",
 331                cclk / 1000000,  sclk / 1000000);
 332
 333 #if defined(ANOMALY_05000273)
 334         if ((cclk >> 1) <= sclk)
 335                 printk("\n\n\nANOMALY_05000273: CCLK must be >= 2*SCLK !!!\n\n\n");
 336 #endif
 337
 338         printk(KERN_INFO "Board Memory: %ldMB\n", physical_mem_end >> 20);
 339         printk(KERN_INFO "Kernel Managed Memory: %ldMB\n", _ramend >> 20);
 340
 341         printk(KERN_INFO "Memory map:\n"
 342                KERN_INFO "  text      = 0x%p-0x%p\n"
 343                KERN_INFO "  rodata    = 0x%p-0x%p\n"
 344                KERN_INFO "  data      = 0x%p-0x%p\n"
 345                KERN_INFO "    stack   = 0x%p-0x%p\n"
 346                KERN_INFO "  init      = 0x%p-0x%p\n"
 347                KERN_INFO "  bss       = 0x%p-0x%p\n"
 348                KERN_INFO "  available = 0x%p-0x%p\n"
 349 #ifdef CONFIG_MTD_UCLINUX
 350                KERN_INFO "  rootfs    = 0x%p-0x%p\n"
 351 #endif
 352 #if DMA_UNCACHED_REGION > 0
 353                KERN_INFO "  DMA Zone  = 0x%p-0x%p\n"
 354 #endif
 355                , _stext, _etext,
 356                __start_rodata, __end_rodata,
 357                _sdata, _edata,
 358                (void*)&init_thread_union, (void*)((int)(&init_thread_union) + 0x2000),
 359                __init_begin, __init_end,
 360                __bss_start, __bss_stop,
 361                (void*)_ramstart, (void*)memory_end
 362 #ifdef CONFIG_MTD_UCLINUX
 363                , (void*)memory_mtd_start, (void*)(memory_mtd_start + mtd_size)
 364 #endif
 365 #if DMA_UNCACHED_REGION > 0
 366                , (void*)(_ramend - DMA_UNCACHED_REGION), (void*)(_ramend)
 367 #endif
 368                );
 369
 370         /*
 371          * give all the memory to the bootmap allocator,  tell it to put the
 372          * boot mem_map at the start of memory
 373          */
 374         bootmap_size = init_bootmem_node(NODE_DATA(0), memory_start >> PAGE_SHIFT,      /* map goes here */
 375                                          PAGE_OFFSET >> PAGE_SHIFT,
 376                                          memory_end >> PAGE_SHIFT);
 377         /*
 378          * free the usable memory,  we have to make sure we do not free
 379          * the bootmem bitmap so we then reserve it after freeing it :-)
 380          */
 381         free_bootmem(memory_start, memory_end - memory_start);
 382
 383         reserve_bootmem(memory_start, bootmap_size);
 384         /*
 385          * get kmalloc into gear
 386          */
 387         paging_init();
 388
 389         /* check the size of the l1 area */
 390         l1_length = _etext_l1 - _stext_l1;
 391         if (l1_length > L1_CODE_LENGTH)
 392                 panic("L1 memory overflow\n");
 393
 394         l1_length = _ebss_l1 - _sdata_l1;
 395         if (l1_length > L1_DATA_A_LENGTH)
 396                 panic("L1 memory overflow\n");
 397
 398 #ifdef BF561_FAMILY
 399         _bfin_swrst = bfin_read_SICA_SWRST();
 400 #else
 401         _bfin_swrst = bfin_read_SWRST();
 402 #endif
 403
 404         bf53x_cache_init();
 405
 406         printk(KERN_INFO "Hardware Trace Enabled\n");
 407         bfin_write_TBUFCTL(0x03);
 408
 409         /* Copy atomic sequences to their fixed location, and sanity check that
 410            these locations are the ones that we advertise to userspace.  */
 411         memcpy((void *)FIXED_CODE_START, &fixed_code_start,
 412                FIXED_CODE_END - FIXED_CODE_START);
 413         BUG_ON((char *)&sigreturn_stub - (char *)&fixed_code_start
 414                != SIGRETURN_STUB - FIXED_CODE_START);
 415         BUG_ON((char *)&atomic_xchg32 - (char *)&fixed_code_start
 416                != ATOMIC_XCHG32 - FIXED_CODE_START);
 417         BUG_ON((char *)&atomic_cas32 - (char *)&fixed_code_start
 418                != ATOMIC_CAS32 - FIXED_CODE_START);
 419         BUG_ON((char *)&atomic_add32 - (char *)&fixed_code_start
 420                != ATOMIC_ADD32 - FIXED_CODE_START);
 421         BUG_ON((char *)&atomic_sub32 - (char *)&fixed_code_start
 422                != ATOMIC_SUB32 - FIXED_CODE_START);
 423         BUG_ON((char *)&atomic_ior32 - (char *)&fixed_code_start
 424                != ATOMIC_IOR32 - FIXED_CODE_START);
 425         BUG_ON((char *)&atomic_and32 - (char *)&fixed_code_start
 426                != ATOMIC_AND32 - FIXED_CODE_START);
 427         BUG_ON((char *)&atomic_xor32 - (char *)&fixed_code_start
 428                != ATOMIC_XOR32 - FIXED_CODE_START);
 429 }
 430
 431 static int __init topology_init(void)
 432 {
 433 #if defined (CONFIG_BF561)
 434         static struct cpu cpu[2];
 435         register_cpu(&cpu[0], 0);
 436         register_cpu(&cpu[1], 1);
 437         return 0;
 438 #else
 439         static struct cpu cpu[1];
 440         return register_cpu(cpu, 0);
 441 #endif
 442 }
 443
 444 subsys_initcall(topology_init);
 445
 446 #if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE)
 447 static u16 __init lock_kernel_check(u32 start, u32 end)
 448 {
 449         if ((start <= (u32) _stext && end >= (u32) _end)
 450             || (start >= (u32) _stext && end <= (u32) _end))
 451                 return IN_KERNEL;
 452         return 0;
 453 }
 454
 455 static unsigned short __init
 456 fill_cplbtab(struct cplb_tab *table,
 457              unsigned long start, unsigned long end,
 458              unsigned long block_size, unsigned long cplb_data)
 459 {
 460         int i;
 461
 462         switch (block_size) {
 463         case SIZE_4M:
 464                 i = 3;
 465                 break;
 466         case SIZE_1M:
 467                 i = 2;
 468                 break;
 469         case SIZE_4K:
 470                 i = 1;
 471                 break;
 472         case SIZE_1K:
 473         default:
 474                 i = 0;
 475                 break;
 476         }
 477
 478         cplb_data = (cplb_data & ~(3 << 16)) | (i << 16);
 479
 480         while ((start < end) && (table->pos < table->size)) {
 481
 482                 table->tab[table->pos++] = start;
 483
 484                 if (lock_kernel_check(start, start + block_size) == IN_KERNEL)
 485                         table->tab[table->pos++] =
 486                             cplb_data | CPLB_LOCK | CPLB_DIRTY;
 487                 else
 488                         table->tab[table->pos++] = cplb_data;
 489
 490                 start += block_size;
 491         }
 492         return 0;
 493 }
 494
 495 static unsigned short __init
 496 close_cplbtab(struct cplb_tab *table)
 497 {
 498
 499         while (table->pos < table->size) {
 500
 501                 table->tab[table->pos++] = 0;
 502                 table->tab[table->pos++] = 0; /* !CPLB_VALID */
 503         }
 504         return 0;
 505 }
 506
 507 /* helper function */
 508 static void __fill_code_cplbtab(struct cplb_tab *t, int i,
 509                                 u32 a_start, u32 a_end)
 510 {
 511         if (cplb_data[i].psize) {
 512                 fill_cplbtab(t,
 513                                 cplb_data[i].start,
 514                                 cplb_data[i].end,
 515                                 cplb_data[i].psize,
 516                                 cplb_data[i].i_conf);
 517         } else {
 518 #if (defined(CONFIG_BLKFIN_CACHE) && defined(ANOMALY_05000263))
 519                 if (i == SDRAM_KERN) {
 520                         fill_cplbtab(t,
 521                                         cplb_data[i].start,
 522                                         cplb_data[i].end,
 523                                         SIZE_4M,
 524                                         cplb_data[i].i_conf);
 525                 } else
 526 #endif
 527                 {
 528                         fill_cplbtab(t,
 529                                         cplb_data[i].start,
 530                                         a_start,
 531                                         SIZE_1M,
 532                                         cplb_data[i].i_conf);
 533                         fill_cplbtab(t,
 534                                         a_start,
 535                                         a_end,
 536                                         SIZE_4M,
 537                                         cplb_data[i].i_conf);
 538                         fill_cplbtab(t, a_end,
 539                                         cplb_data[i].end,
 540                                         SIZE_1M,
 541                                         cplb_data[i].i_conf);
 542                 }
 543         }
 544 }
 545
 546 static void __fill_data_cplbtab(struct cplb_tab *t, int i,
 547                                 u32 a_start, u32 a_end)
 548 {
 549         if (cplb_data[i].psize) {
 550                 fill_cplbtab(t,
 551                                 cplb_data[i].start,
 552                                 cplb_data[i].end,
 553                                 cplb_data[i].psize,
 554                                 cplb_data[i].d_conf);
 555         } else {
 556                 fill_cplbtab(t,
 557                                 cplb_data[i].start,
 558                                 a_start, SIZE_1M,
 559                                 cplb_data[i].d_conf);
 560                 fill_cplbtab(t, a_start,
 561                                 a_end, SIZE_4M,
 562                                 cplb_data[i].d_conf);
 563                 fill_cplbtab(t, a_end,
 564                                 cplb_data[i].end,
 565                                 SIZE_1M,
 566                                 cplb_data[i].d_conf);
 567         }
 568 }
 569 static void __init generate_cpl_tables(void)
 570 {
 571
 572         u16 i, j, process;
 573         u32 a_start, a_end, as, ae, as_1m;
 574
 575         struct cplb_tab *t_i = NULL;
 576         struct cplb_tab *t_d = NULL;
 577         struct s_cplb cplb;
 578
 579         cplb.init_i.size = MAX_CPLBS;
 580         cplb.init_d.size = MAX_CPLBS;
 581         cplb.switch_i.size = MAX_SWITCH_I_CPLBS;
 582         cplb.switch_d.size = MAX_SWITCH_D_CPLBS;
 583
 584         cplb.init_i.pos = 0;
 585         cplb.init_d.pos = 0;
 586         cplb.switch_i.pos = 0;
 587         cplb.switch_d.pos = 0;
 588
 589         cplb.init_i.tab = icplb_table;
 590         cplb.init_d.tab = dcplb_table;
 591         cplb.switch_i.tab = ipdt_table;
 592         cplb.switch_d.tab = dpdt_table;
 593
 594         cplb_data[SDRAM_KERN].end = memory_end;
 595
 596 #ifdef CONFIG_MTD_UCLINUX
 597         cplb_data[SDRAM_RAM_MTD].start = memory_mtd_start;
 598         cplb_data[SDRAM_RAM_MTD].end = memory_mtd_start + mtd_size;
 599         cplb_data[SDRAM_RAM_MTD].valid = mtd_size > 0;
 600 # if defined(CONFIG_ROMFS_FS)
 601         cplb_data[SDRAM_RAM_MTD].attr |= I_CPLB;
 602
 603         /*
 604          * The ROMFS_FS size is often not multiple of 1MB.
 605          * This can cause multiple CPLB sets covering the same memory area.
 606          * This will then cause multiple CPLB hit exceptions.
 607          * Workaround: We ensure a contiguous memory area by extending the kernel
 608          * memory section over the mtd section.
 609          * For ROMFS_FS memory must be covered with ICPLBs anyways.
 610          * So there is no difference between kernel and mtd memory setup.
 611          */
 612
 613         cplb_data[SDRAM_KERN].end = memory_mtd_start + mtd_size;;
 614         cplb_data[SDRAM_RAM_MTD].valid = 0;
 615
 616 # endif
 617 #else
 618         cplb_data[SDRAM_RAM_MTD].valid = 0;
 619 #endif
 620
 621         cplb_data[SDRAM_DMAZ].start = _ramend - DMA_UNCACHED_REGION;
 622         cplb_data[SDRAM_DMAZ].end = _ramend;
 623
 624         cplb_data[RES_MEM].start = _ramend;
 625         cplb_data[RES_MEM].end = physical_mem_end;
 626
 627         if (reserved_mem_dcache_on)
 628                 cplb_data[RES_MEM].d_conf = SDRAM_DGENERIC;
 629         else
 630                 cplb_data[RES_MEM].d_conf = SDRAM_DNON_CHBL;
 631
 632         if (reserved_mem_icache_on)
 633                 cplb_data[RES_MEM].i_conf = SDRAM_IGENERIC;
 634         else
 635                 cplb_data[RES_MEM].i_conf = SDRAM_INON_CHBL;
 636
 637         for (i = ZERO_P; i <= L2_MEM; i++) {
 638                 if (!cplb_data[i].valid)
 639                         continue;
 640
 641                 as_1m = cplb_data[i].start % SIZE_1M;
 642
 643                 /*
 644                  * We need to make sure all sections are properly 1M aligned
 645                  * However between Kernel Memory and the Kernel mtd section,
 646                  * depending on the rootfs size, there can be overlapping
 647                  * memory areas.
 648                  */
 649
 650                 if (as_1m && i != L1I_MEM && i != L1D_MEM) {
 651 #ifdef CONFIG_MTD_UCLINUX
 652                         if (i == SDRAM_RAM_MTD) {
 653                                 if ((cplb_data[SDRAM_KERN].end + 1) >
 654                                                 cplb_data[SDRAM_RAM_MTD].start)
 655                                         cplb_data[SDRAM_RAM_MTD].start =
 656                                                 (cplb_data[i].start &
 657                                                  (-2*SIZE_1M)) + SIZE_1M;
 658                                 else
 659                                         cplb_data[SDRAM_RAM_MTD].start =
 660                                                 (cplb_data[i].start &
 661                                                  (-2*SIZE_1M));
 662                         } else
 663 #endif
 664                                 printk(KERN_WARNING
 665                                         "Unaligned Start of %s at 0x%X\n",
 666                                         cplb_data[i].name, cplb_data[i].start);
 667                 }
 668
 669                 as = cplb_data[i].start % SIZE_4M;
 670                 ae = cplb_data[i].end % SIZE_4M;
 671
 672                 if (as)
 673                         a_start = cplb_data[i].start + (SIZE_4M - (as));
 674                 else
 675                         a_start = cplb_data[i].start;
 676
 677                 a_end = cplb_data[i].end - ae;
 678
 679                 for (j = INITIAL_T; j <= SWITCH_T; j++) {
 680
 681                         switch (j) {
 682                         case INITIAL_T:
 683                                 if (cplb_data[i].attr & INITIAL_T) {
 684                                         t_i = &cplb.init_i;
 685                                         t_d = &cplb.init_d;
 686                                         process = 1;
 687                                 } else
 688                                         process = 0;
 689                                 break;
 690                         case SWITCH_T:
 691                                 if (cplb_data[i].attr & SWITCH_T) {
 692                                         t_i = &cplb.switch_i;
 693                                         t_d = &cplb.switch_d;
 694                                         process = 1;
 695                                 } else
 696                                         process = 0;
 697                                 break;
 698                         default:
 699                                         process = 0;
 700                                 break;
 701                         }
 702
 703                         if (!process)
 704                                 continue;
 705                         if (cplb_data[i].attr & I_CPLB)
 706                                 __fill_code_cplbtab(t_i, i, a_start, a_end);
 707
 708                         if (cplb_data[i].attr & D_CPLB)
 709                                 __fill_data_cplbtab(t_d, i, a_start, a_end);
 710                 }
 711         }
 712
 713 /* close tables */
 714
 715         close_cplbtab(&cplb.init_i);
 716         close_cplbtab(&cplb.init_d);
 717
 718         cplb.init_i.tab[cplb.init_i.pos] = -1;
 719         cplb.init_d.tab[cplb.init_d.pos] = -1;
 720         cplb.switch_i.tab[cplb.switch_i.pos] = -1;
 721         cplb.switch_d.tab[cplb.switch_d.pos] = -1;
 722
 723 }
 724
 725 #endif
 726
 727 static u_long get_vco(void)
 728 {
 729         u_long msel;
 730         u_long vco;
 731
 732         msel = (bfin_read_PLL_CTL() >> 9) & 0x3F;
 733         if (0 == msel)
 734                 msel = 64;
 735
 736         vco = CONFIG_CLKIN_HZ;
 737         vco >>= (1 & bfin_read_PLL_CTL());      /* DF bit */
 738         vco = msel * vco;
 739         return vco;
 740 }
 741
 742 /*Get the Core clock*/
 743 u_long get_cclk(void)
 744 {
 745         u_long csel, ssel;
 746         if (bfin_read_PLL_STAT() & 0x1)
 747                 return CONFIG_CLKIN_HZ;
 748
 749         ssel = bfin_read_PLL_DIV();
 750         csel = ((ssel >> 4) & 0x03);
 751         ssel &= 0xf;
 752         if (ssel && ssel < (1 << csel)) /* SCLK > CCLK */
 753                 return get_vco() / ssel;
 754         return get_vco() >> csel;
 755 }
 756
 757 EXPORT_SYMBOL(get_cclk);
 758
 759 /* Get the System clock */
 760 u_long get_sclk(void)
 761 {
 762         u_long ssel;
 763
 764         if (bfin_read_PLL_STAT() & 0x1)
 765                 return CONFIG_CLKIN_HZ;
 766
 767         ssel = (bfin_read_PLL_DIV() & 0xf);
 768         if (0 == ssel) {
 769                 printk(KERN_WARNING "Invalid System Clock\n");
 770                 ssel = 1;
 771         }
 772
 773         return get_vco() / ssel;
 774 }
 775
 776 EXPORT_SYMBOL(get_sclk);
 777
 778 /*
 779  *      Get CPU information for use by the procfs.
 780  */
 781 static int show_cpuinfo(struct seq_file *m, void *v)
 782 {
 783         char *cpu, *mmu, *fpu, *name;
 784         uint32_t revid;
 785
 786         u_long cclk = 0, sclk = 0;
 787         u_int dcache_size = 0, dsup_banks = 0;
 788
 789         cpu = CPU;
 790         mmu = "none";
 791         fpu = "none";
 792         revid = bfin_revid();
 793         name = bfin_board_name;
 794
 795         cclk = get_cclk();
 796         sclk = get_sclk();
 797
 798         seq_printf(m, "CPU:\t\tADSP-%s Rev. 0.%d\n"
 799                    "MMU:\t\t%s\n"
 800                    "FPU:\t\t%s\n"
 801                    "Core Clock:\t%9lu Hz\n"
 802                    "System Clock:\t%9lu Hz\n"
 803                    "BogoMips:\t%lu.%02lu\n"
 804                    "Calibration:\t%lu loops\n",
 805                    cpu, revid, mmu, fpu,
 806                    cclk,
 807                    sclk,
 808                    (loops_per_jiffy * HZ) / 500000,
 809                    ((loops_per_jiffy * HZ) / 5000) % 100,
 810                    (loops_per_jiffy * HZ));
 811         seq_printf(m, "Board Name:\t%s\n", name);
 812         seq_printf(m, "Board Memory:\t%ld MB\n", physical_mem_end >> 20);
 813         seq_printf(m, "Kernel Memory:\t%ld MB\n", (unsigned long)_ramend >> 20);
 814         if (bfin_read_IMEM_CONTROL() & (ENICPLB | IMC))
 815                 seq_printf(m, "I-CACHE:\tON\n");
 816         else
 817                 seq_printf(m, "I-CACHE:\tOFF\n");
 818         if ((bfin_read_DMEM_CONTROL()) & (ENDCPLB | DMC_ENABLE))
 819                 seq_printf(m, "D-CACHE:\tON"
 820 #if defined CONFIG_BLKFIN_WB
 821                            " (write-back)"
 822 #elif defined CONFIG_BLKFIN_WT
 823                            " (write-through)"
 824 #endif
 825                            "\n");
 826         else
 827                 seq_printf(m, "D-CACHE:\tOFF\n");
 828
 829
 830         switch(bfin_read_DMEM_CONTROL() & (1 << DMC0_P | 1 << DMC1_P)) {
 831                 case ACACHE_BSRAM:
 832                         seq_printf(m, "DBANK-A:\tCACHE\n" "DBANK-B:\tSRAM\n");
 833                         dcache_size = 16;
 834                         dsup_banks = 1;
 835                         break;
 836                 case ACACHE_BCACHE:
 837                         seq_printf(m, "DBANK-A:\tCACHE\n" "DBANK-B:\tCACHE\n");
 838                         dcache_size = 32;
 839                         dsup_banks = 2;
 840                         break;
 841                 case ASRAM_BSRAM:
 842                         seq_printf(m, "DBANK-A:\tSRAM\n" "DBANK-B:\tSRAM\n");
 843                         dcache_size = 0;
 844                         dsup_banks = 0;
 845                         break;
 846                 default:
 847                 break;
 848         }
 849
 850
 851         seq_printf(m, "I-CACHE Size:\t%dKB\n", BLKFIN_ICACHESIZE / 1024);
 852         seq_printf(m, "D-CACHE Size:\t%dKB\n", dcache_size);
 853         seq_printf(m, "I-CACHE Setup:\t%d Sub-banks/%d Ways, %d Lines/Way\n",
 854                    BLKFIN_ISUBBANKS, BLKFIN_IWAYS, BLKFIN_ILINES);
 855         seq_printf(m,
 856                    "D-CACHE Setup:\t%d Super-banks/%d Sub-banks/%d Ways, %d Lines/Way\n",
 857                    dsup_banks, BLKFIN_DSUBBANKS, BLKFIN_DWAYS,
 858                    BLKFIN_DLINES);
 859 #ifdef CONFIG_BLKFIN_CACHE_LOCK
 860         switch (read_iloc()) {
 861         case WAY0_L:
 862                 seq_printf(m, "Way0 Locked-Down\n");
 863                 break;
 864         case WAY1_L:
 865                 seq_printf(m, "Way1 Locked-Down\n");
 866                 break;
 867         case WAY01_L:
 868                 seq_printf(m, "Way0,Way1 Locked-Down\n");
 869                 break;
 870         case WAY2_L:
 871                 seq_printf(m, "Way2 Locked-Down\n");
 872                 break;
 873         case WAY02_L:
 874                 seq_printf(m, "Way0,Way2 Locked-Down\n");
 875                 break;
 876         case WAY12_L:
 877                 seq_printf(m, "Way1,Way2 Locked-Down\n");
 878                 break;
 879         case WAY012_L:
 880                 seq_printf(m, "Way0,Way1 & Way2 Locked-Down\n");
 881                 break;
 882         case WAY3_L:
 883                 seq_printf(m, "Way3 Locked-Down\n");
 884                 break;
 885         case WAY03_L:
 886                 seq_printf(m, "Way0,Way3 Locked-Down\n");
 887                 break;
 888         case WAY13_L:
 889                 seq_printf(m, "Way1,Way3 Locked-Down\n");
 890                 break;
 891         case WAY013_L:
 892                 seq_printf(m, "Way 0,Way1,Way3 Locked-Down\n");
 893                 break;
 894         case WAY32_L:
 895                 seq_printf(m, "Way3,Way2 Locked-Down\n");
 896                 break;
 897         case WAY320_L:
 898                 seq_printf(m, "Way3,Way2,Way0 Locked-Down\n");
 899                 break;
 900         case WAY321_L:
 901                 seq_printf(m, "Way3,Way2,Way1 Locked-Down\n");
 902                 break;
 903         case WAYALL_L:
 904                 seq_printf(m, "All Ways are locked\n");
 905                 break;
 906         default:
 907                 seq_printf(m, "No Ways are locked\n");
 908         }
 909 #endif
 910         return 0;
 911 }
 912
 913 static void *c_start(struct seq_file *m, loff_t *pos)
 914 {
 915         return *pos < NR_CPUS ? ((void *)0x12345678) : NULL;
 916 }
 917
 918 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
 919 {
 920         ++*pos;
 921         return c_start(m, pos);
 922 }
 923
 924 static void c_stop(struct seq_file *m, void *v)
 925 {
 926 }
 927
 928 struct seq_operations cpuinfo_op = {
 929         .start = c_start,
 930         .next = c_next,
 931         .stop = c_stop,
 932         .show = show_cpuinfo,
 933 };
 934
 935 void __init cmdline_init(const char *r0)
 936 {
 937         if (r0)
 938                 strncpy(command_line, r0, COMMAND_LINE_SIZE);
 939 }