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   1 /*
   2  * Blackfin CPLB initialization
   3  *
   4  *               Copyright 2004-2007 Analog Devices Inc.
   5  *
   6  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, see the file COPYING, or write
  20  * to the Free Software Foundation, Inc.,
  21  * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  22  */
  23 #include <linux/module.h>
  24
  25 #include <asm/blackfin.h>
  26 #include <asm/cacheflush.h>
  27 #include <asm/cplb.h>
  28 #include <asm/cplbinit.h>
  29
  30 u_long icplb_tables[NR_CPUS][CPLB_TBL_ENTRIES+1];
  31 u_long dcplb_tables[NR_CPUS][CPLB_TBL_ENTRIES+1];
  32
  33 #ifdef CONFIG_CPLB_SWITCH_TAB_L1
  34 #define PDT_ATTR __attribute__((l1_data))
  35 #else
  36 #define PDT_ATTR
  37 #endif
  38
  39 u_long ipdt_tables[NR_CPUS][MAX_SWITCH_I_CPLBS+1] PDT_ATTR;
  40 u_long dpdt_tables[NR_CPUS][MAX_SWITCH_D_CPLBS+1] PDT_ATTR;
  41 #ifdef CONFIG_CPLB_INFO
  42 u_long ipdt_swapcount_tables[NR_CPUS][MAX_SWITCH_I_CPLBS] PDT_ATTR;
  43 u_long dpdt_swapcount_tables[NR_CPUS][MAX_SWITCH_D_CPLBS] PDT_ATTR;
  44 #endif
  45
  46 struct s_cplb {
  47         struct cplb_tab init_i;
  48         struct cplb_tab init_d;
  49         struct cplb_tab switch_i;
  50         struct cplb_tab switch_d;
  51 };
  52
  53 #if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
  54 static struct cplb_desc cplb_data[] = {
  55         {
  56                 .start = 0,
  57                 .end = SIZE_1K,
  58                 .psize = SIZE_1K,
  59                 .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
  60                 .i_conf = SDRAM_OOPS,
  61                 .d_conf = SDRAM_OOPS,
  62 #if defined(CONFIG_DEBUG_HUNT_FOR_ZERO)
  63                 .valid = 1,
  64 #else
  65                 .valid = 0,
  66 #endif
  67                 .name = "Zero Pointer Guard Page",
  68         },
  69         {
  70                 .start = 0,     /* dyanmic */
  71                 .end = 0,       /* dynamic */
  72                 .psize = SIZE_4M,
  73                 .attr = INITIAL_T | SWITCH_T | I_CPLB,
  74                 .i_conf = L1_IMEMORY,
  75                 .d_conf = 0,
  76                 .valid = 1,
  77                 .name = "L1 I-Memory",
  78         },
  79         {
  80                 .start = 0,     /* dynamic */
  81                 .end = 0,       /* dynamic */
  82                 .psize = SIZE_4M,
  83                 .attr = INITIAL_T | SWITCH_T | D_CPLB,
  84                 .i_conf = 0,
  85                 .d_conf = L1_DMEMORY,
  86 #if ((L1_DATA_A_LENGTH > 0) || (L1_DATA_B_LENGTH > 0))
  87                 .valid = 1,
  88 #else
  89                 .valid = 0,
  90 #endif
  91                 .name = "L1 D-Memory",
  92         },
  93         {
  94                 .start = L2_START,
  95                 .end = L2_START + L2_LENGTH,
  96                 .psize = SIZE_1M,
  97                 .attr = L2_ATTR,
  98                 .i_conf = L2_IMEMORY,
  99                 .d_conf = L2_DMEMORY,
 100                 .valid = (L2_LENGTH > 0),
 101                 .name = "L2 Memory",
 102         },
 103         {
 104                 .start = 0,
 105                 .end = 0,  /* dynamic */
 106                 .psize = 0,
 107                 .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
 108                 .i_conf = SDRAM_IGENERIC,
 109                 .d_conf = SDRAM_DGENERIC,
 110                 .valid = 1,
 111                 .name = "Kernel Memory",
 112         },
 113         {
 114                 .start = 0, /* dynamic */
 115                 .end = 0, /* dynamic */
 116                 .psize = 0,
 117                 .attr = INITIAL_T | SWITCH_T | D_CPLB,
 118                 .i_conf = SDRAM_IGENERIC,
 119                 .d_conf = SDRAM_DNON_CHBL,
 120                 .valid = 1,
 121                 .name = "uClinux MTD Memory",
 122         },
 123         {
 124                 .start = 0, /* dynamic */
 125                 .end = 0,   /* dynamic */
 126                 .psize = SIZE_1M,
 127                 .attr = INITIAL_T | SWITCH_T | D_CPLB,
 128                 .d_conf = SDRAM_DNON_CHBL,
 129                 .valid = 1,
 130                 .name = "Uncached DMA Zone",
 131         },
 132         {
 133                 .start = 0, /* dynamic */
 134                 .end = 0, /* dynamic */
 135                 .psize = 0,
 136                 .attr = SWITCH_T | D_CPLB,
 137                 .i_conf = 0, /* dynamic */
 138                 .d_conf = 0, /* dynamic */
 139                 .valid = 1,
 140                 .name = "Reserved Memory",
 141         },
 142         {
 143                 .start = ASYNC_BANK0_BASE,
 144                 .end = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE,
 145                 .psize = 0,
 146                 .attr = SWITCH_T | D_CPLB,
 147                 .d_conf = SDRAM_EBIU,
 148                 .valid = 1,
 149                 .name = "Asynchronous Memory Banks",
 150         },
 151         {
 152                 .start = BOOT_ROM_START,
 153                 .end = BOOT_ROM_START + BOOT_ROM_LENGTH,
 154                 .psize = SIZE_1M,
 155                 .attr = SWITCH_T | I_CPLB | D_CPLB,
 156                 .i_conf = SDRAM_IGENERIC,
 157                 .d_conf = SDRAM_DGENERIC,
 158                 .valid = 1,
 159                 .name = "On-Chip BootROM",
 160         },
 161 };
 162
 163 static u16 __init lock_kernel_check(u32 start, u32 end)
 164 {
 165         if (start >= (u32)_end || end <= (u32)_stext)
 166                 return 0;
 167
 168         /* This cplb block overlapped with kernel area. */
 169         return IN_KERNEL;
 170 }
 171
 172 static unsigned short __init
 173 fill_cplbtab(struct cplb_tab *table,
 174              unsigned long start, unsigned long end,
 175              unsigned long block_size, unsigned long cplb_data)
 176 {
 177         int i;
 178
 179         switch (block_size) {
 180         case SIZE_4M:
 181                 i = 3;
 182                 break;
 183         case SIZE_1M:
 184                 i = 2;
 185                 break;
 186         case SIZE_4K:
 187                 i = 1;
 188                 break;
 189         case SIZE_1K:
 190         default:
 191                 i = 0;
 192                 break;
 193         }
 194
 195         cplb_data = (cplb_data & ~(3 << 16)) | (i << 16);
 196
 197         while ((start < end) && (table->pos < table->size)) {
 198
 199                 table->tab[table->pos++] = start;
 200
 201                 if (lock_kernel_check(start, start + block_size) == IN_KERNEL)
 202                         table->tab[table->pos++] =
 203                             cplb_data | CPLB_LOCK | CPLB_DIRTY;
 204                 else
 205                         table->tab[table->pos++] = cplb_data;
 206
 207                 start += block_size;
 208         }
 209         return 0;
 210 }
 211
 212 static unsigned short __init
 213 close_cplbtab(struct cplb_tab *table)
 214 {
 215
 216         while (table->pos < table->size) {
 217
 218                 table->tab[table->pos++] = 0;
 219                 table->tab[table->pos++] = 0; /* !CPLB_VALID */
 220         }
 221         return 0;
 222 }
 223
 224 /* helper function */
 225 static void __init
 226 __fill_code_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_end)
 227 {
 228         if (cplb_data[i].psize) {
 229                 fill_cplbtab(t,
 230                                 cplb_data[i].start,
 231                                 cplb_data[i].end,
 232                                 cplb_data[i].psize,
 233                                 cplb_data[i].i_conf);
 234         } else {
 235 #if defined(CONFIG_BFIN_ICACHE)
 236                 if (ANOMALY_05000263 && i == SDRAM_KERN) {
 237                         fill_cplbtab(t,
 238                                         cplb_data[i].start,
 239                                         cplb_data[i].end,
 240                                         SIZE_4M,
 241                                         cplb_data[i].i_conf);
 242                 } else
 243 #endif
 244                 {
 245                         fill_cplbtab(t,
 246                                         cplb_data[i].start,
 247                                         a_start,
 248                                         SIZE_1M,
 249                                         cplb_data[i].i_conf);
 250                         fill_cplbtab(t,
 251                                         a_start,
 252                                         a_end,
 253                                         SIZE_4M,
 254                                         cplb_data[i].i_conf);
 255                         fill_cplbtab(t, a_end,
 256                                         cplb_data[i].end,
 257                                         SIZE_1M,
 258                                         cplb_data[i].i_conf);
 259                 }
 260         }
 261 }
 262
 263 static void __init
 264 __fill_data_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_end)
 265 {
 266         if (cplb_data[i].psize) {
 267                 fill_cplbtab(t,
 268                                 cplb_data[i].start,
 269                                 cplb_data[i].end,
 270                                 cplb_data[i].psize,
 271                                 cplb_data[i].d_conf);
 272         } else {
 273                 fill_cplbtab(t,
 274                                 cplb_data[i].start,
 275                                 a_start, SIZE_1M,
 276                                 cplb_data[i].d_conf);
 277                 fill_cplbtab(t, a_start,
 278                                 a_end, SIZE_4M,
 279                                 cplb_data[i].d_conf);
 280                 fill_cplbtab(t, a_end,
 281                                 cplb_data[i].end,
 282                                 SIZE_1M,
 283                                 cplb_data[i].d_conf);
 284         }
 285 }
 286
 287 void __init generate_cplb_tables_cpu(unsigned int cpu)
 288 {
 289
 290         u16 i, j, process;
 291         u32 a_start, a_end, as, ae, as_1m;
 292
 293         struct cplb_tab *t_i = NULL;
 294         struct cplb_tab *t_d = NULL;
 295         struct s_cplb cplb;
 296
 297         printk(KERN_INFO "NOMPU: setting up cplb tables for global access\n");
 298
 299         cplb.init_i.size = CPLB_TBL_ENTRIES;
 300         cplb.init_d.size = CPLB_TBL_ENTRIES;
 301         cplb.switch_i.size = MAX_SWITCH_I_CPLBS;
 302         cplb.switch_d.size = MAX_SWITCH_D_CPLBS;
 303
 304         cplb.init_i.pos = 0;
 305         cplb.init_d.pos = 0;
 306         cplb.switch_i.pos = 0;
 307         cplb.switch_d.pos = 0;
 308
 309         cplb.init_i.tab = icplb_tables[cpu];
 310         cplb.init_d.tab = dcplb_tables[cpu];
 311         cplb.switch_i.tab = ipdt_tables[cpu];
 312         cplb.switch_d.tab = dpdt_tables[cpu];
 313
 314         cplb_data[L1I_MEM].start = get_l1_code_start_cpu(cpu);
 315         cplb_data[L1I_MEM].end = cplb_data[L1I_MEM].start + L1_CODE_LENGTH;
 316         cplb_data[L1D_MEM].start = get_l1_data_a_start_cpu(cpu);
 317         cplb_data[L1D_MEM].end = get_l1_data_b_start_cpu(cpu) + L1_DATA_B_LENGTH;
 318         cplb_data[SDRAM_KERN].end = memory_end;
 319
 320 #ifdef CONFIG_MTD_UCLINUX
 321         cplb_data[SDRAM_RAM_MTD].start = memory_mtd_start;
 322         cplb_data[SDRAM_RAM_MTD].end = memory_mtd_start + mtd_size;
 323         cplb_data[SDRAM_RAM_MTD].valid = mtd_size > 0;
 324 # if defined(CONFIG_ROMFS_FS)
 325         cplb_data[SDRAM_RAM_MTD].attr |= I_CPLB;
 326
 327         /*
 328          * The ROMFS_FS size is often not multiple of 1MB.
 329          * This can cause multiple CPLB sets covering the same memory area.
 330          * This will then cause multiple CPLB hit exceptions.
 331          * Workaround: We ensure a contiguous memory area by extending the kernel
 332          * memory section over the mtd section.
 333          * For ROMFS_FS memory must be covered with ICPLBs anyways.
 334          * So there is no difference between kernel and mtd memory setup.
 335          */
 336
 337         cplb_data[SDRAM_KERN].end = memory_mtd_start + mtd_size;;
 338         cplb_data[SDRAM_RAM_MTD].valid = 0;
 339
 340 # endif
 341 #else
 342         cplb_data[SDRAM_RAM_MTD].valid = 0;
 343 #endif
 344
 345         cplb_data[SDRAM_DMAZ].start = _ramend - DMA_UNCACHED_REGION;
 346         cplb_data[SDRAM_DMAZ].end = _ramend;
 347
 348         cplb_data[RES_MEM].start = _ramend;
 349         cplb_data[RES_MEM].end = physical_mem_end;
 350
 351         if (reserved_mem_dcache_on)
 352                 cplb_data[RES_MEM].d_conf = SDRAM_DGENERIC;
 353         else
 354                 cplb_data[RES_MEM].d_conf = SDRAM_DNON_CHBL;
 355
 356         if (reserved_mem_icache_on)
 357                 cplb_data[RES_MEM].i_conf = SDRAM_IGENERIC;
 358         else
 359                 cplb_data[RES_MEM].i_conf = SDRAM_INON_CHBL;
 360
 361         for (i = ZERO_P; i < ARRAY_SIZE(cplb_data); ++i) {
 362                 if (!cplb_data[i].valid)
 363                         continue;
 364
 365                 as_1m = cplb_data[i].start % SIZE_1M;
 366
 367                 /* We need to make sure all sections are properly 1M aligned
 368                  * However between Kernel Memory and the Kernel mtd section, depending on the
 369                  * rootfs size, there can be overlapping memory areas.
 370                  */
 371
 372                 if (as_1m && i != L1I_MEM && i != L1D_MEM) {
 373 #ifdef CONFIG_MTD_UCLINUX
 374                         if (i == SDRAM_RAM_MTD) {
 375                                 if ((cplb_data[SDRAM_KERN].end + 1) > cplb_data[SDRAM_RAM_MTD].start)
 376                                         cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M)) + SIZE_1M;
 377                                 else
 378                                         cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M));
 379                         } else
 380 #endif
 381                                 printk(KERN_WARNING "Unaligned Start of %s at 0x%X\n",
 382                                        cplb_data[i].name, cplb_data[i].start);
 383                 }
 384
 385                 as = cplb_data[i].start % SIZE_4M;
 386                 ae = cplb_data[i].end % SIZE_4M;
 387
 388                 if (as)
 389                         a_start = cplb_data[i].start + (SIZE_4M - (as));
 390                 else
 391                         a_start = cplb_data[i].start;
 392
 393                 a_end = cplb_data[i].end - ae;
 394
 395                 for (j = INITIAL_T; j <= SWITCH_T; j++) {
 396
 397                         switch (j) {
 398                         case INITIAL_T:
 399                                 if (cplb_data[i].attr & INITIAL_T) {
 400                                         t_i = &cplb.init_i;
 401                                         t_d = &cplb.init_d;
 402                                         process = 1;
 403                                 } else
 404                                         process = 0;
 405                                 break;
 406                         case SWITCH_T:
 407                                 if (cplb_data[i].attr & SWITCH_T) {
 408                                         t_i = &cplb.switch_i;
 409                                         t_d = &cplb.switch_d;
 410                                         process = 1;
 411                                 } else
 412                                         process = 0;
 413                                 break;
 414                         default:
 415                                         process = 0;
 416                                 break;
 417                         }
 418
 419                         if (!process)
 420                                 continue;
 421                         if (cplb_data[i].attr & I_CPLB)
 422                                 __fill_code_cplbtab(t_i, i, a_start, a_end);
 423
 424                         if (cplb_data[i].attr & D_CPLB)
 425                                 __fill_data_cplbtab(t_d, i, a_start, a_end);
 426                 }
 427         }
 428
 429 /* close tables */
 430
 431         close_cplbtab(&cplb.init_i);
 432         close_cplbtab(&cplb.init_d);
 433
 434         cplb.init_i.tab[cplb.init_i.pos] = -1;
 435         cplb.init_d.tab[cplb.init_d.pos] = -1;
 436         cplb.switch_i.tab[cplb.switch_i.pos] = -1;
 437         cplb.switch_d.tab[cplb.switch_d.pos] = -1;
 438
 439 }
 440 #endif
 441